KR20160080650A - Time interleaved pipeline SAR ADC for minimizing channel offset mismatch - Google Patents

Abstract

The present invention relates to a time interleaved pipeline SAR ADC for reducing an inter-channel offset mismatch, comprising: a first stage which constitutes a plurality of channels by using a time interleaving SAR ADC according to the number of first bits; a second stage which constitutes a plurality of channels by using a time interleaving SAR ADC according to the number of second bits; and a residue voltage amplifier which receives a residue voltage per channel of the first stage which is shared between channels and outputs the residue voltage per channel to the second stage after amplification. The present invention is designed to solve the problem of the increase in an element area and power consumption.

Description

[0001] The present invention relates to a time interleaved pipeline SAR ADC for minimizing the channel mismatch between channels,

The present invention relates to a pipelined SAR (Successive Approximation Register Analog to Digital Converter) technique, and more particularly to a time-interleaved pipelined SAR ADC with a problem of deteriorating performance due to mismatching between channels. .

An analog-to-digital converter (ADC) for converting an analog signal to a digital signal is indispensable to the analog front end (AFE) of a high-definition imaging system. In particular, a high-resolution display system for a mobile phone requires an ADC having a resolution of 10 bits or more and an operating speed of 80 ms / s or more. In order to satisfy such a requirement, a pipeline structure ADC has been mainly used.

On the other hand, research on SAR ADCs based on digital circuits has been actively pursued as the process technology has been developed, but the operation speed of the internal circuits increases as the resolution increases. To overcome these shortcomings, it is possible to implement a pipelined architecture and a time-interleaved (TI) structure that connects several identical ADCs in parallel to achieve high-resolution and high-speed ADCs. There is a problem that the performance of the entire ADC is deteriorated due to offset mismatch between channels, gain mismatch, and sampling timing mismatch. In order to solve the mismatch problems between various channels, a correction technique is necessary, but additional timing and complicated circuits are required, and there is a disadvantage that an area is increased. The following prior art documents introduce a pipelined ADC to which such a self correction technique is applied.

P. Bogner, F. Kuttner, C. Kropf, T. Hartig, M. Burian, and E. Hermann, "A 14b 100 MS / s digitally self-calibrated pipelined ADC in 0.13um CMOS," in ISSCC Dig. Tech Papers, Feb. 2006, pp. 832-841.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pipelined SAR ADC of a time interleaving structure that overcomes the limitations of performance degradation due to channel mismatch incompatibility caused by a comparator, The need for additional timing, increased circuit complexity, increased device area and power consumption, which may arise when utilizing additional correction means for the device.

According to an aspect of the present invention, there is provided a pipeline SAR ADC having a time-interleaved structure according to an embodiment of the present invention. The pipeline SAR ADC includes a plurality of channels A first stage which constitutes the first stage; A second stage for constructing the plurality of channels using a time interleaving SAR ADC according to a second number of bits; And a residue amplifier that is shared between the channels, receives and amplifies a residue voltage of each channel of the first stage, and outputs the amplified residue voltage to the second stage on a channel-by-channel basis.

The pipelined SAR ADC of the temporal interleaving structure according to an embodiment comprises a comparator each of which performs a comparison operation required for the SAR operation of a channel in the SAR ADC of the first stage and the second stage, The offset mismatch between the channels can be prevented by sharing the comparator.

In a pipelined SAR ADC of the time interleaving structure according to an embodiment, by generating a sampling clock used in each channel in synchronization with one reference clock, it is possible to prevent mismatching of input sampling signals between channels have.

In a pipelined SAR ADC of the time interleaving structure according to an embodiment, the comparator constituting the first stage comprises: a number of input pairs as the number of the channels; And a pull-down switch disposed at a drain node of the input terminal pair to reduce a kick-back noise by performing a buffer function .

In a pipelined SAR ADC of the time interleaving structure according to an embodiment, the comparator constituting the first stage may further include an additional latch that increases the operating speed of the comparator.

In a pipelined SAR ADC of the time interleaving scheme according to an embodiment, the comparator constituting the first stage may automatically remove a memory effect occurring at the input of the comparator during a sampling operation.

In a pipelined SAR ADC of the time interleaving structure according to an embodiment, the comparator constituting the second stage comprises: one input pair configured such that the plurality of channels are alternately connected by a switch; And a pull-down switch disposed at a drain node of the input terminal pair to reduce a kick-back noise by performing a buffer function.

In a pipelined SAR ADC of the time interleaving structure according to an embodiment, the comparator constituting the second stage may further include an additional latch for increasing the operating speed of the comparator.

In the pipelined SAR ADC of the time interleaving structure according to the embodiment, the comparator constituting the second stage may remove the memory effect by resetting the input terminal after a SAR operation of each channel at predetermined intervals.

According to another aspect of the present invention, there is provided a pipelined SAR ADC having a time-interleaved structure according to another embodiment of the present invention. The pipelined SAR ADC has a time interleaving SAR ADC according to a first number of bits, A first stage which constitutes the first stage; A second stage for constructing the plurality of channels using a time interleaving SAR ADC according to a second number of bits; And a residue voltage amplifier that is shared between the first and second stages and receives and amplifies a residue voltage of each channel of the first stage and outputs the amplified residue voltage to the second stage for each channel, Scaling method in which only half of the input signal range input to the first stage is output to the second stage, thereby reducing power consumption by the amplifier.

In the pipelined SAR ADC of the time interleaving structure according to another embodiment, the residual voltage amplifier includes a pair of input stages separated by a channel, but can secure a reset time of a non-operating channel, thereby eliminating the memory effect .

In a pipelined SAR ADC of the time interleaving structure according to another embodiment, the residual voltage amplifier comprises: a first amplifier of a gain-boosting structure for increasing voltage gain; And a second amplifier of a common-source structure having a signal swing range above a reference value.

In a pipelined SAR ADC of the time interleaving structure according to another embodiment, the SAR ADC constituting the second stage may further comprise a capacitor for processing the range-scaled input signal through the residual voltage amplifier have.

According to another aspect of the present invention, there is provided a pipelined SAR ADC having a time-interleaved structure according to another embodiment of the present invention. The pipelined SAR ADC has a time interleaving SAR ADC according to a first number of bits, A first stage configuring the channel; A second stage for constructing the plurality of channels using a time interleaving SAR ADC according to a second number of bits; And a residue voltage amplifier that is shared between the first and second stages and receives and amplifies a residue voltage of each channel of the first stage and outputs the amplified residue voltage to the second stage for each channel, And the second stage are determined in accordance with the number of bits, and the number of bits of the first stage is smaller than the number of bits of the second stage.

In a pipelined SAR ADC of the time interleaving structure according to yet another embodiment, the SAR ADC constituting the second stage can determine the most significant bit by directly comparing the sampled signal with a common mode voltage .

In a pipelined SAR ADC of the time interleaving structure according to another embodiment, the SAR ADC constituting the second stage applies a reference voltage generated by using a column of resistances to a least significant bit of the DAC to obtain a predetermined number of least significant bits Can be determined.

In a pipelined SAR ADC of the time interleaving structure according to yet another embodiment, the SAR ADC constituting the first and second stages comprises a true-single-phase-clock (TSPC) D flip-flop based SAR logic ; ≪ / RTI >

In the pipelined SAR ADC of the time interleaving structure according to another embodiment, the reference voltage for the SAR operation of the first stage, the reference voltage for the SAR operation of the second stage, and the reference voltage for the SAR operation of the residual voltage amplifier And the reference voltage generator can be shared.

Embodiments of the present invention solve the problem of offset mismatch between channels without using an offset correction technique by sharing a comparator between two channels, and further, there is an advantage that power consumption and area can be further reduced. Shared comparators do not require additional timing or correction circuitry, minimizing offset mismatch by alternately using a pair of input stages for both channels, and sharing the residual voltage amplifier between the two channels, , Gain and bandwidth mismatch problems are solved and power consumption can be minimized by applying the range scaling technique to lower the requirements of the amplifier.

FIG. 1 is a diagram for explaining a situation where offset mismatch between channels is caused by a comparator for each channel in the SAR ADC technology of a time interleaving structure.
2 is a diagram for explaining an idea of sharing a comparator in a SAR ADC of a time interleaving structure adopted by embodiments of the present invention.
3 is a block diagram illustrating a pipelined SAR ADC of a time interleaving structure that reduces interchannel offset mismatch according to an embodiment of the present invention.
4 is a timing diagram illustrating main operations of a pipelined SAR ADC of the time interleaving structure of FIG. 3 according to an embodiment of the present invention.
5A and 5B are diagrams illustrating a shared comparator of a first stage SAR ADC in a pipelined SAR ADC of a time interleaving structure according to an embodiment of the present invention.
6 is a diagram illustrating a shared comparator of a SAR ADC of a second stage in a pipelined SAR ADC of a time interleaving structure according to an embodiment of the present invention.
7 is a circuit diagram illustrating a shared residual voltage amplifier in a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention.
8 is a circuit diagram illustrating a capacitor-resistor (CR) hybrid DAC structure of a SAR ADC of a second stage in a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention.
9 is a circuit diagram illustrating SAR logic based on a TSPC D flip-flop in a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention.
FIG. 10 is a diagram for comparing simulation results of a general-purpose D flip-flop and a TSPC D flip-flop with respect to a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention.
11 is a view for explaining a case where one reference voltage is shared by a pipelined SAR ADC of a time interleaving structure according to yet another embodiment of the present invention and a case where a reference voltage driving circuit is separated.
12 is a diagram illustrating a result of measuring a typical FFT spectrum of a prototype of a pipelined SAR ADC of a time interleaving structure according to embodiments of the present invention.

Prior to describing embodiments of the present invention, after briefly introducing the characteristics and weak points of the pipelined SAR ADC of the time interleaving scheme, technical solutions employed by the embodiments of the present invention to solve such problems are sequentially Be presented.

As described above, the performance degradation due to offset mismatch between channels is mainly caused by the channel-to-channel offset mismatch in the case of the pipelined ADC of the time interleaving structure, while the SAR ADC of the time interleaving structure The main cause of mismatch between channels is offset by a comparator.

FIG. 1 is a view for explaining a situation in which offset mismatch between channels is caused by comparators 115 and 125 for respective channels 110 and 120 in the SAR ADC technology of a time interleaving structure. In the case of a single SAR ADC, the offset of the comparator only has the effect of shifting the characteristic curve of the entire ADC, but does not affect the overall linearity, but the SAR ADC of the time interleaving structure is comparator 115, 125, Channel offset mismatch occurs, which affects the linearity of the entire ADC and degrades the performance.

To solve this problem, there is a disadvantage in that an additional timing and digital circuit for offset correction is required, although a technique of correcting the offset by arranging a scalable capacitor at the output terminal of the comparator is available. In addition, if a digital-based offset correction technique is utilized, there is a disadvantage that area and power consumption increase because a large-scale and complicated correction circuit must be integrated in a chip. Therefore, there is a need for a proposal of a technical means capable of eliminating offset mismatch without an additional structure for offset correction.

FIG. 2 is a diagram for explaining the idea of sharing a comparator in a pipelined SAR ADC of a time interleaving structure commonly adopted by embodiments of the present invention. As shown in FIG. 2, a comparator 130 composed of a pair of input stages, The two channels 110 and 120 are alternately used so that no offset mismatch occurs between the channels. Thus, the comparator 130 shared between the two channels 110 and 120 does not require additional timing or circuitry for offset correction and because the two channels 110 and 120 use only one comparator 130, Can be reduced.

On the other hand, the higher the resolution of the SAR ADC, the larger the area and the power consumption are, because the number of unit capacitors used in the DAC increases exponentially. Although small size unit capacitors can be used to reduce area and power consumption, capacitor mismatch can occur and performance degradation due to nonlinearity can occur. Thus, various techniques are available to effectively reduce the number of unit capacitors used. For example, although a two-stage structure using a separate weight capacitor C _A can be used, there is a problem that mismatching occurs between the upper capacitor row and the lower capacitor row because the size of C _A does not become an integral multiple of the unit capacitor.

Accordingly, the ADC proposed by an embodiment of the present invention simultaneously implements a 2-stage pipelined SAR structure and a 2-channel time interleaving structure based on, for example, 4-bit to 7-bit, thereby realizing a fast conversion speed while minimizing power consumption , We use a channel-to-channel comparator sharing scheme that minimizes offset mismatch between channels without special correction techniques. In addition to offset mismatch between channels, various circuit design techniques are applied to minimize mismatch between channels, such as gain mismatch and sampling timing mismatch. The second stage 7-bit SAR ADC uses a small-sized unit capacitor, or a V _CM- based switching technique instead of a two-stage structure using C _A , and generates six reference voltages for the lowest 2-bit decision Applying a technique using simple resistance heat, the number of unit capacitors used is reduced to 1/8 level, minimizing area and power consumption, and preventing degradation in performance due to capacitor mismatch.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description and the accompanying drawings, detailed description of well-known functions or constructions that may obscure the subject matter of the present invention will be omitted. It should be noted that the same constituent elements are denoted by the same reference numerals as possible throughout the drawings. The following embodiments illustrate a structure in which each stage is designed based on, for example, 4-bit to 7-bit in the implementation of a two-stage pipelined SAR structure. However, The present invention is not limited to the set values exemplified as being set to be suitable for the operation speed required in the terminal.

3 is a block diagram illustrating a pipelined SAR ADC of a time interleaving structure that reduces interchannel offset mismatch according to an embodiment of the present invention.

The first stage (stage) 10 constructs a plurality of channels using a time interleaved SAR ADC according to a first number of bits, and as described above with reference to FIG. 2, And performs a comparison operation required for the SAR operation of the comparator, and prevents offset mismatch between channels by sharing the comparator between respective channels.

The second stage 20 constructs the plurality of channels using a time interleaving SAR ADC according to the second number of bits, and as described above with reference to FIG. 2, the SAR ADC of the second stage is required to perform the SAR operation of the channel And a comparator that performs a comparison operation, and prevents the interchannel offset mismatch by sharing the comparator between the respective channels.

The residual voltage amplifier 30 is configured such that the two channels of the first stage 10 and the second stage 20 are shared between the two channels and the residual voltage of the first stage 10 residue voltage, and outputs the amplified residue voltage to the second stage 20 on a channel-by-channel basis.

3, the proposed ADC shares channel-to-channel comparators (one at each of the first and second stages respectively) and a residual voltage amplifier 20 to minimize channel-to-channel offset mismatch And the sampling clock used in each channel is synchronized with one reference clock, thereby solving the problem of input sampling signal mismatch between channels. In addition, by applying a range-scaling technique that reduces the input signal from 1.4Vpp to 0.7Vpp from the second stage (20), it reduces power consumption by the amplifier by reducing the design requirement of the amplifier . In the capacitor column of the second stage (20) 7-bit SAR ADC, the number of capacitors used by applying the V _CM- based switching technique and the technique of determining the least significant 2 bits by applying 6 reference voltages generated by simple resistance arrays To 1/8 level, and true-single-phase-clock (TSPC) D flip-flop instead of general-purpose D flip-flop for SAR logic of 4-bit and 7-bit SAR ADC for high-speed SAR operation. And reduces the number of transistors used at the same time by half. The reference current and voltage generators are integrated in the chip. By separating the reference voltage driving circuit used for residual voltage amplification and SAR operation, the problem of reference voltage interference and channel-to-channel gain misalignment due to different switching operations is minimized. On-chip clock generation circuitry, which can be externally duty cycle controlled, generates its own high frequency clocks, 960MHz and 840MHz, required for 4-bit and 7-bit SAR operation, respectively, and 120MHz And generates and supplies 120 MHz and 60 MHz clocks required for each block. The detailed configuration described above will be described later in detail with reference to the respective drawings.

4 is a timing diagram for explaining the main operation of a pipelined SAR ADC of the time interleaving structure of FIG. 3 according to an embodiment of the present invention. FIG. 4 is a timing diagram of a 10-bit 120 MS / s pipelined SAR ADC based on a 2-channel time- The main operation, SAR operation and residual voltage amplification timing, are illustrated.

The first stage 4-bit SAR ADC consists of two channels, sampling the input signal for half a period of 120 MHz clock, and converting it to a high-order 4-bit digital code with high-speed SAR operation at 960 MHz for the next half-period. Then, the residual voltage, which is the difference between the input signal and the reference voltage determined by the upper 4-bit code, is amplified four times by the residual-voltage amplifier with the range-scaling technique for half a period of 60 MHz clock, Is sampled. During the remaining 60MHz half-period, the 7-bit SAR ADC outputs the lower 7-bit digital code through the SAR operation at 840MHz, resulting in a 10-bit digital code for the analog input signal finally output at a rate of 120MS / s.

4, the SAR operation of the first stage, the residual voltage amplification, and the SAR operation of the second stage proceed at the same timing to cause a reference voltage interference problem. However, the ADC proposed by the embodiments of the present invention, We solved the problem of reference voltage interference by separating the driving circuit into three types. This configuration will be described later in detail with reference to FIG.

5A and 5B are diagrams illustrating a shared comparator of a first stage SAR ADC in a pipelined SAR ADC of a time interleaving structure according to an embodiment of the present invention.

It has already been described that a SAR ADC with a normal time interleaving structure causes offset mismatch by a comparator between each channel and may be a main cause of degradation of the overall ADC performance. In addition, various offset correction techniques have been proposed to solve this problem, but it has been pointed out that additional timing and digital circuits are necessary. Therefore, in the pipelined SAR ADC of the time interleaving structure according to the embodiments of the present invention, an interchannel comparator sharing technique for resolving the interchannel offset mismatch without special correction technique is proposed, and the structure of the comparator used in the first stage SAR ADC Is illustrated in FIG. 5B.

The comparator shared in the first stage 10 of FIG. 3 is configured as a latch without a preamplifier as shown in FIG. 5B. Unlike the conventional latch, the comparator includes two pairs of input stages and a kick- A pull-down switch 11 for reducing noise, and an additional latch 12 for speed up. In order to perform the comparison operation of the two channels alternately, a pair of input stages may be used and each channel may be selected through a switch. However, in the first stage (10), the residual voltage generated after the SAR operation is amplified The residual voltage may be distorted due to the charge input generated when the switch for channel selection is turned off. Therefore, the switch for channel selection is removed and two pairs of input stages are formed. Also, the memory effect generated at the input terminal of the comparator is automatically removed during the sampling operation.

5b, when the offset of the first stage (10) comparator of the proposed pipelined SAR ADC is within 1/2 LSB of 4 bits, the code error due to offset can be corrected through a digital calibration circuit, The overall ADC is nonlinear and performance degrades. Although the size of the offset can be easily reduced by increasing the input-stage transistor size of the comparator, since the kick-back noise increases and the signal stored in the capacitor string may be distorted, By arranging the pull-down switch 11 acting as a buffer, the kick-back noise is reduced. The graph of Figure 5a is a Monte Carlo simulation result of comparator offsets for 500 samples, with a standard deviation of 6.79mV for the comparator offset size and a stable distribution within the half-LSB (43.75mV) of the 4 bits. Therefore, the code error due to the offset of the comparator can be corrected by the digital calibration circuit, so that the linearity of the entire ADC is not affected. Further, the operation speed of the comparator is improved through the additional latch 12, so that a stable comparison operation can be performed even at a high speed operation of 960 MHz.

In summary, the comparator constituting the first stage 10 of the pipelined SAR ADC of the time interleaving structure according to an embodiment of the present invention includes a number of input pairs corresponding to the number of channels and a drain node and a pull-down switch 11 disposed at a drain node of the comparator and serving as a buffer to reduce kick-back noise, (Not shown) to the latches 12 and the latches 12, as shown in FIG. Particularly, the comparator constituting the first stage 10 is characterized in that the memory effect generated at the input terminal of the comparator can be automatically removed during a sampling operation.

The comparator offset of the first stage (10) SAR ADC of FIG. 3 is corrected through a digital calibration circuit while the comparator offset of the second stage (20) SAR ADC of FIG. 3 is not corrected, Which causes deterioration of ADC performance. The inter-channel offset mismatch by the second-stage (20) comparator seen from the input reference of the entire ADC is expressed by Equation (1), and the SNDR representing the performance limitation of the ADC due to the mismatch is expressed by Equation (2).

In the above equations, σ _{os, mis_2nd} and σ _{os, mis} are the standard deviations of the offset mismatch by the second-stage (20) comparator and the offset mismatch from the input reference of all ADCs, and P _s , P _d and A _in are The power of the input signal, the power of the distortion signal, and the amplitude of the input signal. In order to obtain SNDR of 62 dB according to Equation (2), σ _{os and mis_2nd} should be designed to be 1.57 mV or less, but there is a limitation in designing a comparator having an offset of 1.57 mV or less without applying a correction technique. Therefore, the shared comparator of the second stage 20 is configured such that two channels are alternately connected to a pair of input stages as shown in FIG. 3, thereby minimizing the offset mismatch between channels by the comparator. The structure and timing diagram of the shared comparator of the second stage 20 are the same as in FIG.

6 is a diagram illustrating a shared comparator of a SAR ADC of a second stage in a pipelined SAR ADC of a time interleaving structure according to an embodiment of the present invention.

The SAR2_CH1 and SAR2_CH2 signals of the timing diagram control a switch connecting the capacitor row of each channel and the input terminal of the comparator, and the comparator performs a comparison operation required for SAR operation of each channel through a pair of input terminals. On the other hand, after the SAR operation of one channel, it is possible to perform erroneous comparison operation in the SAR operation of the other channel due to the charge remaining at the input terminal of the comparator, so that the memory effect is eliminated by periodically resetting the input terminal after the SAR operation of each channel Respectively. The pull-down switch 21 for reducing the kick-back noise and the additional latch 11 for increasing the speed are applied in the same manner as the comparator of the first stage.

In summary, a comparator that constitutes the second stage 20 of the pipelined SAR ADC of the time interleaving structure according to an embodiment of the present invention comprises a pair of input stages in which the plurality of channels are configured to be alternately connected, Down switch 21 disposed at the drain node of the first stage 20 and serving as a buffer to reduce the kick-back noise, and the comparator constituting the second stage 20 may include a pull- And may further optionally include additional latches 22. Particularly, the comparator constituting the second stage 20 is characterized in that the memory effect can be eliminated by resetting the input terminal after every SAR operation of each channel at predetermined intervals.

Now, a description will now be given of a residual voltage amplifier sharing scheme (corresponding to No. 30 in FIG. 3) for interchannel offset and gain mismatch resolution.

In the case of a pipelined ADC with a general time interleaving structure, offset and gain mismatch between the input stage SHA and the first stage MDAC amplifier of each channel is a main cause of deteriorating the performance of the entire ADC. For ADCs, amplifier offsets and gain matching between each channel must be designed to be at least 10 bit level. It is not only difficult to obtain a 10-bit level match or more without an additional correction circuit, but also efficiency in terms of power consumption when each amplifier is used for each channel. Therefore, the ADC proposed by the embodiments of the present invention solves the offset and gain mismatch problem by minimizing the area and power consumption by sharing the residual voltage amplifier between the channels as shown in FIG.

7 is a circuit diagram illustrating a residual voltage amplifier shared in a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention, in which power consumption and area are reduced compared to the case of using two amplifiers using only one amplifier 50%, and the power consumption is minimized by applying a range-scaling technique to lower the requirements of the amplifier.

To this end, the pipelined SAR ADC of the time interleaving structure according to another embodiment of the present invention includes a first stage for constructing a plurality of channels using a time interleaving SAR ADC according to a first number of bits, A second stage constituting the plurality of channels and a residue voltage for each channel of the first stage are amplified and amplified using a time interleaving SAR ADC according to the number of 2 bits, Wherein the residual voltage amplifier (30) comprises a shared-residue voltage amplifier (30) for outputting only the half of the input signal range input to the first stage to the second stage, (range-scaling) scheme to reduce power consumption by the amplifier.

In particular, the residual voltage amplifier 30 has a feature of eliminating the memory effect by ensuring a reset time of a non-operating channel including a pair of input terminals separated for each channel. The residual voltage amplifier 30 also includes a first amplifier having a gain-boosting structure for increasing the voltage gain and a common amplifier having a wide (e.g., greater than or equal to a reference value) signal swing range A second amplifier of a common-source structure.

More specifically, the shared residual voltage amplifier eliminates the memory effect generated in the conventional amplifier sharing technique by securing the reset time of the unused channel by using two separated pairs of input stages as shown in FIG. 7, Using the nested clocks Q1MB and Q2MB to solve the settling time delay problem of glitches and amplified signals that can occur when both input transistors are turned off and on again. In addition, in the nanometer process, short channel length and lower supply voltage limit the implementation of a high voltage gain amplifier and sufficient signal swing range. However, in order to realize a high voltage gain residual voltage amplifier satisfying a resolution of 10 bits or more A gain-boosting structure is applied to the first amplifier of the two-stage amplifier, and a common-source structure is applied to the second amplifier to ensure a sufficient signal swing range even at a low power supply voltage.

On the other hand, the SAR ADC constituting the second stage in the pipelined SAR ADC of the time interleaving structure according to another embodiment of the present invention is capable of receiving the range-scaled input signal through the residual voltage amplifier 30 without an additional reference voltage generator And a capacitor (not shown) for processing. This additional capacitor will be described later with reference to FIG.

Various design techniques and implementation examples of the SAR ADC constituting the second stage in the pipelined SAR ADC of the time interleaving structure proposed by still another embodiment of the present invention will be described below.

The proposed ADC adopts a 4-bit-7-bit pipeline structure. The 7-bit SAR ADC of the second stage has a larger number of capacitors to be used than the 4-bit SAR ADC of the first stage Which is disadvantageous in terms of area and power consumption. Smaller unit capacitors can be used to reduce area and power consumption, but performance degradation due to capacitor mismatch can occur. Also, when a two-stage structure using a separate weight capacitor (C _A ) is used to reduce the number of capacitors used, the size of C _A does not become an integral multiple of the unit capacitors, and mismatching occurs between the upper capacitor row and the lower capacitor row Which can be a cause of performance degradation.

Therefore proposed ADC is using a simple resistive heat that generate six reference voltage for the common-mode voltage V _CM-based switching technique, and the least significant two bits determined as without having to apply a two-stage structure using a C _A, 8 to , The area and power consumption are minimized by dramatically reducing the number of capacitors used.

FIG. 8 is a circuit diagram illustrating a capacitor-resistor (CR) hybrid DAC structure of a second stage SAR ADC in a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention, And various configurations for reducing consumption.

8, a pipelined SAR ADC of a time-interleaved structure according to another embodiment of the present invention may be implemented using a time interleaving SAR ADC according to a first number of bits, A first stage constituting a plurality of channels and a second stage constituting the plurality of channels and a channel using a time interleaving SAR ADC according to a second number of bits, and a residue voltage amplifier for receiving and amplifying a residue voltage of the first stage and outputting the amplified residue voltage to the second stage for each channel, wherein the first stage and the second stage have operation speeds And the number of bits of the first stage has a value smaller than the number of bits of the second stage.

More specifically, the sampled signal is directly compared with the common mode voltage V _CM without additional switching operation to determine the most significant bit. The common mode voltage V _CM- based switching technique occupies the largest area in the DAC and determines the most significant bit It is possible to remove (27) the capacitor ( ²⁶ C _U ). Since the capacitor row is switched based on the common mode voltage V _CM , there is no performance degradation due to the input common mode voltage change of the comparator, and the voltage change across the capacitor is reduced to half compared with the conventional switching method, The power consumption is reduced by about 90% compared with the conventional one. The two largest capacitors (2 ⁵ C _U and 2 ⁴ C _U ) of the capacitor row are determined by applying the six reference voltages generated by using a simple resistor string to the lowest capacitor (C _U ) of the DAC to determine the least significant two bits. (26) to reduce area and power consumption. Compared to a typical 7-bit SAR ADC with a total of 128 capacitors, the second-stage 7-bit SAR ADC uses both capacitors, reducing both area and power consumption simultaneously.

In summary, in a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention, the SAR ADC constituting the second stage directly compares the sampled signal with a common mode voltage, The most significant bit can be determined by switching the capacitor row based on the common mode voltage and a certain number of least significant bits can be determined by applying the reference voltage generated using the column of resistance to the least significant capacitor of the DAC.

On the other hand, when the reference voltage generator is added to process the range-scaled input signal in the second-stage 7-bit SAR ADC, the power consumption and area increase sharply. Therefore, only 2 ⁴ C _U is added to the capacitor column of the second 7-bit SAR ADC (25), so that the range-scaled input signal can be efficiently processed without additional reference voltage.

In order to improve the speed of SAR operation, we introduce SAR logic with D flip-flop based on TSPC.

9 is a circuit diagram illustrating SAR logic based on a TSPC D flip-flop in a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention.

As described above, the ADC proposed by the embodiments of the present invention adopts a two-channel time-interleaving structure and a pipeline structure of two stages (for example, 4 bits to 7 bits) Although the operation speed of voltage amplifiers can be mitigated, 4-bit and 7-bit SAR ADCs still have to perform high-speed SAR operation at 960MHz and 840MHz, and to achieve this, the delay in SAR logic must be reduced as much as possible.

Therefore, the SAR logic based on the D flip-flop can be applied to the high-speed SAR operation by applying the TSPC D flip-flop as shown in FIG. 9 instead of the general-purpose D flip-flop. That is, in the pipelined SAR ADC of the time interleaving structure according to another embodiment of the present invention, the SAR ADC constituting the first stage and the second stage includes a set (S) and a reset (R) It is desirable to include a true-single-phase-clock (TSPC) D flip-flop based SAR logic.

FIG. 10 is a diagram for comparing simulation results of a general-purpose D flip-flop and a TSPC D flip-flop with respect to a pipelined SAR ADC of a time interleaving structure according to another embodiment of the present invention.

The simulation results for the circuit and the delay time of the TSPC D flip-flop applied to the SAR logic for high-speed SAR operation are shown in Fig. Using a TSPC D flip-flop instead of a general-purpose static D flip-flop can reduce the delay time by about 83.2 ps, and the number of transistors used can also be reduced to half, improving the SAR ADC operation speed. And power consumption and area can be minimized.

In the meantime, technical means and an implementation example for solving the problem of the reference voltage interference, which has been briefly introduced above, will be described below.

11 is a view for explaining a case where one reference voltage is shared by a pipelined SAR ADC of a time interleaving structure according to yet another embodiment of the present invention and a case where a reference voltage driving circuit is separated.

In the case of a typical pipelined SAR ADC, the reference voltage settling may be unstable due to the overlapping of different modes of operation due to the mixed SAR ADC operating at high speed and the residual voltage amplifier requiring high accuracy. In the case of the ADC proposed by the embodiments of the present invention, the reference voltage used in the residual voltage amplification is required to have a high accuracy of 10 bits. However, when one reference voltage is shared as shown in FIG. 11A, A reference voltage interference problem occurs, and there is a restriction in generating a reference voltage having a high accuracy of 10 bits. On the other hand, when the SAR operation and the reference voltage used in the residual voltage amplification are separated as shown in FIG. 11 (b), the reference voltage interference due to the fast switching operation of the SAR ADC can be minimized, .

That is, in the pipelined SAR ADC of the time interleaving structure according to another embodiment of the present invention, the reference voltage for the SAR operation of the first stage, the reference voltage for the SAR operation of the second stage, and the amplification operation of the residual voltage amplifier It is preferable that the reference voltage generator is shared.

More specifically, the ADC proposed in this embodiment separates the reference voltage driving circuit for the 4-bit SAR operation, the residual voltage amplification in the first stage, and the 7-bit SAR operation in the second stage, respectively. That is, by using only one reference voltage having 10 bits of high resolution for residual voltage amplification and two reference voltages having 4 bit and 7 bit resolution for SAR operation, The gain mismatch problem was minimized and the reference voltage generator was shared, but power dissipation could be optimized by separating only the reference voltage driving circuit.

Hereinafter, embodiments of the present invention will be described with reference to the results of performance measurement using a prototype ADC manufactured based on the technical features described above.

The 10-bit 120 MS / s pipelined SAR ADC based on the two-channel time interleaving structure proposed by embodiments of the present invention was fabricated by a 45 nm CMOS process, and the total area of the prototype ADC was 0.38 mm ² . The 790pF on-chip MOS capacitors are integrated in the idle space excluding each block constituting the entire ADC, minimizing the noise of the supply voltage, the noise of the reference voltage due to the fast switching, and the interference between each block. The prototype ADC consumes 12.1mW at 1.1V supply voltage and 120MS / s operating speed, and consumes 8.8mW when not using the internal reference generator.

12 is a diagram illustrating a result of measuring a typical FFT spectrum of a prototype of a pipelined SAR ADC of a time interleaving structure according to embodiments of the present invention, wherein a 4 MHz input frequency, 20 MS / s and 120 MS / s operation The typical signal spectrum of the prototype ADC measured at the speed is shown. It can be seen that no tone occurs at f _s / 2 at both operating speeds of 20 MS / s and 120 MS / s. It can be seen that the offset mismatch problem between channels has been solved properly by the comparator sharing technique between two channels.

As described above, embodiments of the present invention provide a 10-bit 120 MS / s pipelined SAR ADC based on a 2-channel time-interleaving structure using a simultaneous sharing technique of a comparator and an amplifier to minimize the channel mismatch problem without any correction scheme The

According to the embodiments of the present invention described above, the offset mismatch problem between channels can be solved without using offset correction techniques by sharing a comparator between the two channels, and power consumption and area can be further reduced. Shared comparators do not require additional timing or correction circuitry, and offset mismatch is minimized by alternately using a pair of input stages for the two channels. In addition, by sharing the residual voltage amplifier between two channels, the problem of offset, gain, and bandwidth mismatch caused by the amplifier is solved and power consumption is minimized by applying the range scaling technique to lower the requirement of the amplifier.

The second-stage 7-bit SAR ADC employs a V _CM- based switching scheme and a simple resistor-string technique that generates six reference voltages for the lowest 2-bit decisions, reducing the number of capacitors used to one- Reducing the area and switching power consumed within the DAC. In addition, to implement the high-speed 4-bit and 7-bit SAR ADC, TSPC D flip-flop is applied to each SAR logic rather than general D flip-flop to reduce the delay time, Thereby minimizing the area and power consumption.

In order to solve the problem of reference voltage interference which occurs when only one reference voltage is used, the problem of reference voltage interference and channel-to-channel gain misalignment is minimized by separating the reference voltage driving circuit used in residual voltage amplification and SAR operation. The high frequency clock needed for high-speed SAR operation is generated inside the chip via an on-chip clock generation circuit, and a circuit can be implemented so that the duty cycle can be controlled externally if necessary.

The present invention has been described above with reference to various embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

110, 120: SAR circuit for each channel
115, 125: Comparator separated per channel
130: Channel-shared comparator
10: First stage
20: second stage
30: Residual voltage amplifier
11, 21: Full-down switch
12, 22: Additional latches

Claims (18)

In a time-interleaved pipelined SAR ADC,
A first stage for constructing a plurality of channels using a time interleaving SAR ADC according to a first number of bits;
A second stage for constructing the plurality of channels using a time interleaving SAR ADC according to a second number of bits; And
And a residue voltage amplifier, which is shared between the channels, receives and amplifies the residue voltage of each channel of the first stage, and outputs the amplified residue voltage to the second stage for each channel. The method according to claim 1,
The SAR ADCs of the first and second stages each include a comparator for performing a comparison operation required for the SAR operation of the channel and sharing the comparator between the respective channels to prevent offset mismatch between channels And a pipelined SAR ADC. 3. The method of claim 2,
Wherein the sampling clocks used in each channel are synchronized to one reference clock to prevent mismatching of the interchannel input sampling signals. 3. The method of claim 2,
Wherein the comparator constituting the first stage comprises:
A pair of input terminals corresponding to the number of the channels; And
And a pull-down switch disposed at a drain node of the input terminal pair to reduce a kick-back noise by performing a buffer function. Pipelined SAR ADCs. 3. The method of claim 2,
Wherein the comparator constituting the first stage comprises:
Further comprising: an additional latch that increases the operating speed of the comparator. 3. The method of claim 2,
Wherein the comparator constituting the first stage comprises:
And automatically removes a memory effect occurring at an input of the comparator during a sampling operation. 3. The method of claim 2,
Wherein the comparator constituting the second stage comprises:
One input pair configured such that the plurality of channels are alternately connected by a switch; And
And a pull-down switch disposed at a drain node of the input pair to reduce a kick-back noise by acting as a buffer. 3. The method of claim 2,
Wherein the comparator constituting the second stage comprises:
And an additional latch to increase the operating speed of the comparator. 3. The method of claim 2,
Wherein the comparator constituting the second stage comprises:
Wherein the memory effect is removed by resetting the input terminal after every SAR operation of each channel at predetermined intervals. In a time-interleaved pipelined SAR ADC,
A first stage for constructing a plurality of channels using a time interleaving SAR ADC according to a first number of bits;
A second stage for constructing the plurality of channels using a time interleaving SAR ADC according to a second number of bits; And
And a residue voltage amplifier, which is shared between the channels, receives and amplifies a residue voltage of each channel of the first stage, and outputs the amplified residue voltage to the second stage for each channel,
Wherein the residual voltage amplifier comprises:
Scaled manner to output half of the input signal range input to the first stage to the second stage, thereby reducing power consumption by the amplifier. 11. The method of claim 10,
Wherein the residual voltage amplifier comprises:
A pair of input terminals separated by a channel,
And a memory effect is removed by securing a reset time of the inoperative channel. 11. The method of claim 10,
Wherein the residual voltage amplifier comprises:
A first amplifier having a gain-boosting structure for increasing a voltage gain; And
And a second amplifier of a common-source structure having a signal swing range above a reference value. 11. The method of claim 10,
The SAR ADC, which constitutes the second stage,
And a capacitor for processing the range-scaled input signal through the residual voltage amplifier. In a time-interleaved pipelined SAR ADC,
A first stage for constructing a plurality of channels using a time interleaving SAR ADC according to a first number of bits;
A second stage for constructing the plurality of channels using a time interleaving SAR ADC according to a second number of bits; And
And a residue voltage amplifier, which is shared between the channels, receives and amplifies a residue voltage of each channel of the first stage, and outputs the amplified residue voltage to the second stage for each channel,
Characterized in that the operating speed is determined according to the number of bits of the first stage and the second stage, and the number of bits of the first stage has a value smaller than the number of bits of the second stage. ADC. 15. The method of claim 14,
The SAR ADC, which constitutes the second stage,
Wherein the most significant bit is determined by directly comparing the sampled signal with a common mode voltage and switching the capacitor string based on the common mode voltage. 15. The method of claim 14,
The SAR ADC, which constitutes the second stage,
Wherein a predetermined number of least significant bits are determined by applying a reference voltage generated by using the column of resistances to a least significant capacitor of the DAC. 15. The method of claim 14,
The SAR ADC constituting the first stage and the second stage includes:
A true-single-phase-clock (TSPC) D flip-flop based SAR logic. 15. The method of claim 14,
A reference voltage for SAR operation in the first stage, a reference voltage for SAR operation in the second stage, and a reference voltage used in an amplifying operation of the residual voltage amplifier are separated from each other, Wherein the ADC is a pipelined SAR ADC.

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