KR102380254B1 - Time-interleaved bandpass sar adc and method for mismatch shaping using the same - Google Patents

Abstract

Disclosed are a time interleaving-based bandpass successive approximation register (SAR) analog-digital converter (ADC) to remove performance degradation due to mismatch of a plurality of capacitors and a mismatch correction method thereof. According to one embodiment of the present invention, the interleaving-based bandpass SAR ADC comprises: an SAR conversion unit including a plurality of channels for performing digital conversion on the basis of an input signal acquired by sampling an analog signal at each preset sampling period to sequentially output digital signals corresponding to the analog signals; a digital-to-analog conversion unit including a plurality of capacitors sampling the analog signal as the input signal on the basis of the sampling period; and a mismatch shaping unit performing data weight averaging to determine an allocation order from the most significant bit to the least significant bit for the plurality of capacitor on the basis of the digital signal.

Description

TIME-INTERLEAVED BANDPASS SAR ADC AND METHOD FOR MISMATCH SHAPING USING THE SAME

The present application relates to a time interleaving-based bandpass SAR ADC and a mismatch correction method thereof.

Analog Digital Converter (ADC) is a device that converts an analog signal representing a continuous value into a digital signal representing a discrete positive value (for example, a string of n bits) means Examples of such ADCs include pipelined ADCs, successive approximation registers (SARs), and delta-sigma ADCs.

In particular, a high-performance ADC having a resolution of 10 bits or more and an operation speed of 80 MS/s or more is required in a high-definition display system for mobile use. In order to satisfy these performance requirements, an ADC having a pipeline structure has been mainly used. In addition, as process technology develops, research on digital circuit-based SAR ADCs is being actively conducted, but there is a disadvantage in that the operation speed of the internal circuit increases as the resolution increases. In order to overcome these shortcomings, a high-resolution and high-speed ADC can be implemented by applying a pipeline structure and a time-interleaved (T-I) structure in which several identical ADCs are connected in parallel.

In this regard, in the case of an ADC having a time interleaving structure through a plurality of channels, signal-dependent harmonics may occur in-band due to mismatch between capacitors, thereby deteriorating performance. there is. Specifically, in the ADC having a time interleaving structure, a mismatch between capacitors is generated by being divided into a routing mismatch related to each of a plurality of channels and a process mismatch not related to the channel.

In order to correct the aforementioned routing mismatch, process mismatch, etc., mismatch shaping through data weight averaging (DWA) based on digital output values from individual channels can be applied, but application to time interleaving structure For this, digital logic that prevents direct interaction between channels is required.

On the other hand, the conventional literature [J. Liu, X. Wang, Z. Gao, M. Zhan, X. Tang and N. Sun, "9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4Х Passive Gain and 2nd-Order Mismatch Error Shaping"] Since the mismatch shaping technique is a technique that can be applied only to a single channel, when applied to an ADC having a time interleaving structure including a plurality of channels, it increases white noise and deteriorates performance. has a limit to

The technology that is the background of the present application is disclosed in Korean Patent No. 10-1299215.

The present application is intended to solve the problems of the prior art, and a time interleaving-based band capable of solving performance degradation due to mismatch of a plurality of capacitor elements in an analog-to-digital converter having a time interleaving structure including a plurality of channels It aims to provide a pass-through SAR ADC and a method for correcting its mismatch.

However, the technical problems to be achieved by the embodiments of the present application are not limited to the technical problems described above, and other technical problems may exist.

As a technical means for achieving the above technical problem, the time interleaving-based bandpass SAR ADC according to an embodiment of the present application performs digital conversion based on an input signal sampling an analog signal at each preset sampling period. A digital-to-analog conversion comprising: a SAR converter including a plurality of channels for sequentially outputting a digital signal corresponding to the analog signal; and a plurality of capacitor elements for sampling the analog signal as the input signal based on the sampling period and a mismatch shaping unit that performs data weight averaging for determining an allocation order from the most significant bit to the least significant bit for the plurality of capacitor elements based on the negative and the digital signal.

Also, the mismatch shaping unit may determine the allocation order applied to the one channel based on the digital signal output from the one channel among the plurality of channels.

In addition, the mismatch shaping unit may determine the allocation order associated with a sampling operation performed two cycles after the one channel based on the digital signal output from the one channel.

In addition, the plurality of channels may include a first channel, a second channel, and a third channel.

In addition, the mismatch shaping unit determines the allocation order applied to the n+6th sampling period of the first channel based on a digital signal outputted corresponding to the nth sampling period in the first channel, and The allocation order applied to the n+7th sampling period of the second channel is determined based on the digital signal output corresponding to the n+1th sampling period in the second channel, and n+2 in the third channel The allocation order applied to the n+8th sampling period of the third channel may be determined based on the digital signal output corresponding to the th sampling period.

In addition, the plurality of capacitor elements may include a first capacitor element to an M-th capacitor element.

In addition, the mismatch shaping unit may be configured to perform a forward assignment that determines the assignment order in a first order, which is an order from the first capacitor element to the Mth capacitor element, and a second order opposite to the first order. The reverse assignment that determines the assignment order may be alternately applied.

In addition, the mismatch shaping unit, based on the digital signal output corresponding to the n-6th sampling period, corresponds to the starting point of the forward allocation or the reverse allocation applied to the nth sampling period among the plurality of capacitor elements. The capacitor element can be determined.

Also, the mismatch shaping unit may perform the data weight averaging based on the mismatch transfer function according to Equation 1 below.

In addition, the SAR converter may perform the digital conversion corresponding to the n+2th sampling period based on the residual signal remaining in the digital-analog converter after the digital conversion is performed in response to the nth sampling period. can

In addition, a bandpass characteristic in which the analog signal is converted into a digital signal corresponding to a predetermined passband by a difference between two sampling periods of the sampled analog signal used for the digital conversion and the residual signal may be implemented.

On the other hand, in the mismatch correction method for a bandpass SAR ADC based on time interleaving according to an embodiment of the present application, an input signal to be applied to a plurality of channels by sequentially sampling an analog signal through time interleaving based on a plurality of capacitor elements and outputting a digital signal corresponding to the analog signal by performing digital conversion by each of the plurality of channels based on the input signal.

In addition, the generating of the input signal may include performing data weight averaging to determine an allocation order from the most significant bit to the least significant bit for the plurality of capacitor elements based on the digital signal.

The above-described problem solving means are merely exemplary, and should not be construed as limiting the present application. In addition to the exemplary embodiments described above, additional embodiments may exist in the drawings and detailed description.

According to the above-described problem solving means of the present application, a time interleaving-based bandpass SAR ADC capable of solving performance degradation due to mismatch of a plurality of capacitor elements in an analog-to-digital converter having a time interleaving structure including a plurality of channels, and A method for correcting its mismatch can be provided.

According to the above-described problem solving means of the present application, data weight averaging is performed by delaying the digital output so as not to cause direct interaction between a plurality of channels, so that in a SAR ADC having a time interleaving structure ( Mismatch shaping for reducing in-band harmonic components may be performed.

According to the above-described problem solving means of the present application, there is an advantage that a digital circuit can be easily configured by performing digital logic-based mismatch correction in which direct interaction between a plurality of channels does not occur.

However, the effects obtainable herein are not limited to the above-described effects, and other effects may exist.

1 is a conceptual diagram for explaining a schematic operation of a time interleaving-based bandpass SAR ADC according to an embodiment of the present application.
2 is a schematic configuration diagram of a time interleaving-based bandpass SAR ADC according to an embodiment of the present application.
3 is a diagram illustrating an interleaving spur generated by mismatch between channels of a time interleaving ADC according to the number of channels of the time interleaving ADC.
4 is a detailed configuration diagram of a SAR converter according to an embodiment of the present application.
5 is a detailed configuration diagram of a digital-to-analog converter according to an embodiment of the present application.
6 is a conceptual diagram for explaining a data weight averaging technique according to an embodiment of the present application.
7 and 8 are diagrams illustrating changes in white noise and harmonics when a conventional mismatching shaping technique is used.
9 is a diagram illustrating changes in white noise and harmonics according to the mismatch shaping technique of the present application for a bandpass SAR ADC including a plurality of channels.
10 is a conceptual diagram for explaining the structure and function of each of a first stage and a second stage of a time interleaving-based bandpass SAR ADC of a pipeline structure according to another embodiment of the present application.
11 is a schematic block diagram of a time interleaving-based bandpass SAR ADC of a pipeline structure according to another embodiment of the present application.
12 is an operation flowchart of a mismatch correction method for a bandpass SAR ADC based on time interleaving according to an embodiment of the present application.

Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art to which the present application pertains can easily carry out. However, the present application may be implemented in several different forms and is not limited to the embodiments described herein. And in order to clearly explain the present application in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout this specification, when a part is "connected" with another part, it is not only "directly connected" but also "electrically connected" or "indirectly connected" with another element interposed therebetween. "Including cases where

Throughout this specification, when a member is positioned “on”, “on”, “on”, “on”, “under”, “under”, or “under” another member, this means that a member is positioned on the other member. It includes not only the case where they are in contact, but also the case where another member exists between two members.

Throughout this specification, when a part "includes" a certain component, it means that other components may be further included, rather than excluding other components, unless otherwise stated.

The present application relates to a time interleaving-based bandpass SAR ADC and a mismatch correction method thereof.

1 is a conceptual diagram for explaining a schematic operation of a time interleaving-based bandpass SAR ADC according to an embodiment of the present application, and FIG. 2 is a schematic configuration diagram of a time interleaving-based bandpass SAR ADC according to an embodiment of the present application am.

Specifically, FIG. 1 shows a mismatch shaping technique disclosed herein to solve a mismatch between a plurality of capacitor elements in a bandpass SAR ADC including a plurality of channels of a time interleaving structure. A timing diagram may be shown.

In addition, referring to FIGS. 1 and 2 , the time interleaving-based bandpass SAR ADC 100 (hereinafter referred to as 'bandpass SAR ADC 100') according to an embodiment of the present application includes a SAR converter ( 110 ), a digital-to-analog converter 120 , and a mismatch shaping unit 130 .

The SAR converter 110 sequentially outputs a digital signal corresponding to the analog signal by performing digital conversion ('Convs' process in FIG. 1) based on the input signal sampling the analog signal at each preset sampling period. It may include a plurality of channels.

Here, sequential sampling through time interleaving means that after sampling by a first channel (eg, CH _A in FIG. 1 ) of a plurality of channels is performed, a second channel of a plurality of channels (eg, Between a plurality of channels, such as sampling by the CH _B of FIG. 1 ), sampling by the second channel is performed, and sampling by the third channel (eg, CH _C in FIG. 1 ) is performed. It may be understood to mean a series of sequential sample and hold operations according to a predetermined order.

In addition, according to an embodiment of the present application, the SAR converter 110 may include an odd number of channels. For example, the SAR converter 110 may include three channels including a first channel (CH _A ), a second channel (CH _B ), and a third channel (CH _C ). Hereinafter, the number of channels included in the SAR converter 110 will be described with reference to FIG. 3 .

3 is a diagram illustrating an interleaving spur generated by mismatch between channels of a time interleaving ADC according to the number of channels of the time interleaving ADC.

Specifically, FIG. 3A shows interleaving spurs due to mismatch between channels in a time interleaving ADC including an even number of channels, and FIG. 3B illustrates a channel in a time interleaving ADC including an odd number of channels. Interleaving spurs due to liver mismatch are shown.

Referring to (a) of FIG. 3 , when an even number of channels are included, even if a narrow bandwidth is formed around the intermediate frequency (IF) of the signal, in-band While interleaving spurs occur, referring to FIG. 3 (b), when an odd number of channels are included, interleaving spurs are not formed in the band around the intermediate frequency (IF) of the signal (In-band). can check that

Therefore, it may be preferable that the number of the plurality of channels included in the bandpass SAR ADC 100 disclosed herein is an odd number in order to prevent interleaving spurs due to mismatch between channels. For example, as shown in FIG. 1 , the SAR converter 110 of the bandpass SAR ADC 100 may include three channels CH _A , CH _B , and CH _C .

4 is a detailed configuration diagram of a SAR converter according to an embodiment of the present application.

Referring to FIG. 4 , the SAR converter 110 of the bandpass SAR ADC 100 according to an embodiment of the present application may include a comparator element 111 and an asynchronous SAR logic structure (Async SAR Logic, 112). there is. The comparator element 111 compares the input signal sampled from the analog signal by the digital-to-analog converter 120 with a predetermined reference voltage, and compares the bit value corresponding to the applied analog signal from the upper bit (MSB) to the lower bit ( LSB) as a circuit element for outputting a digital signal (D _out ) corresponding to the applied analog signal by sequentially determining, ADC), since it is obvious to those skilled in the art, a detailed description thereof will be omitted.

In addition, according to an embodiment of the present application, each of the plurality of channels of the SAR converter 110 is digitally converted in response to the nth sampling period, and then a plurality of capacitor elements C of the digital-to-analog converter 120 are performed. _DAC ) may perform digital conversion corresponding to an n+2th sampling period after two sampling periods based on the residual signal remaining in the DAC.

More specifically, the residual signal V _res generated in response to the n-3 th sampling period (# n-3) in the first channel CH _A of the SAR converter 110 is the n-1 th sampling period ( # n-1) may be applied to the third channel (CH _C ) performing digital conversion, and similarly, in the second channel (CH _B ), in response to the n-2th sampling period (# n-2) The generated residual signal V _res may be applied to the first channel CH _A performing digital conversion for the nth sampling period # n , and the n−1th sampling in the third channel CH _C . The residual signal V _res generated corresponding to the period # n-1 may be applied to the second channel CH _B for performing digital conversion for the n+1th sampling period (# n+1). .

In this regard, the difference between the two sampling periods of the input signal used for digital conversion for a given sampling period (in other words, an analog signal sampled in that period) and the residual signal generated as a result of the digital conversion before two sampling periods (in other words, A bandpass characteristic in which an analog signal applied by a delay of z ⁻² ) is converted into a digital signal corresponding to a predetermined passband may be implemented by the bandpass SAR ADC 100 .

In addition, according to an embodiment of the present application, the residual signal has a predetermined sampling period so that digital conversion performed in a predetermined sampling period may be performed based on the input signal for the corresponding sampling period and the residual signal before two sampling periods. After being generated for and stored in a residual filter, it may be applied to the SAR converter 110 . Exemplarily, the residual filter may include a storage element for storing the residual signal for two sampling periods, for example, the storage element may be a capacitor element C _RES . Specifically, according to an embodiment of the present application, the capacitor element C _RES as the storage element is a predetermined sampling through charge sharing with the plurality of capacitor elements C _DAC of the digital-analog converter 120 . After the digital conversion for the period is completed, the residual signals remaining in the plurality of capacitor elements C _DAC may be stored.

5 is a detailed configuration diagram of a digital-to-analog converter according to an embodiment of the present application.

Referring to FIG. 5 , the digital-to-analog converter 120 is connected to an input terminal of an analog signal, and is closed at a preset sampling period so that the applied analog signal is sampled through a plurality of capacitor elements C _DAC . (121) and a plurality of capacitor elements (C _DAC ) for sampling the analog signal to the input signal based on the sampling period may include.

Also, according to an exemplary embodiment of the present disclosure, the plurality of capacitor devices C _DAC may include M capacitor devices including the first capacitor device C ₁ to the Mth capacitor device C _M . For example, when the number of bits of the output digital signal determined in consideration of the resolution of the bandpass SAR ADC 100 is m, the number M of capacitor elements may be determined to be 2 ^m , but is not limited thereto.

As another example, according to the embodiment of the present application, the number (M) of the capacitor elements is determined to be greater than 2 ^m , so that the mismatch shaping unit 130 to be described later is based on a large number of capacitor elements compared to the number of bits of the output digital signal. The bandpass SAR ADC 100 may be designed to apply data weight averaging (DWA).

The mismatch shaping unit 130 determines the allocation order from the most significant bit to the least significant bit for the plurality of capacitor elements C _DAC based on the digital signal sequentially output through time interleaving from the SAR conversion unit 110 . data weight averaging may be performed.

Here, determining the allocation order for the plurality of capacitor elements C _DAC means that the analog signal applied for a predetermined sampling period is sampled and the residual signal after digital conversion performed in the predetermined sampling period is stored. It may mean rotating (switching) the bit allocation order of the capacitor element C _DAC every sampling period. For example, with respect to a predetermined sampling period, the allocation order is determined so that the first capacitor element corresponds to the MSB bit and the ²ⁿ -th capacitor element corresponds to the LSB bit, the sampling operation is performed, and after the predetermined sampling period, It may mean that the bit charge (allocation) order between the capacitor elements is rotated (switched) to be different from the previously exemplified pattern.

Specifically, the mismatch shaping unit 130 may include a parameter difference (eg, size In order to prevent degradation of the performance of the bandpass SAR ADC 100 due to harmonic components generated by the difference, capacitance difference, etc.), a plurality of capacitor elements (C _DAC ) ) by rotating (switching), the influence of mismatch between capacitor elements is prevented from being biased depending on the parameter value of each of the plurality of capacitor elements (C _DAC ), and the effect of mismatch between capacitor elements is reduced The order of allocation of the plurality of capacitor elements C _DAC may be adjusted in each sampling period so that the sampling period is randomly applied.

In other words, the mis-medium shaping unit 130 outputs the unit elements constituting the digital-to-analog converter 120 to the digital-to-analog converter 120 using each of the capacitor elements as a plurality of unit elements at every sampling period. Rotation (switching) based on the bit information of the digital signal to appropriately change the allocation order of each of the plurality of capacitor elements (C _DAC ) every sampling period, so that the harmonic component is reduced in-band can work

Specifically, the mismatch shaping unit 130 is an assignment order applied to the corresponding channel (in other words, any one of the channels described above) based on the digital signal D _out output from any one of the plurality of channels. can be decided In this regard, referring to FIG. 1 , an arrow indicated in a row corresponding to the first channel CH _A of FIG. 1 is a digital signal output corresponding to the n-3th sampling period from the first channel CH _A. It indicates that the allocation order of the plurality of capacitor elements C _DAC associated with sampling performed in response to the n + 3 th sampling period in the first channel CH _A is determined based on D _out (n-3) can

Similarly, the arrow indicated in the row corresponding to the second channel (CH _B ) of FIG. 1 corresponds to the digital signal D _out (n-2) output in response to the n-2th sampling period in the second channel (CH _B ). It shows that the allocation order of the plurality of capacitor elements C _DAC associated with sampling performed in response to the n+4th sampling period in the second channel CH _B is determined based on the third channel ( The arrow indicated in the row corresponding to CH _C ) is based on D _out (n-1), which is a digital signal output corresponding to the n-1th sampling period in the third channel (CH _C ), the third channel (CH _C ) It may indicate that the allocation order of the plurality of capacitor elements C _DAC associated with sampling performed in response to the n+5th sampling period is determined.

In other words, the mismatch shaping unit 130, based on the digital signal (D _out ) output from any one channel, sampling performed after two cycles based on the corresponding channel (in other words, any one of the above-mentioned channels) It may be to determine the allocation order associated with the operation. That is, on the basis of each of the channels included in the plurality of channels of the SAR converter 110 , the output digital signal may be involved in mismatch shaping associated with a sampling operation after two sampling cycles have elapsed.

More specifically, as shown in FIG. 1 , when the SAR converter 110 includes three channels, in the first channel CH _A , the n-3 th sampling period, the n th sampling period, and the n + 3 th A sampling operation and a digital conversion operation are performed in response to the sampling period, etc., and in the second channel (CH _B ) through time interleaving, in response to the n-2th sampling period, the n+1th sampling period, the n+4th sampling period, etc. Sampling operation and digital conversion operation are performed, and in the third channel (CH _C ), sampling operation and digital conversion operation are performed corresponding to the n-1th sampling period, n+2th sampling period, n+5th sampling period, etc. can

In addition, when the sampling period of the first channel (CH _A ) arrives, the digital generated by the digital conversion operation performed on the first channel (CH _A ) before two sampling periods based on only the first channel (CH _A ) A signal (eg, D _out (n-6)) is reflected in the assignment order of the plurality of capacitor elements C _DAC associated with the sampling period (nth sampling period) of the current time, and this trend is reflected in the remaining channels (The second channel (CH _B ) and the third channel (CH _C )) can be equally applied.

In summary, the mismatch shaping unit 130 performs n+ of the first channel CH _A based on the digital signal D _out (n) outputted in response to the n-th sampling period in the first channel CH _A . An allocation order applied to the sixth sampling period may be determined. In addition, the mismatch shaping unit 130 is configured to perform the second channel CH _B based on the digital signal D _out (n+1) output in response to the n+1th sampling period in the second channel CH _B . It is possible to determine the allocation order applied to the n+7th sampling period of . In addition, the mismatch shaping unit 130 is a third channel (CH _C ) based on the digital signal (D _out (n+2)) output in response to the n+2th sampling period in the third channel (CH _C ) It is possible to determine the allocation order applied to the n+8th sampling period of .

6 is a conceptual diagram for explaining a data weight averaging technique according to an embodiment of the present application.

When the above-described C _DAC allocation sequence pattern is exemplified with reference to FIG. 6 , D _out (value: 3), which is a digital signal output corresponding to the n-14th sampling period in the first channel (CH _A ), includes all channels It can be confirmed that it is involved in the allocation sequence associated with the n-8th sampling period, which is after 6 sampling cycles as a reference (for reference, after two sampling cycles with respect to the first channel CH _A ). is expressed through a dotted line in the horizontal direction connecting the end point of the leftmost arrow shown in FIG. 6 and the start point of the arrow shown for the n-8th sampling period.

In addition, referring to FIG. 6 , the mismatch shaping unit 130 determines the assignment order in the first order from the first capacitor device C ₁ to the Mth capacitor device C _M in the forward assignment and above-mentioned manner. The reverse assignment in which the assignment order is determined in a second order that is opposite to the first order may be alternately applied. Specifically, forward assignment may be represented by an arrow pointing from bottom to top in FIG. 6 , and backward assignment may be represented by an arrow pointing from top to bottom in FIG. 6 .

For example, referring to FIG. 6 , with respect to the first channel CH _A , an arrow corresponding to the n-14th sampling period is a direction corresponding to the forward assignment (from bottom to top), and n- The arrow corresponding to the 8th sampling period is a direction corresponding to the backward assignment (a direction from top to bottom), and the arrow corresponding to the n-2th sampling period is again a direction corresponding to the forward assignment (a direction from the bottom to the top) It can be confirmed that , which is equally applied to the remaining sampling period, and further it can be confirmed that it is equally applied to other channels.

In addition, the mismatch shaping unit 130 may be configured to select a predetermined value among a plurality of capacitor devices C _DAC based on a digital signal D _out outputted in response to a predetermined sampling period (eg, an n-6th sampling period). It is possible to determine a capacitor element corresponding to a starting point of forward allocation or backward allocation applied to a sampling period (eg, an n-th sampling period) after six sampling periods of the sampling period of .

For example, three capacitors in the forward direction from the first capacitor element C ₁ by '3', which is the value of the digital signal D _out , output in response to the n-14th sampling period from the first channel CH _A It is rotated by the element so that the third capacitor element C ₃ is determined as the starting point of the reverse assignment applied to the n-8th sampling period, which is the sampling period after six sampling periods performed by the first channel CH _A , and similarly , is rotated by six capacitor elements in the reverse direction from the third capacitor element (C ₃ ) by '6', which is the value of the digital signal (D _out ) output in response to the n-8th sampling period, and the M-2th capacitor element ( C _M-2 ) may be determined as the starting point of the forward allocation applied to the n-2 th sampling period performed by the first channel CH _A.

The mismatch shaping technique in the present application described in detail above is expressed as Equation 1 below. In other words, the mismatch shaping unit 130 may perform data weight averaging based on a mismatch transfer function according to Equation 1 below.

[Equation 1]

는 미스매치 전달함수를 나타내는 것일 수 있다. 또한, 상기 식 1의 z^-6 텀은 소정의 채널에서 출력된 디지털 신호(D_out)가 여섯 샘플링 주기 후의 샘플링 동작에 적용되는 커패시터 소자의 할당 순서 결정에 영향을 주는 것을 나타내고, '+' 텀은 순방향 할당과 역방향 할당이 교번되어 수행되는 특징을 반영하는 것일 수 있다.here,

may indicate a mismatch transfer function. In addition, the z ^-6 term of Equation 1 indicates that the digital signal D _out output from the predetermined channel affects the determination of the assignment order of the capacitor elements applied to the sampling operation after six sampling cycles, and the '+' term may reflect a characteristic in which forward allocation and backward allocation are alternately performed.

Hereinafter, the harmonic component reduction effect and the degree of change in white noise between the conventional mismatch shaping technique and the mismatch shaping technique disclosed herein will be described with reference to FIGS. 7 to 9 .

7 and 8 are diagrams illustrating changes in white noise and harmonics when a conventional mismatching shaping technique is used.

Specifically, FIG. 7 shows changes in a harmonic component and white noise according to the application of a conventional technique for shaping a mismatch between capacitor elements in a SAR ADC including a single channel, and FIG. The diagram shows changes in harmonic components and white noise when the conventional mismatch shaping technique is applied to a SAR ADC having a time interleaving structure including three channels.

Referring to FIG. 7, (a) of FIG. 7 shows the harmonic component and white noise level before the conventional mismatch shaping technique is applied, and FIG. 7(b) shows the harmonic component after the conventional mismatch shaping technique is applied. and white noise. For reference, the mismatch transfer function for the conventional mismatch shaping technique described with reference to FIGS. 7 and 8 may be expressed by Equation 2 below.

[Equation 2]

는 미스매치 전달함수를 나타내는 것일 수 있다. 또한, 도 7의 (b)를 참조하면, 주파수 성분의 증가에 따라 하모닉 성분이 크게 증가하는 것을 확인할 수 있다.here,

may indicate a mismatch transfer function. Also, referring to FIG. 7B , it can be seen that the harmonic component greatly increases as the frequency component increases.

Also, referring to FIG. 8, (a) of FIG. 8 shows the harmonic component and white noise level before the conventional mismatch shaping technique is applied in the SAR ADC of the time interleaving structure including three channels. (b) shows the change in harmonic component and white noise after the conventional mismatch shaping technique is applied in the SAR ADC of the time interleaving structure including three channels.

Referring to (b) of FIG. 8 , when the conventional mismatch shaping technique is applied, it can be seen that the performance of the entire SAR ADC is deteriorated because the white noise component is rather increased. That is, the conventionally disclosed mismatch shaping technique may not be applicable to a SAR ADC having a time interleaving structure including a plurality of channels.

9 is a diagram illustrating changes in white noise and harmonics according to the mismatch shaping technique of the present application for a bandpass SAR ADC including a plurality of channels.

Referring to FIG. 9 , when mismatch shaping is not applied as shown in FIG. 9 (a) in the bandpass SAR ADC designed so that the intermediate frequency (IF) is 1/4 times the sampling rate, a plurality of Unlike signal-dependent harmonics that occur due to mismatch between capacitor elements C _DAC , when the mismatch shaping technique disclosed herein is applied as shown in FIG. 9 ( b ), in-band It can be seen that the harmonic component is significantly reduced. That is, unlike the conventional mismatch shaping technique applicable only to the ADC of a single channel structure, the bandpass SAR ADC 100 disclosed herein is a time interleaving structure including a plurality of channels (eg, three channels). Also, there is an advantage in that the influence of the harmonic component in the in-band can be reduced.

Hereinafter, a bandpass SAR ADC according to another embodiment of the present application prepared in a pipeline structure including a plurality of stages will be described with reference to FIGS. 10 and 11 .

The description of the bandpass SAR ADC 100 according to an embodiment of the present application described above is, according to an embodiment of the present application, a time interleaving-based bandpass of a pipeline structure according to another embodiment of the present application to be described below. It can be understood through the description of the SAR ADC (10). Therefore, hereinafter, even if omitted, the description of the bandpass SAR ADC 100 according to an embodiment of the present application is based on a time interleaving-based bandpass SAR of a pipeline structure according to another embodiment of the present application. The same may be applied to the ADC 10 .

10 is a conceptual diagram for explaining the structure and function of each of the first stage and the second stage of a time interleaving-based bandpass SAR ADC of a pipeline structure according to another embodiment of the present application, and FIG. 11 is another embodiment of the present application It is a schematic block diagram of the time interleaving-based bandpass SAR ADC of the pipeline structure according to the

10 and 11 , a time interleaving-based bandpass SAR ADC 10 having a pipeline structure according to another embodiment of the present disclosure may include a first stage 1000 and a second stage 2000 .

Also, referring to FIGS. 10 and 11 , the first stage 1000 and the second stage 2000 may each include a plurality of channels. In other words, the bandpass SAR ADC 10 according to another embodiment of the present application is provided in a pipeline structure including two stages, and each stage includes a plurality of channels, so that the time interleaving-based of an analog-digital converter (ADC) can be implemented.

In addition, according to an embodiment of the present application, each of the first stage 1000 and the second stage 2000 is connected to an input terminal of a signal sampled for each stage and a switch element operated to apply a signal every sampling period, digital conversion It may include a comparator element for performing , a capacitor element array for sampling the analog signal applied from the input terminal, and storing the residual signal after digital conversion (MSB conversion or LSB conversion), SAR logic, etc. but is not limited.

In addition, the number of channels of the first stage 1000 of the bandpass SAR ADC according to another embodiment of the present application may be greater than the number of channels of the second stage 2000 . Illustratively, referring to FIG. 10 , the first stage 1000 includes three channels including CH _1,A , CH _1,B and CH _1,C , and the second stage 2000 is CH _{2 , A} and CH _{2, may include two channels including B} , but is not limited thereto, and according to the embodiment of the present application, the first stage 1000 includes three or more channels or the second stage ( 2000) may be designed to include two or more channels.

Hereinafter, for convenience of description of the embodiment of the present application, as shown in FIG. 10 , the first stage 1000 includes three channels and the second stage 2000 includes two channels. Time interleaving The pipeline structure of the base will be mainly described, and the three channels of the first stage 1000 (ie, CH _1,A , CH _1,B and CH _1,C in FIG. 10 ) are respectively a first channel to a second channel. It is referred to as three channels, and the two channels of the second stage 2000 (ie, CH _2,A and CH _2,B in FIG. 10 ) are referred to as a fourth channel and a fifth channel, respectively.

The plurality of channels of the first stage 1000 may sequentially sample the input analog signal V _in through time interleaving to generate the first input signal (S/H ₁ ). Here, sequential sampling through time interleaving means, referring to FIG. 10 , after sampling by a first channel is performed, sampling by a second channel is performed, and sampling by a second channel is performed, Sampling by the third channel is performed, and after sampling by the third channel is performed, a series of sequential sample and hold (Sample & Hold) (Sample & Hold) in a predetermined order among a plurality of channels in which sampling by the first channel is performed again Hold) can be understood as meaning an operation. More specifically, each of a plurality of channels (eg, each of the first to fifth channels) included in the first stage 1000 and the second stage 2000 of the bandpass SAR ADC according to another embodiment of the present application may perform sampling on the sequentially input signal based on a preset sampling period. In this regard, each sampling period may be referred to as an n-3 th period, an n-2 th period, an n-1 th period, an n th period, an n+1 th period, etc. according to the passage of time.

In addition, the plurality of channels of the first stage 1000 perform MSB conversion ('Convs' process in FIG. 10) based on the generated first input signal, and the upper bit corresponding to the input analog signal (V _in ) The digital signal D ₁ and the first residual signal V _RES1 may be output.

In addition, the plurality of channels of the first stage 1000 may amplify the first residual signal V _RES1 output (generated) by MSB conversion ('Amp' process in FIG. 10 ).

In addition, according to another embodiment of the present application, the first stage 1000 is shared by a plurality of channels of the first stage 1000, the first residual generated by each of the plurality of channels of the first stage 1000 A single amplifier 101 that alternately amplifies the signal V _RES1 according to a preset period may be included. Here, the preset period may correspond to the above-described sampling period. Also, the amplifier 101 may be an operational transconductance amplifier (OTA).

On the other hand, as shown in FIG. 10 , when the plurality of channels of the first stage 1000 includes the first channel, the second channel, and the third channel, the analog signal V _in for the n-th period in the first channel ) while sampling (S/H ₁ (#n)), in the second channel, the amplification of the first residual signal for the n-2th cycle is performed (Amp), and in the third channel, the n-1th cycle MSB conversion may be performed on the first input signal with respect to the period (Convs).

In addition, the plurality of channels of the second stage 2000 may generate a second input signal by sequentially sampling the first residual signal V _RES1 amplified by the amplifier 101 through time interleaving (S/ H ₂ ). Here, sequential sampling through time interleaving means, referring to FIG. 10 , after sampling by the fourth channel is performed, sampling by the fifth channel is performed, and after sampling by the fifth channel is performed, It may be understood to mean a series of sequential sample and hold operations according to a predetermined order among a plurality of channels in which sampling by the fourth channel is performed again.

In summary, each of the plurality of channels of the first stage 1000 is sequentially applied to the plurality of channels of the second stage 2000 with the first residual signal V _RES1 corresponding to each of the sampled first input signals. Each of the plurality of channels of the second stage 2000 may receive the first residual signal V _RES1 from each of the plurality of channels of the first stage 1000 and sequentially sample the second input signal .

In addition, according to another embodiment of the present application, the amplification operation of the first residual signal (V _RES1 ) by the amplifier 101 of the first stage 1000 and the second stage amplified by the plurality of channels of the second stage 2000 The sampling operation S/H ₂ for one residual signal V _RES1 may be synchronized and proceeded together with reference to FIG. 10 .

In other words, the STG1 V _RES1 arrow of FIG. 10 indicates that the first residual signal V _RES1 is amplified by the amplifier 101 and directly transferred to a plurality of channels of the second stage 2000 of the second stage 2000 It may indicate that sampling (S/H ₂ ) is performed in each of the plurality of channels. In this regard, if the plurality of channels of the second stage 2000 include the fourth channel and the fifth channel as shown in FIG. 10 , the first channel to the first channel included in the plurality of channels of the first stage 1000 . Each of the third channels may alternately apply the amplified first residual signal V _RES1 to the fourth channel and the fifth channel according to a preset period (sampling period). In other words, when the first residual signal V RES1 for a predetermined sampling period is transmitted to the fourth channel in the first stage 1000, the first residual signal (V _RES1 ) for the next sampling period of the predetermined sampling period ( V _RES1 ) may be transmitted to the fifth channel, and vice versa.

In addition, each of the plurality of channels of the second stage 2000 performs LSB conversion on the basis of the sampled second input signal ('Convs' process in FIG. 10), and the lower bit corresponding to the input analog signal (V _in ) The digital signal D ₂ and the second residual signal V _RES2 may be output.

Also, referring to FIG. 10 , when the plurality of channels of the second stage 2000 include the fourth channel and the fifth channel, sampling for generating a second input signal corresponding to the nth period in the fourth channel While this is performed (S/H ₂ (#n)), LSB conversion may be performed on the second input signal generated in the n−1 th period in the fifth channel (Convs).

In addition, in relation to the number of channels of a plurality of channels for time interleaving of the first stage 1000 and the second stage 2000, as described above in detail with reference to FIG. 10, in the first stage 1000, sampling ( S/H ₁ of FIG. 10), MSB conversion (Convs of FIG. 10), and amplification of residual signals (Amp of FIG. 10). An operation cycle including three distinct processes is repeatedly performed on each of a plurality of channels, In the second stage 2000, an operation cycle including two distinct processes of sampling (S/H ₂ in FIG. 10) and LSB conversion (Convs in FIG. 10) may be repeatedly performed on each of a plurality of channels, such A difference in the operation cycle exists between the first stage 1000 and the second stage 2000, in other words, in the first stage 1000, unlike the second stage 2000, the first residual signal V _RES1 An additional process called amplification may be performed.

Accordingly, since the time required to complete one operation cycle in each channel of the second stage 2000 is longer than the time required to complete one operation cycle in each channel of the first stage 1000, the second stage In 2000, the lower bit conversion based on the first residual signal V _RES1 applied from each of the channels of the first stage 1000 can be performed with only a small number of channels compared to the first stage 1000 . Accordingly, according to an embodiment of the present application, the number of channels of the first stage 1000 may be greater than the number of channels of the second stage 2000 .

In addition, referring to FIG. 11 , the amplifier 101 amplifies the first residual signal V _RES1 and the second residual signal V _RES2 generated in response to the analog signal V _in applied before two cycles together. can do. Specifically, referring to FIG. 11 , the amplifier 101 is provided to receive two inputs (2-Input AMP), and any one of the two inputs is a first residual signal ( V _RES1 ), and the other one of the two inputs is the second residual signal V _RES2 generated in the second stage 2000 , the first residual signal V _RES1 applied to the amplifier 101 and the second residual A signal (V _RES2 ) may have a difference (Z ⁻² ) between two sampling periods. At this time, referring to FIG. 11 , the second residual signal V _RES2 delayed twice (in other words, by two sampling periods) is applied to the amplifier 101 after passing through the 1/G block to match the signal size. can be

In addition, referring to FIG. 11 , a resonator having a high Q-factor in the bandpass SAR ADC is implemented through the amplifier 101 which is an interstage amplifier between the first stage 1000 and the second stage 2000 . it may be

In addition, the analog signal Vin input by the difference (two-period delay) between the two sampling periods of the first residual signal V _RES1 and the second residual signal V _RES2 applied to the amplifier 101 has a predetermined passband Bandpass characteristics and noise shaping that are converted into a digital signal corresponding to may be implemented. In other words, the bandpass SAR ADC according to another embodiment of the present application transmits the residual signal (in other words, the second residual signal (V _RES2 ) after LSB conversion to the next pipeline stage - Error-feedback) structure Second-order bandpass noise-shaping can be achieved by implementing z ^-2 based residual filter characteristics.

In addition, the bandpass SAR ADC according to another embodiment of the present application may have a bandpass characteristic at which the intermediate frequency (IF) is 1/4 times the sampling rate (F _s ) (IF = F _s ) /4).

In addition, each of the plurality of channels of the second stage 2000 generates a second input signal based on a sampling result for the amplified first residual signal V _RES1 and the second residual signal V _RES2 . there is. Specifically, the second residual signal (V _RES2 ) delayed twice (in other words, by two sampling periods) in the process of the quantization (Quantization, Q ₂ ) of the comparator 201 provided for the plurality of channels of the second stage 2000 . ) is applied through a feed-forward (FF) path and using it to perform sampling to generate a second input signal, in-band quantization noise is attenuated. it could be In addition, according to an embodiment of the present application, the second residual signal V _RES2 delayed twice is converted in size by a predetermined ratio (eg, 3/4 times, etc., referring to FIG. 11 ) to the second stage (2000) may be applied to the comparator 201 .

Hereinafter, an operation flow of the present application will be briefly reviewed based on the details described above.

12 is an operation flowchart of a mismatch correction method for a bandpass SAR ADC based on time interleaving according to an embodiment of the present application.

The mismatch correction method for the time interleaving-based bandpass SAR ADC shown in FIG. 12 may be performed by the bandpass SAR ADC 100 described above. Therefore, even if omitted below, the description of the bandpass SAR ADC 100 may be equally applied to the description of the mismatch correction method for the bandpass SAR ADC based on time interleaving.

Referring to FIG. 12 , in step S11 , the mismatch shaping unit 130 determines the allocation order from the most significant bit to the least significant bit for the plurality of capacitor devices C _DAC based on the previously outputted digital signal D _out . data weight averaging may be performed.

Next, in step S12, the digital-to-analog converter 120 sequentially samples the analog signal based on the plurality of capacitor elements C _DAC through time interleaving to generate an input signal to be applied to the plurality of channels. .

Next, in step S13 , each of the plurality of channels of the SAR converter 110 may perform digital conversion based on the applied input signal to output a digital signal D _out corresponding to the analog signal.

In the above description, steps S11 to S13 may be further divided into additional steps or combined into fewer steps, according to an embodiment of the present application. In addition, some steps may be omitted if necessary, and the order between steps may be changed.

The mismatch correction method for the time interleaving-based bandpass SAR ADC according to an embodiment of the present application may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the present invention, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

In addition, the above-described time interleaving-based mismatch correction method for the bandpass SAR ADC may be implemented in the form of a computer program or application executed by a computer stored in a recording medium.

The foregoing description of the present application is for illustration, and those of ordinary skill in the art to which the present application pertains will understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present application. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. For example, each component described as a single type may be implemented in a dispersed form, and likewise components described as distributed may be implemented in a combined form.

The scope of the present application is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present application.

100: time interleaving based bandpass SAR ADC
110: SAR conversion unit
111: comparator element
120: digital-analog conversion unit
121: switch element
C _DAC : a plurality of capacitor elements

Claims (12)

A time interleaving-based bandpass SAR ADC, comprising:
a SAR converter including a plurality of channels for sequentially outputting digital signals corresponding to the analog signals by performing digital conversion on the basis of an input signal sampling an analog signal at each preset sampling period;
a digital-to-analog converter including a plurality of capacitor elements for sampling the analog signal as the input signal based on the sampling period; and
A mismatch shaping unit that performs data weight averaging for determining an allocation order of the plurality of capacitor elements corresponding to each bit from the most significant bit to the least significant bit of the input signal based on the digital signal;
A bandpass SAR ADC comprising: According to claim 1,
The mismatch shaping unit,
Based on the digital signal output from any one of the plurality of channels, the bandpass SAR ADC is to determine the allocation order applied to the one channel. 3. The method of claim 2,
The mismatch shaping unit,
Based on the digital signal output from the one channel, the allocation sequence associated with the sampling operation performed two periods later based on the one channel is determined. 3. The method of claim 2,
The plurality of channels includes a first channel, a second channel, and a third channel,
The mismatch shaping unit,
determining the allocation order applied to the n+6th sampling period of the first channel based on the digital signal output in response to the nth sampling period in the first channel;
determining the allocation order applied to the n+7th sampling period of the second channel based on a digital signal output corresponding to the n+1th sampling period in the second channel;
and determining the allocation order applied to the n+8th sampling period of the third channel based on a digital signal output corresponding to the n+2th sampling period in the third channel. 5. The method of claim 4,
The plurality of capacitor elements includes a first capacitor element to an M-th capacitor element,
The mismatch shaping unit,
Forward allocation for determining the allocation order in a first order, which is an order from the first capacitor element to the M-th capacitor element, and a reverse allocation for determining the allocation order in a second order opposite to the first order A bandpass SAR ADC, characterized in that it is applied alternately. 6. The method of claim 5,
The mismatch shaping unit,
Determining a capacitor element corresponding to the starting point of the forward allocation or the reverse allocation applied to the n-th sampling period among the plurality of capacitor elements based on the digital signal output in response to the n-6th sampling period, Bandpass SAR ADC. 7. The method of claim 6,
The mismatch shaping unit,
Performing the data weight averaging based on the mismatch transfer function according to Equation 1 below,
[Equation 1]

Here, the

is the mismatch transfer function, and z is a variable representing the conversion of a discrete time domain signal to the frequency domain. According to claim 1,
The SAR conversion unit,
Bandpass SAR ADC to perform the digital conversion corresponding to the n+2th sampling period based on the residual signal remaining in the digital-analog converter after the digital conversion is performed corresponding to the nth sampling period . 9. The method of claim 8,
Bandpass SAR ADC in which the analog signal is converted into a digital signal corresponding to a predetermined passband by a difference between two sampling periods of the sampled analog signal used for the digital conversion and the residual signal is implemented . A method for correcting mismatch for a bandpass SAR ADC based on time interleaving, comprising:
generating input signals to be applied to a plurality of channels by sequentially sampling analog signals based on a plurality of capacitor elements through time interleaving; and
outputting a digital signal corresponding to the analog signal by performing digital conversion by each of the plurality of channels based on the input signal;
including,
The step of generating the input signal comprises:
performing data weight averaging for determining an allocation order of the plurality of capacitor elements corresponding to each bit from the most significant bit to the least significant bit of the input signal based on the digital signal;
That comprising a, mismatch correction method. 11. The method of claim 10,
The plurality of channels includes a first channel, a second channel, and a third channel,
Performing the data weight averaging (Data Weight Averaging),
determining the allocation order applied to the n+6th sampling period of the first channel based on the digital signal output in response to the nth sampling period in the first channel;
determining the allocation order applied to the n+7th sampling period of the second channel based on a digital signal output corresponding to the n+1th sampling period in the second channel;
The method for correcting mismatch is to determine the assignment order applied to the n+8th sampling period of the third channel based on a digital signal output corresponding to the n+2th sampling period in the third channel. 12. The method of claim 11,
Performing the data weight averaging (Data Weight Averaging),
Performing the weighted averaging (Data Weight Averaging) based on the mismatch transfer function according to Equation 1 below,
[Equation 1]

Here, the

is the mismatch transfer function, and z is a variable representing the transformation of a discrete time domain signal to a frequency domain.

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