KR20220142686A - Time-interleaved SAR ADC with comparator offset-based timing-skew calibration and comparator offset-based timing skew correction method using the same - Google Patents

Abstract

Disclosed are a time interleaved successive approximation register analog-to-digital converter to which comparator offset-based timing skew correction is applied and a comparator offset-based timing skew correction method using the same. According to the present invention, provided is a time interleaved successive approximation register analog-to-digital converter comprising: a window detector that detects whether an analog input voltage is within a preset window width; a plurality of sub-channel successive-approximation (SAR) ADCs converting the analog input voltage into a digital signal when the analog input voltage is located within the window width; a phase generator generating sampling clock phases of the plurality of sub-channel SAR ADCs and the window detector through an external clock; a Variable Delay Line (VDL) outputting a sampling clock for controlling switching elements corresponding to the plurality of sub-channel SAR ADCs and the window detector by delaying the sampling clock phases; a comparator offset correction unit correcting offsets of comparators included in the window detector and the plurality of sub-channel SAR ADCs through digital signals output from the plurality of sub-channel SAR ADCs; and a timing skew correction unit for controlling the VDL by generating a timing skew correction code using a comparator offset determined by the comparator offset correction unit. It is possible to detect mismatch errors with low power and high efficiency.

Description

Time-interleaved SAR ADC with comparator offset-based timing-skew calibration and comparator offset-based timing skew using comparator offset-based timing skew correction correction method using the same}

The present invention relates to a time-interleaved successive approximation register analog-to-digital converter to which a comparator offset-based timing skew correction is applied, and a comparator offset-based timing skew correction method using the same. It relates to a low-power, low-area correction technique for error correction by

Time-interleaved successive approximation register analog-to-digital converter (hereinafter referred to as 'time-interleaved successive-approximation (SAR) ADC') maintains the advantages of low power and high efficiency of SAR ADC and overcomes the slow speed, which is a disadvantage of SAR ADC. to be.

Time-interleaved SAR ADC has a structure in which multiple sub-channel SAR ADCs operate sequentially and increases the speed with the same effect as one SAR ADC. crazy

Among the many mismatches, the timing skew mismatch causes an input-dependent error with the magnitude and phase of the error changing with the input frequency.

Various correction techniques have been proposed to solve the timing skew mismatch, but in the case of a method of calculating the variance of a digital output to detect an error caused by mismatch, very complex digital logic such as a multiplier for variance calculation is required.

This not only increases the difficulty of the design, but also has a problem of undermining the advantages of low power and high efficiency of the SAR ADC.

In addition, when an error is detected using the speed of the comparator, an additional correction technique is required because the speed of the comparator is very sensitive to the process, power supply voltage, and temperature, which also has a problem in hindering the low power and high efficiency of the SAR ADC.

KR registered patent 10-1680080

In order to solve the problems of the prior art, the present invention provides a time-interleaved successive approximation register analog-to-digital converter to which a comparator offset-based timing skew correction that can detect mismatch errors with low power and high efficiency is applied, and a comparator offset-based timing skew using the same. We would like to suggest a correction method.

In order to achieve the above object, according to an embodiment of the present invention,

A time-interleaved successive approximation register analog-to-digital converter to which a comparator offset-based timing skew correction is applied, comprising: a window detector for detecting whether an analog input voltage is located within a preset window width; a plurality of sub-channel successive-approximation (SAR) ADCs for converting the analog input voltage into a digital signal; a phase generator for generating sampling clock phases of the plurality of sub-channel SAR ADCs and the window detector through an external clock; a variable delay line (VDL) for delaying the sampling clock phase to output a sampling clock for controlling the switching elements corresponding to the plurality of sub-channel SAR ADCs and the window detector; a comparator offset correcting unit for correcting offsets of comparators included in the plurality of sub-channel SAR ADCs and the window detector through digital signals output from the plurality of sub-channel SAR ADCs; and a timing skew correction unit controlling the VDL by generating a timing skew correction code through the comparator offset determined by the comparator offset correction unit when the analog input voltage is located within the window width. An analog-to-digital converter is provided.

The timing skew correction unit controls the VDL through the timing skew correction code to align sampling clocks of switching devices corresponding to the plurality of sub-channel SAR ADCs with a sampling clock for controlling a switching device corresponding to the window detector. By doing so, the timing skew mismatch can be corrected.

Each of the plurality of sub-channel SAR ADCs includes a main capacitive-digital-to-analog converter (CDAC), a reference CDAC, and a plurality of differential-difference comparators (DDCs), wherein the plurality of DDCs include a sampled input differential voltage ( input differential voltage) may be compared with a plurality of reference voltages generated by the reference CDAC to determine 2 bits in a decision cycle.

The window detector may include a main capacitive-digital-to-analog converter (CDAC), a reference CDAC, and a plurality of differential comparators.

The comparator offset correcting unit may sequentially correct offsets of the plurality of DDCs included in each of the plurality of sub-channel SAR ADCs and the differential comparator included in the window detector when the analog input voltage is located within the window width. can

The comparator offset correcting unit may include: a comparator outputting a comparison result of input signals after shorting the differential input voltage to a common mode voltage; an up-down counter for outputting a specific code by inputting the output of the comparator; and an offset correcting unit for correcting a comparator offset by receiving the specific code as an input.

The differential comparator includes a plurality of pre-amplifiers, a plurality of latches, a plurality of reset switches, a dummy input transistor for reducing kickback noise, and a plurality of offset correction transistors. When turned on, the comparison error can be corrected with the correction current.

The differential comparator of the window detector converts the switched capacitor on the positive input side of the differential CDAC including the main capacitive-digital-to-analog converter (CDAC) and the reference CDAC from VDD to GND so that the sampled input difference is not desired. It can be output by converting it to the sum of the window comparator offset (-OS) and the desired window comparator offset (-OS _WD ).

A window width of the window detector may be determined by a ratio of the switched capacitor.

The timing skew correcting unit may correct the timing skew based on an average absolute deviation.

The timing skew correcting unit may include: a digital integrator for integrating an average absolute value of the digital outputs of the plurality of sub-channel SAR ADCs for each period; and the skew arbitration/correction unit controlling the adjustment direction of the VDL by comparing the average absolute value with a previous period to determine whether the timing skew is decreased or increased compared to the previous period.

According to another aspect of the present invention, there is provided a method for comparator offset-based timing skew correction of a time-interleaved successive approximation register analog-to-digital converter, the method comprising: generating sampling clock phases of a plurality of sub-channel SAR ADCs and a window detector through a phase generator; outputting a sampling clock for controlling a switching element corresponding to the plurality of sub-channel SAR ADCs and the window detector by delaying the sampling clock phase through a variable delay line (VDL); detecting whether an analog input voltage is located within a preset window width through the window detector; converting the analog input voltage into a digital signal through the plurality of sub-channel successive-approximation (SAR) ADCs; correcting offsets of the plurality of sub-channel SAR ADCs and comparators included in the window detector through digital signals output from the plurality of sub-channel SAR ADCs; and controlling the VDL by generating a timing skew correction code through the offset of the corrected comparator when the analog input voltage is located within the window width. An offset-based timing skew correction method is provided.

According to the present invention, since the mean absolute deviation method is used, a complex multiplier is not used and it can be implemented using only an adder, thereby maintaining the advantages of a low-power and high-efficiency SAR ADC.

In addition, according to the present invention, since the comparator offset is determined by the ratio of the capacitor, it is possible to compensate for timing skew mismatch that is insensitive to changes in process, power supply voltage, and temperature.

1 is a diagram illustrating a time-interleaved successive approximation register analog-to-digital converter according to a preferred embodiment of the present invention.
2 is a diagram illustrating detailed configurations of a sub-channel SAR ADC and a window detector according to the present embodiment.
3 is a diagram showing the configuration of a differential comparator applied to the window detector according to the present embodiment.
4 is a diagram illustrating a block diagram of a comparator offset correcting unit according to the present embodiment.
5 is a diagram illustrating an input cross-coupled comparator (OS _WD ) of the window detector according to the present embodiment.
6 shows the relationship between window width, calibration accuracy and convergence time.
7 is a diagram illustrating a process of adjusting a comparator offset in a window detector for timing skew detection according to a preferred embodiment of the present invention.
8 is a diagram illustrating a digital output of each sub-channel SAR ADC when there is no timing skew.
9 is a diagram illustrating a block diagram of a timing skew correcting unit according to the present embodiment.

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail.

However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals have been used for like elements.

1 is a diagram illustrating a time-interleaved successive approximation register analog-to-digital converter according to a preferred embodiment of the present invention.

As shown in FIG. 1, the time-interleaved SAR ADC according to the present embodiment includes a phase generator 100, a Variable Delay Line (VDL) 102, and a plurality of sub-channel SAR ADCs (2b/Cycle SAR, 104-n). , a window detector 106 , a comparator offset correcting unit 108 , a timing skew correcting unit 110 , and a multiplexer 112 .

The phase generator 100 generates the sampling clock phase of the sub-channel SAR ADC 104 and the window detector 106 via an external clock.

,

)를 제어하기 위한 샘플링 클록을 출력한다. The VDL 102 delays the phase of the generated sampling clock, so that a plurality of sub-channel SAR ADCs 104 and switching elements corresponding to the window detector 106 (

,

) to control the sampling clock.

The plurality of sub-channel SAR ADCs (2b/Cycle SAR, 104-n) receives an analog input voltage (V _in ) and outputs a digital signal of a predetermined bit (eg, 7 bits).

The multiple sub-channel SAR ADCs 104-n use a 2b/Cycle architecture to significantly improve conversion speed.

The window detector 106 detects whether the analog input voltage is located within a preset window width.

A plurality of sub-channel SAR ADCs 104 convert an analog input voltage into a digital signal.

The comparator offset correcting unit 108 corrects the offsets of the comparators included in the plurality of sub-channel SAR ADCs 104 and the window detector 106 through digital signals converted by each of the plurality of sub-channel SAR ADCs 104 .

The timing skew correcting unit 110 determines whether or not a timing skew occurs through the comparator offset determined by the comparator offset correcting unit 108 and generates a timing-skew calibration code.

)에 맞춰 상기 복수의 서브 채널 SAR ADC(104)에 대응되는 스위칭 소자의 샘플링 클록(

)을 정렬함으로써 타이밍 스큐 부정합을 보정한다. The timing skew correction unit 110 controls the VDL 102 through the timing skew correction code to control the switching element corresponding to the window detector 106 using a sampling clock (

), the sampling clock of the switching device corresponding to the plurality of sub-channel SAR ADCs 104

) to correct the timing skew mismatch.

Hereinafter, a timing skew correction process according to the present embodiment will be described in detail with reference to the drawings.

2 is a diagram illustrating detailed configurations of a sub-channel SAR ADC and a window detector according to the present embodiment.

As shown in FIG. 2A , the sub-channel SAR ADC 104 according to the present embodiment includes a main capacitive-digital-to-analog converter (CDAC) 200, a reference CDAC 202, and three differential-difference comparators (DDCs). , 204).

The three DDCs 204 compare the sampled input differential voltage with the three reference voltages generated by the reference CDAC 202 to determine two bits in a decision cycle.

A nonbinary decision scheme is applied to correct for CDAC settling error and kick-back noise.

In the end, the ADC determines 8 bits including 1-bit redundancy, and a nonbinary-to-binary decoder converts them into 7-bit binary code.

The window detector 106 has a similar structure to the sub-channel SAR ADC except for the input cross-coupled comparator (differential comparator, CMP, 206) used for window detection, which will be described in detail again below.

The comparator offset correction unit 108 according to the present embodiment not only corrects the comparator offset of the sub-channel SAR ADC 104 , but also allows the input cross-coupled comparator to operate as the window detector 106 .

In the architecture according to the present embodiment, a total of 17 comparators are used, 15 DDCs are used for each sub-channel SAR ADC 100 , and the remaining two differential comparators are used for the window detector 106 .

All comparators (DDC and differential comparators) according to this embodiment are sequentially corrected by the comparator offset correction unit 108, and correction data is stored in the registers of each ADC.

The window detector 106 according to the present embodiment has two differential comparators implemented in a strong-ARM latch-based dynamic comparator and operates at high speed while maintaining high power efficiency.

3 is a diagram showing the configuration of a differential comparator applied to the window detector according to the present embodiment.

Referring to FIG. 3 , the differential comparator includes a plurality of pre-amplifiers M _1,2,11 , a plurality of latches M _3-6 , a plurality of reset switches M _7-10 , and a dummy for reducing kickback noise. It may include an input transistor M _Dum and a plurality of offset correction transistors M _F,C .

If V _inp > V _inn , I _p > I _n because the current is different due to the input difference of the differential comparator, then OUT _p and OUT _n are driven to VDD ("1") and GND ("0") by regeneration by the latch. do. Here, the differential comparator output is defined as 1 when OUT _p is VDD.

However, if an offset exists, I _n > I _p despite V _inp > V _inn . In this case, the comparison error may be corrected with the correction current I _pcal by turning on M _F,C connected in parallel with the input transistor M ₂ .

If there is no offset and the input difference is zero, then the comparator output is randomly distributed to either "1" or "0". However, if there is an offset, the output remains either "1" or "0" even if the input difference is zero.

Thus, you can apply the input difference to zero and monitor the differential comparator output to see if there is an offset, which allows you to perform comparator offset correction.

4 is a diagram illustrating a block diagram of a comparator offset correcting unit according to the present embodiment.

Figure 4 shows the overall configuration of the Comparator Offset Calibration Logic and Comparator Offset Calibration Routers and Registers shown at the top of FIG.

As shown in FIG. 4 , the comparator offset correcting unit 108 may include a comparator 400 , an up/down counter 402 , an offset correcting unit 404 , a data router 406 , and a register 408 .

Referring to FIG. 4 , the comparator 400 outputs a comparison result of the input signal after the differential input voltage is short-circuited to the common mode voltage V _cm .

The up-down counter 402 outputs a specific code by receiving the output of the comparator 400 as an input.

When the comparator 400 maintains the output as “1” or “0”, the up-down counter 402 reaches a specific code (OS+ or OS-), and then the offset correction unit 404 receives the specific code as an input to offset the comparator. To compensate for , the correction transistors M _F,C are turned on or off.

If a small offset remains after a series of offset corrections, the comparator output may alternate between "1" and "0", which can be detected by a majority voting method.

That is, the up-down counter 402 competes so that one of them reaches the specific code first, and the correction is performed.

The data router 406 routes the code output by the up-down counter 402, and the register 408 stores it.

5 is a diagram illustrating an input cross-coupled comparator (OS _WD ) of the window detector according to the present embodiment.

As shown in FIG. 5 , when there is no offset, the comparator output should always be opposite regardless of the input voltage, but in the case of the offset, the comparator output becomes the same when the input voltage falls to the window region.

On the other hand, if the input voltage is out of the window region, the comparator output is reversed again. Thus, an input cross-coupled comparator can be used as a window detector, even with unavoidable offsets.

The smaller the window width, the longer the correction convergence time, so it may not be able to keep up with temperature and voltage fluctuations that significantly affect timing skew. On the other hand, the larger the window width, the lower the calibration accuracy.

6 shows the relationship between window width, calibration accuracy and convergence time.

Referring to FIG. 6 , when the window width is W = 1 LSB, 130k or more samples are required to converge within ± 1ps skew. On the other hand, if W = 2 LSB, 70k samples are required to converge within ± 1ps skew.

The convergence time to maintain ±1ps accuracy is half that of W = 1LSB. On the other hand, if W = 10 LSB, only 40k samples are needed to converge, but the accuracy is very low, giving an accuracy of ~6ps. Therefore, considering the balance between convergence time and calibration accuracy, set the window width to 2LSB (±1LSB, ±15mV).

Since the window width of the comparator offset-based window detector according to the present embodiment is determined by the comparator offset, comparator offset control is required to set the window width. To obtain the desired comparator offset, the comparator offset due to process random mismatch must first be corrected.

To this end, it is important to know the amount of comparator offset that can occur due to process random mismatch.

In Monte Carlo simulations and post-layout parasitic extraction, the comparator offset is estimated to be ±48 mV. An additional correction transistor is connected in parallel with the input transistor to correct the comparator offset.

To control the comparator offset 1.5 mV accuracy, the correction currents (I _pcal and I _ncal in Fig. 3) must be much smaller than the main currents (I _p and I _n in Fig. 3). For this purpose, a long channel transistor is used for calibration. Additionally, an additional transistor of 6 bits or more is required to compensate for the ±48mV offset. However, this results in large parasitic capacitance and limits the speed of the comparator.

To solve this problem, coarse-fine calibration is proposed.

First, a short channel transistor covers the ±48mV range with 8.5mV accuracy, and then a long channel transistor controls the comparator offset with 1.5mV accuracy.

Thus, only a 4-bit long channel transistor is required, allowing accurate calibration while maintaining comparator speed.

In practice it is necessary to force the desired window offset (OS _WD ) corresponding to the window width, since the comparator has a random offset which is an unwanted offset.

7 is a diagram illustrating a process of adjusting a comparator offset in a window detector for timing skew detection according to a preferred embodiment of the present invention.

7A-7B , the window detector 106 may include a differential CDAC 700 including a main capacitive-digital-to-analog converter (CDAC) and a reference CDAC, and a differential comparator 702 .

A differential CDAC 700 samples the common-mode voltage (V _cm ) and the switched capacitor (C _WD ) on the positive input side is switched from VDD to GND so that the sampled input difference is undesired window comparator offset (-OS) and the desired window. Convert to "-OS + (-OS _WD )", which is the sum of the comparator offsets (-OS _WD ).

Since this is the same as having an offset of “-OS + (-OS _WD )”, the input difference is changed back to zero when the comparator offset correction unit 108 is corrected.

After storing the corrected offset in the comparator, if V _cm is resampled and C _WD is not converted, the desired window offset OS _WD is forced as shown in Figure 7b. This is because the offset correction corrects the unwanted offset “-OS” and “-OS _WD ” created by the C _WD conversion. Therefore, only the desired offset (OS _WD ) value is left.

Since the window width of the window detector 106 according to the present embodiment is determined by the switched capacitor (C _WD ) ratio and has a structure similar to that of the sub-channel SAR ADC 104, it is insensitive to PVT change than the comparative time-based window detector. . If an offset is forced in both comparators, the comparator can be used as a window detector 106 with only one conversion period.

Finally, the circuit according to this embodiment does not require additional correction to adjust the window width thanks to its resistance to PVT fluctuations. Additionally, only one comparison period is required, eliminating the need for an additional dummy SAR ADC to compensate for input impedance variations.

Hereinafter, a timing skew correction algorithm will be described.

The timing skew correcting unit 110 according to the present embodiment corrects the timing skew based on the mean absolute deviation (MAD), and unlike the variance-based correction, the average absolute deviation does not require a multiplier, so digital complexity and power consumption can be reduced. have.

The details of the MAD-based timing skew correction are as follows.

When there is no timing skew, the digital output, D _out of each sub-channel SAR ADC 104 should be collected close to 0 because the window is set near the zero crossing as shown in FIG. 8 .

Therefore, the average absolute value E (| D _out |) of D _out tends to be very small. However, with timing skew, E (| D _out |) can become very large because D _out is far from zero. Therefore, timing skew can be minimized by adjusting the sampling clock in a direction that minimizes E (|D _out |).

9 is a diagram illustrating a block diagram of a timing skew correcting unit according to the present embodiment.

As shown in FIG. 9 , the timing skew correcting unit 110 according to the present embodiment may include a digital integrator 900 and a skew arbiter & calibrator 902 .

Timing skew correction initially controls VDL 102 to induce or delay the sampling clock in any direction. Then, when the analog input voltage is within the window width, the digital integrator 900 takes the absolute value of D _out and integrates it for each period.

The post-integration skew arbitration/correction unit 902 compares E (| D _out |) with the previous period to determine whether the timing skew decreases or increases compared to the previous period.

Then, when the timing skew decreases, the skew arbitration/correction unit 902 controls the correction to keep the adjustment direction of the VDL 102 the same as before (keep the sampling clock read or delay as in the previous period).

When the timing skew increases, the skew arbitration/correction unit 902 causes the adjustment direction of the VDL 102 to be reversed in the previous period.

In order to better understand the above procedure, let's look at the working example of each block in the nth cycle.

After all D _out of the nth period are integrated by the digital integrator 900 | The nth average value of D _out | E _n (| D _out |) is compared with the previous E _n-1 (| D _out |).

If E _n (| D _out |) ≤ E _n-1 (| D _out |), the skew arbitration/correction unit 902 determines that the calibration is currently working correctly and instructs the calibration process to run the same as the last cycle. do.

In the opposite case, the skew arbitration/correction unit 902 controls to operate opposite to the previous period. Accordingly, the skew arbitration/correction unit 902 controls the VDL 102 to read or delay the sampling clock to reduce timing skew in the (n + 1) th period. Timing skew compensation works in the background to track voltage-temperature changes.

On the other hand, to handle the estimated timing skew (3σ = 25 ps) obtained from Monte Carlo simulation and post-layout parasitic extraction, the control range of VDL 102 is set to ±28 ps and the accuracy is set to ~1 ps at pin = 1.25 GHz. SNR above 40dB. In addition, the delay can be controlled linearly using a coarse microstructure to avoid excessive loading on the VDL.

The above-described embodiments of the present invention have been disclosed for the purpose of illustration, and various modifications, changes, and additions will be possible within the spirit and scope of the present invention by those skilled in the art having ordinary knowledge of the present invention, and such modifications, changes and additions should be regarded as belonging to the following claims.

Claims (12)

A time-interleaved successive approximation register analog-to-digital converter with comparator offset-based timing skew correction, comprising:
a window detector for detecting whether the analog input voltage is located within a preset window width;
a plurality of sub-channel successive-approximation (SAR) ADCs for converting the analog input voltage into a digital signal;
a phase generator for generating sampling clock phases of the plurality of sub-channel SAR ADCs and the window detector through an external clock;
a variable delay line (VDL) for delaying the sampling clock phase to output a sampling clock for controlling the switching elements corresponding to the plurality of sub-channel SAR ADCs and the window detector;
a comparator offset correcting unit for correcting offsets of comparators included in the plurality of sub-channel SAR ADCs and the window detector through digital signals output from the plurality of sub-channel SAR ADCs; and
and a timing skew correction unit for controlling the VDL by generating a timing skew correction code through the comparator offset determined by the comparator offset correction unit when the analog input voltage is located within the window width. - Digital converter. According to claim 1,
The timing skew correction unit controls the VDL through the timing skew correction code to align sampling clocks of switching devices corresponding to the plurality of sub-channel SAR ADCs with a sampling clock for controlling a switching device corresponding to the window detector. A time-interleaved successive approximation register analog-to-digital converter that corrects for timing skew mismatches by According to claim 1,
Each of the plurality of sub-channel SAR ADCs,
a main capacitive-digital-to-analog converter (CDAC), a reference CDAC and a plurality of differential-difference comparators (DDCs);
The plurality of DDCs compare a sampled input differential voltage with a plurality of reference voltages generated by the reference CDAC to determine two bits in a decision cycle, analog-to-digital time-interleaved successive approximation registers. converter. 4. The method of claim 3,
The window detector is
Time-interleaved successive approximation register analog-to-digital converter with main capacitive-digital-to-analog converter (CDAC), reference CDAC and multiple differential comparators. 5. The method of claim 4,
The comparator offset correcting unit is configured to sequentially correct offsets of the plurality of DDCs included in each of the plurality of sub-channel SAR ADCs and the differential comparators included in the window detector. 6. The method of claim 5,
The comparator offset correcting unit,
a comparator for shorting the differential input voltage to a common mode voltage and outputting a comparison result of the input signal;
an up-down counter for outputting a specific code by inputting the output of the comparator; and
and an offset correction unit for correcting a comparator offset by inputting the specific code as an input. 5. The method of claim 4,
The differential comparator includes a plurality of pre-amplifiers, a plurality of latches, a plurality of reset switches, a dummy input transistor for reducing kickback noise, and a plurality of offset correction transistors. A time-interleaved successive approximation resistor analog-to-digital converter that turns on and corrects for comparison errors with a correction current. 5. The method of claim 4,
The differential comparator of the window detector converts the switched capacitor on the positive input side of the differential CDAC including the main capacitive-digital-to-analog converter (CDAC) and the reference CDAC from VDD to GND so that the sampled input difference is not desired. Converted to the sum of the window comparator offset (-OS) and the desired window comparator offset (-OS _WD ) and output Time-interleaved successive approximation register analog-to-digital converter. 9. The method of claim 8,
A time-interleaved successive approximation register analog-to-digital converter in which a window width of the window detector is determined by a ratio of the switched capacitor. According to claim 1,
The timing skew corrector is configured to correct the timing skew based on an average absolute deviation. 11. The method of claim 10,
The timing skew correction unit,
a digital integrator for integrating an average absolute value of digital outputs of the plurality of sub-channel SAR ADCs for each period when the analog input voltage is located within the window width; and
and the skew arbitration/correction unit controlling an adjustment direction of the VDL by comparing the average absolute value with a previous period to determine whether timing skew is decreased or increased compared to the previous period. A method for comparator offset-based timing skew correction of a time-interleaved successive approximation register analog-to-digital converter, comprising:
generating sampling clock phases of a plurality of sub-channel SAR ADCs and a window detector via a phase generator;
outputting a sampling clock for controlling a switching element corresponding to the plurality of sub-channel SAR ADCs and the window detector by delaying the sampling clock phase through a variable delay line (VDL);
detecting whether an analog input voltage is located within a preset window width through the window detector;
converting the analog input voltage into a digital signal through the plurality of sub-channel successive-approximation (SAR) ADCs;
correcting offsets of the plurality of sub-channel SAR ADCs and comparators included in the window detector through digital signals output from the plurality of sub-channel SAR ADCs; and
and controlling the VDL by generating a timing skew correction code through the corrected offset of the comparator when the analog input voltage is located within the window width. based timing skew correction method.

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