CN107171668A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
CN107171668A
CN107171668A CN201710102441.6A CN201710102441A CN107171668A CN 107171668 A CN107171668 A CN 107171668A CN 201710102441 A CN201710102441 A CN 201710102441A CN 107171668 A CN107171668 A CN 107171668A
Authority
CN
China
Prior art keywords
capacitor
switch
capacitance
reference voltage
redundant digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710102441.6A
Other languages
Chinese (zh)
Other versions
CN107171668B (en
Inventor
船户是宏
森本康夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN107171668A publication Critical patent/CN107171668A/en
Application granted granted Critical
Publication of CN107171668B publication Critical patent/CN107171668B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/22—Analogue/digital converters pattern-reading type
    • H03M1/24—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip
    • H03M1/26—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with weighted coding, i.e. the weight given to a digit depends on the position of the digit within the block or code word, e.g. there is a given radix and the weights are powers of this radix
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Abstract

The present invention relates to a kind of semiconductor device.Electric capacity DAC (digital analog converter) circuits and comparator are had according to the semiconductor device of the present invention.The electric capacity DAC-circuit includes：First capacitor, the capacitance that each capacitor in input signal and the first capacitor is respectively provided with the weight corresponding to position to be converted is given to it；And second capacitor, give common electric voltage to it and its capacitance sum is equal with the capacitance of first capacitor.Further, second capacitor includes：Redundant digit capacitor, it has the capacitance of the weight corresponding to redundant digit；And adjustment capacitor, adjust each capacitor in capacitor and be respectively provided with the capacitance as obtained by the capacitance that the redundant digit capacitor is subtracted from the capacitance sum of second capacitor.

Description

Semiconductor device
The cross reference of related application
The Japanese patent application No. 2016-043276's that on March 7th, 2016 submits includes specification, accompanying drawing and summary It is open to be herein incorporated by reference with entire contents.
Technical field
The present invention relates to a kind of semiconductor device, for example, it is related to a kind of semiconductor device including analog to digital conversion circuit.
Background technology
In semiconductor devices, it is that the processing about analog signal is performed in digital circuit, using analog to digital conversion circuit, The analogue value of analog signal is converted into digital value by it.A type of analog to digital conversion circuit is gradually to compare type analog-to-digital conversion electricity Road.In type analog to digital conversion circuit is gradually compared, there is execution redundancy ratio and relatively operate to correct by various noises and the steady error that becomes The situation of caused erroneous judgement.
Therefore, non-patent literature 1, which is disclosed, performs example of the redundancy ratio compared with the analog to digital conversion circuit of operation.On non-patent The analog to digital conversion circuit of document 1, input signal is provided with differential signal, and provides comparator and two wirings, by this two Differential signal is transferred to comparator by individual wiring.Thus, in the analog to digital conversion circuit of non-patent literature 1, some electric capacity Utensil has one corresponding to electric capacity of equal weight etc., and in the electrostatic condenser changed using the same capacitance to hold Row redundancy ratio is relatively handled.Then, by performing the relatively processing of this redundancy ratio, the analog to digital conversion circuit correction of non-patent literature 1 is missed Sentence.
[non-patent literature]
[non-patent literature 1] C.C.Liu, " the mW SAR ADC with of 100 message store/s of A 10b 1.13 Binary-scaled error compensation ", ISSCC, 2010.
The content of the invention
On analog to digital conversion circuit, although there is a kind of type for using differential signal as input signal, but not Several types for using single-ended signal as input signal.However, it is difficult to adopt as it is for institute's public affairs in non-patent literature 1 Open performed in the analog to digital conversion circuit of type redundancy ratio compared with circuit configuration, wherein using differential signal as to using single-ended letter Number as input signal analog to digital conversion circuit (hereinafter referred to as " single-ended analog to digital conversion circuit ") input signal.
Specifically, in single-ended analog to digital conversion circuit, the wiring (example only in the input terminal coupled to comparator Such as, coupled to comparator reversed input terminal wiring) one end set and give the electricity of weighting corresponding to position to be converted Container.Thus, when in single-ended analog to digital conversion circuit according to redundancy ratio relatively to perform correct operation when, to obtain the negative of correction Weighting, the routine before must changing the redundancy ratio relatively compares the transformation result of operation.Therefore, when the fixed Change-over knot of change During fruit, it is necessary to perform the calculating for reversely changing fixed transformation result or using the table for being used to change transformation result Lattice change transformation result.
Using any above method, the gradually comparison resistance of the change request of this transformation result in analog to digital conversion circuit The circuit postponed greatly is provided in logic.Thus, above-mentioned requirements largely have impact on arrives comparator during operation is compared Input signal convergence time.That is, ought use as it is based on the Differential Input type disclosed in non-patent literature 1 Analog to digital conversion circuit redundancy ratio compared with configuration, the problem of conversion ratio is reduced occurs in single-ended analog to digital conversion circuit.
Refering to following description and appended claims, there are other problems to be solved and novel features will be aobvious and easy See.
According to one embodiment, a kind of semiconductor device includes：Electric capacity DAC (digital analog converter) circuit；And comparator, It changes output signal based on the relative size relation of two signals from electric capacity DAC (digital analog converter) circuit output Logic level.The electric capacity DAC-circuit includes：First compares wiring, and it is coupled with multiple first capacitors, by input signal Be given in the multiple first capacitor and the multiple first capacitor each is respectively provided with corresponding to position to be converted The capacitance of weight；And second compare wiring, it is coupled with multiple second capacitors, and common electric voltage is given into the multiple The capacitance sum of two capacitors and the multiple second capacitor is equal to the capacitance of first capacitor.Enter one Step, second capacitor includes：Redundant digit capacitor, it has the capacitance of the weight corresponding to redundant digit；And adjustment Capacitor, it has the capacitance institute by subtracting the redundant digit capacitor from the capacitance sum of second capacitor The capacitance obtained.
According to above-described embodiment 1, the semiconductor device can perform at a higher speed including redundancy ratio compared with conversion behaviour Make.
Brief description of the drawings
Fig. 1 is the block diagram for showing the semiconductor device according to embodiment 1；
Fig. 2 is the block diagram for showing the analog to digital conversion circuit according to embodiment 1；
Fig. 3 is the circuit diagram for showing the electric capacity DAC-circuit according to embodiment 1；
Fig. 4 is to show to control circuit according to the redundant digit of embodiment 1 and the register of circuit is controlled corresponding to redundant digit Block diagram；
Fig. 5 is the diagram for illustrating the binary search path of low 4 in the analog to digital conversion circuit without redundant digit；
Fig. 6 is the diagram for illustrating the binary search path of low 4 in the analog to digital conversion circuit according to embodiment 1；
Fig. 7 is the diagram for illustrating the example of the control of the redundant digit to analog to digital conversion circuit according to embodiment 1；
Fig. 8 is for illustrating showing for the switch control of the electric capacity DAC-circuit to analog to digital conversion circuit according to embodiment 1 Figure；
Fig. 9 is the block diagram for showing the analog to digital conversion circuit according to comparative example；
Figure 10 is the block diagram for showing the electric capacity DAC according to comparative example；
Figure 11 is the diagram for illustrating the example of the control of the redundant digit to analog to digital conversion circuit according to comparative example；
Figure 12 is the circuit diagram for the first modification for illustrating the electric capacity DAC-circuit according to embodiment 1；
Figure 13 is the circuit diagram for the second modification for illustrating the electric capacity DAC-circuit according to embodiment 1；
Figure 14 is the circuit diagram for showing the electric capacity DAC-circuit according to embodiment 2；
Figure 15 is the diagram for illustrating the binary search path in the analog to digital conversion circuit according to embodiment 2；
Figure 16 is the diagram for illustrating the example of the redundant digit of the control analog to digital conversion circuit according to embodiment 2；
Figure 17 is the circuit diagram for showing the electric capacity DAC-circuit according to embodiment 3；
Figure 18 shows the diagram of the control example of the redundant digit for illustrating the analog to digital conversion circuit according to embodiment 3；
Figure 19 is the circuit diagram of the electric capacity DAC-circuit according to embodiment 4.
Embodiment
Hereinafter, for the sake of making explanation apparent, take the circumstances into consideration that some descriptions and accompanying drawing is omitted or simplified.In addition, in accompanying drawing It is each in, identical or corresponding part indicates identical reference, and optionally repeats no more its explanation.
Embodiment 1
First, the semiconductor device according to embodiment 1 will be illustrated.Fig. 1 shows the frame of the semiconductor device according to embodiment 1 Figure.Figure 1 illustrates the example of two semiconductor devices.In the first example of the semiconductor device shown in Fig. 1, the semiconductor Device includes：Analog to digital conversion circuit (ADC) 1；Input/output interface (IO) 2；Rear class signal processing circuit 3；Peripheral circuit 4；Outside Enclose circuit 5；CPU (CPU) 6；And memory 7.In addition, in the second example, replace the input of the first example/ Output interface 2, the semiconductor device includes input/output interface (IO) 8 and prime signal processing circuit 9.
Analog to digital conversion circuit (ADC) 1 is by the input signal VIN of analog signal voltage level conversion is into digital value and incites somebody to action It is output as ADC outputs.Input/output interface 2 and 8 makes from the outside signal input semiconductor device given.In addition, defeated Enter/output interface 2 and 8 exports the signal that generates in semiconductor devices.For example, rear class signal processing circuit 3 is that ADC is exported Perform the circuit of the signal transacting of such as filtering process.Peripheral circuit 4 is included by the peripheral circuits used of CPU 6 and by CPU Analog circuit among the peripheral circuit of 6 controls.Peripheral circuit 4 can be operational amplifier, reference voltage generating unit, common electrical Press generating unit or oscillating circuit.In the peripheral circuit 5 used by CPU 6 and among the peripheral circuit that CPU 6 is controlled, Peripheral circuit 5 includes digital circuit.For example, peripheral circuit 5 can be the circuits such as coprocessor, timer.For example, CPU The program stored in 6 execution holders 7.In addition, CPU 6 carrys out Control peripheral circuit 4 and 5 using result of calculation, at the same time, The result that is obtained using the processing by peripheral circuit 5 performs calculating.For example, holder 7 is preserved used in CPU 6 Program and data.The input signal VIN that 9 pairs of prime signal processing circuit is given to analog to digital conversion circuit 1 performs pretreatment.Pretreatment It can be the amplification of analog signal.
There is one in its feature in analog to digital conversion circuit 1 according to the semiconductor device of embodiment 1.Below will be detailed Describe bright analog to digital conversion circuit 1 in detail.Fig. 2 shows the block diagram of the analog to digital conversion circuit according to embodiment 1.
As shown in Fig. 2 being included according to the analog to digital conversion circuit of embodiment 1：Electric capacity DAC (digital analog converter) circuit 10；Than Compared with device 11；Gradually comparand register logic 12；Output circuit 13；And ADC sequential control circuits 14.Based on defeated by comparator 11 The comparative result gone out, analog to digital conversion circuit 1 determines to be given on the basis of (bit-by-bit) by turn from highest order to lowest order The digital value (for example, switch controlling signal Ssar) of electric capacity DAC-circuit 10, and repeat compare be operated such that generation conversion before tie Really.Now, in analog to digital conversion circuit, the value of redundant digit is included in result before switching.Therefore, in analog to digital conversion circuit 1 In, including redundant digit, by changing shown in preceding result value is calculated using output circuit 13, and acquisition is used as modulus to turn Change the ADC outputs of the final output value of circuit 1.
The sampled input signal VIN of electric capacity DAC-circuit 10 and common electric voltage VCM.Then, based on by being posted by gradually comparing The digital value shown in switch controlling signal Ssar that storage logic 12 is exported, electric capacity DAC10 shifts sampled input signal VIN And common electric voltage VCM, with the shift amount corresponding to switch controlling signal Ssar.Further, based on by by gradually comparing The digital value shown in switch controlling signal Ssar that register logical 12 is exported, electric capacity DAC-circuit 10 shifts sampled input Signal VIN and common electric voltage VCM, with the shift amount corresponding to switch controlling signal Ssar.In the illustrated example shown in fig. 2, Input signal VIN conversion value is given to the reversed input terminal of comparator and by common electric voltage VCM's by electric capacity DAC-circuit 10 Conversion value is given to non-inverting input terminal.
The relative size relation of voltage level based on two input terminals to be entered, the switching output signal of comparator 11 The logic level of (for example, comparative result Cout).Gradually tied before the conversion of the generation of comparand register logic 12 analog to digital conversion circuit 1 Really, the value of redundant digit is included.Gradually comparand register logic 12 includes DAC ON-OFF control circuits 21, redundant digit control circuit 22 And register 23.The number of times of comparison operation based on analog to digital conversion circuit 1 and the comparative result exported by comparator 11, DAC ON-OFF control circuits 21 update the switch controlling signal Ssar of the switch control for electric capacity DAC-circuit 10 place value.Redundancy Position control circuit 22 is changed among the switch controlling signal Ssar updated by DAC ON-OFF control circuits 21 place value corresponding to superfluous The position of remaining position.Redundant digit control circuit 22 is made up of combinational circuit.The details of redundant digit control circuit 22 will be described later. Register 23 is preserved by DAC ON-OFF control circuits 21 and the switch controlling signal Ssar that determines of redundant digit control circuit 22 Value.
Based on result before the conversion of the switch controlling signal Ssar including redundant digit when comparing completion, output circuit 13 is calculated Digital value and generation to be output is exported as the ADC of the final output value of analog to digital conversion circuit 1.When redundant digit be 1 simultaneously And using the output of the value of " n " position as ADC export when, analog to digital conversion circuit 1 exports the value of (n+1) as result before conversion.Therefore, Output circuit 13 passes through the value of value calculating n from (n+1), the ADC outputs of output n.ADC sequential control circuits 14 are from clock Exported in signal CLK to comparator 11, the sequential of gradually comparand register logic 12 and the command operating sequential of output circuit 13 Signal.After clock signal is received, comparator 11, gradually comparand register logic 12 and output circuit 13 perform sampling behaviour Make the switching with being compared operation, or determine in response to clock signal the output timing of ADC outputs.
The details of the electric capacity DAC-circuit 10 according to embodiment 1 is described below.Fig. 3 shows the electric capacity according to embodiment 1 The circuit diagram of DAC-circuit 10.In addition, Fig. 3 also illustrates comparator 11 to illustrate the configuration of electric capacity DAC-circuit 10.In addition, Fig. 3 shows Go out state of the switch when operation is compared in execution first.
As shown in figure 3, electric capacity DAC-circuit 10 includes：Capacitor 30 to 39, supply common electric voltage switching switch (for example, Switch SW1 and SW2), switch SW10 to SW19, first compare wiring Wp, second compare wiring Wn, input wiring Win and public affairs Common voltage connects up Wcm.
Compare wiring Wp on first, one end is coupled to the reversed input terminal of comparator 11, and switchs SW1 by coupling It is bonded to the other end.Further, in switch SW1 to be controlled into the period in closure state, compare wiring Wp to first and pass Send common electric voltage VCM.
In addition, one end of two or more the first capacitors (for example, capacitor 30 to 36) is coupled to first and compared Connect up Wp.Capacitor 30 to 36 has the capacitance for the weight for corresponding to the position for changing respectively.In the example shown in Fig. 3 In, it is assumed that 1C is as specific capacitance, and it is 2C (twice of 1C), 4C (four times of 1C), 8C (1C's is octuple) and 16C to form capacitance The capacitor of (16 times of 1C).
Capacitor 30 is the dummy capacitors with 1C capacitances.In the other end of electrostatic condenser 30, first switch is set SW10.First switch SW10 select input signal VIN and low potential side reference voltage V REFN and any one, and by its It is given to the other end of capacitor 30.
Capacitor 31 is the capacitance with the 1C corresponding with the weight of the least significant bit corresponding to transformation result Capacitor.In the other end of capacitor 31, first switch SW11 is set.First switch SW11 selection input signals VIN, high potential Side reference voltage VREFP and low potential side reference voltage V REFN and any one, and be given to the another of capacitor 31 End.
Capacitor 32 is the redundancy of the capacitance with the 2C corresponding with the weight of the redundant digit corresponding to transformation result Position capacitor.In addition, capacitor 32 has and the identical of deputy capacitor 33 corresponding to transformation result described below Capacitance.That is, in the analog to digital conversion circuit 1 according to embodiment 1, have in transformation result LSB and second it Between redundant digit.In the other end of capacitor 32, first switch SW12 is set.First switch SW12 selection input signals VIN, height Current potential side reference voltage VREFP and low potential side reference voltage V REFN and any one, and be given to capacitor 32 The other end.
Capacitor 33 is the electric capacity of the capacitance with the 2C corresponding with the deputy weight corresponding to transformation result Device.In the other end of capacitor 33, first switch SW13 is set.First switch SW13 selection input signals VIN, high potential side base Quasi- voltage VREFP and low potential side reference voltage V REFN and any one, and be given to the other end of capacitor 33.
Capacitor 34 is the electric capacity of the capacitance with the 4C corresponding with the weight of the 3rd corresponding to transformation result Device.In the other end of capacitor 34, first switch SW14 is set.First switch SW14 selects input signal VIN, high potential side base Quasi- voltage VREFP and low potential side reference voltage V REFN and any one, and be given to the other end of capacitor 34.
Capacitor 35 is the electric capacity of the capacitance with the 8C corresponding with the weight of the 4th corresponding to transformation result Device.In the other end of capacitor 35, first switch SW15 is set.First switch SW15 selection input signals VIN, high potential side base Quasi- voltage VREFP and low potential side reference voltage V REFN and any one, and be given to the other end of capacitor 35.
Capacitor 36 is the electric capacity of the capacitance with the 16C corresponding with the weight of the 5th corresponding to transformation result Device.In the other end of capacitor 36, first switch SW16 is set.First switch SW16 selection input signals VIN, high potential side base Quasi- voltage VREFP and low potential side reference voltage V REFN and any one, and be given to the other end of capacitor 36.
Compare wiring Wn on second, one end is coupled to the positive transmission terminal of comparator 11, and switchs SW2 by coupling It is bonded to the other end.Then, in switch SW2 to be controlled into the period of closure state, wiring Wn transmission is compared to second public Voltage VCM.
In addition, one end of two or more the second capacitors (for example, capacitor 37 to 39) is coupled to second and compared Connect up Wn.Capacitor 37 to 39 is used as the first two or more capacitors with same total capacitance value (for example, capacitor 30 To the capacitance of total capacitance 36).Capacitor 39 is the redundant digit capacitor of the capacitance with the weight according to redundant digit.Electricity The total capacitance value of container 37 and 38 is set to the electricity by subtracting redundant digit capacitor from the total capacitance value of capacitor 30 to 36 Capacitance obtained by capacitance.In addition, in the electric capacity DAC-circuit 10 shown in Fig. 3, by public wiring Wcm to capacitor 37 to 39 supply common electric voltages.
In the other end of capacitor 37, second switch SW17 is set.Second switch SW17 is selected and is provided common electric voltage The other end of VCM, hot side reference voltage V REFP or low potential side reference voltage V REFN to capacitor 37.In Fig. 3 institutes In the example shown, low potential side reference voltage V REFN is given to the other end of capacitor 37 by second switch SW17.In electric capacity The other end of device 38 sets second switch SW18.Second switch SW18 is selected and is provided common electric voltage VCM, hot side benchmark The other ends of the voltage VREFP or low potential side reference voltage V REFN to capacitor 38.In the example depicted in fig. 3, is passed through Two switch SW18 give high low potential side base quasi- voltage VREFP the other end of capacitor 38.Set in the other end of capacitor 39 Second switch SW19.Second switch SW19 is selected and is provided common electric voltage VCM, hot side reference voltage V REFP or low The other ends of the current potential side reference voltage VREFN to capacitor 39.
In the example depicted in fig. 3, because redundant digit is arranged at the deputy position corresponding to transformation result, therefore The capacitance of capacitor 39 is configured to 2C.In addition, because the total capacitance value of capacitor 30 to 36 is configured to 34C, then electric capacity The total capacitance value of device 37 and 38 is configured to the 32C as obtained by subtracting 2C from 34C.When transfer process starts, to as superfluous The other end supply low potential side reference voltage V REFN of the capacitor 39 of remaining position capacitor.Thus, using the He of capacitor 37 38 so that the second voltage stabilization for comparing wiring Wn is common electric voltage VCM.Therefore, in electric capacity DAC-circuit 10, conversion is being started After process, it is preferable that allow to be arranged on second compare wiring Wn with supplied to it low potential side reference voltage V REFN wiring it Between the capacitance of capacitor be equal to and be arranged on second and compare wiring Wn and cloth that hot side reference voltage V REFP is supplied to it The capacitance of capacitor between line.Therefore, in the example depicted in fig. 3 so that supply low potential side benchmark to its other end The capacitance of voltage VREFN capacitor 38 with supplied to its other end hot side reference voltage V REFP capacitor 37 and 39 total capacitance value is identical.Specifically, capacitor 39 is 2C, and the total capacitance value of capacitor 37 to 39 is 4C.Therefore so that By using 34C divided by 2 gained 17C as capacitor 38 capacitance, and cause as obtained by subtracting 2C from 17C 15C as capacitor 37 capacitance.In addition, in discussion below, capacitor 37 and 38 is referred to as exemplified by adjustment capacitor.
As shown in figure 3, in electric capacity DAC-circuit 10, transfer process is performed using the resolution ratio of 5, but by 1 redundant digit It is included in the transformation result.That is, by the transformation result and the transformation result of 5 of 1 redundant digit include from by Before the conversion that secondary comparand register logic 12 is exported in result.In addition, before electric capacity DAC-circuit 10 starts conversion process, its Compare wiring Wn in wiring Wp and second is compared in common electric voltage VCM initialization first and sample capacitor 30 to 36 Input signal VIN state.Then, whenever being carried forward in the stage of conversion process, electric capacity DAC-circuit 10 is controlled to switch SW16 to switch SW11 switching.In addition, electric capacity DAC-circuit 10 performs redundancy ratio using capacitor 32 and 39 based on redundant digit Compared with.In figure 3, the circuit comprising capacitor 32 and 39 is made to become redundant digit circuit 40.
It will now describe the details of gradually comparand register logic 12.In view of the above, figure 4 illustrates redundant digit control Circuit processed and corresponding to redundant digit control circuit register block diagram.In addition, figure 4 illustrates redundant digit control circuit 22 be the example that redundant digit controls circuit 22, and various combinational circuits can be used as redundant digit control circuit 22.As shown in figure 4, Redundant digit control circuit 22 has inverter circuit.Inverter circuit reversion in the comparison for immediately corresponding to redundant digit on grasping Make to perform it deputy comparative result Cout [2] for comparing operation before (hereinafter, " redundancy ratio is relatively operated "), and Output this in register 23 and correspond to the register that redundant digit controls circuit 22 to set.
In addition, as register, using d type flip flop, it is when the rising edge of signal is input into triggering input terminal C Sequence keeps being input to input terminal D signal level, until when next time the rising edge of signal is input into triggering input terminal C Sequential.The register of circuit 12 is controlled to be one in included register in register 23 corresponding to redundant digit.In Fig. 4 In shown example, to the register that circuit 22 is controlled corresponding to redundant digit, the clock signal that ADC sequential control circuits 14 are exported The register that circuit 22 is controlled corresponding to redundant digit is input into, trigger signal is used as.It is input to and controls electricity corresponding to redundant digit The clock signal of the register on road 22 has the rising edge until changing the sequential of the weighting of redundant digit.In addition, shown in Fig. 4 The reset signal for being input to d type flip flop circuit is omitted in d type flip flop circuit.However, in d type flip flop circuit, completing to compare Compare the given sequential of operation after operation next time to beginning, output should be reset to low level.
In addition, though not being described by especially in Fig. 4, but compare the superfluous of wiring Wn sides coupled to second except corresponding to Switch controlling signal outside the switch controlling signal Ssar of remaining position is low level in its original state.Further, just performing Compare before operation, so control into them in high level, if the comparative result after operation is compared is high level High level is then kept, controls circuit 22 and register 23 to return it to low electricity by redundant digit if comparative result is low level It is flat.
The operation of the analog to digital conversion circuit 1 according to embodiment 1 is described below.In the analog-to-digital conversion electricity according to embodiment 1 In road 1, by performing the redundancy ratio using redundant digit circuit compared with being corrected to false transitions.In order to illustrate that this mistake turns Change, first, Fig. 5 shows the diagram in the binary search path of low 4 in analog to digital conversion circuit of the description without redundant digit.This Outside, in Fig. 5 diagram and the diagram in subsequent shown binary search path, circled numbers indicate accordingly to compare in execution Weight used in during operation.In analog to digital conversion circuit, for example, when the comparative result of the 5th is low level, the 5th The weight of position is arranged to " 0 ".Then, when performing the comparison operation of the 4th, given by hot side reference voltage V REFP To after the other end of the capacitor 35 with 8C capacitances, the comparison operation of the 4th is performed.When the comparative result of the 4th During for high level, the weight of the 4th is arranged to " 8 ".Then, it is given to by hot side reference voltage V REFP with correspondence After the other end of the capacitor 34 of the 4C capacitances of the 3rd, the comparison operation of the 3rd is performed.On the other hand, when the 4th When the comparative result of position is low level, the weight of the 4th is arranged to " 0 ".Then, by hot side reference voltage V REFP After the other end for being given to the capacitor 34 with the 4C capacitances corresponding to the 3rd, the comparison operation of the 3rd is performed. That is, the weight of utilization " 4 " or " 12 " performs the comparison operation of the 3rd.Figure 5 illustrates binary search path be to retouch State the diagram of such operation of analog to digital conversion circuit.
As shown in figure 5, in analog to digital conversion circuit, repeating to compare operation based on binary search.Therefore, for Up to each final result only one of which searching route.For this reason, if not performing redundancy ratio compared with wrong when occurring in a high position Misroute when changing, there is no correction in final transformation result because of the error caused by false transitions.
Fig. 6 shows to illustrate the diagram in the binary search path of the low sequence 4 in the analog to digital conversion circuit 1 according to embodiment 1. Further, in figure 6, circled numbers show the weight when execution each compares operation.As shown in fig. 6, according to embodiment 1 Analog to digital conversion circuit 1, during the comparison between lowest order and second perform using redundant digit redundancy ratio relatively operate. Redundancy ratio relatively in, transformation result can provide weight and deputy weight identical effect.Specifically, by performing redundancy ratio Compared with, formed for search for a final result at least two searching routes.Therefore, in the analog-to-digital conversion electricity according to embodiment 1 In road 1, even if when there are false transitions, can also reach the transformation result obtained by the searching route of alternative.
The switch control in the electric capacity DAC paths 10 according to the analog to digital conversion circuit 1 of embodiment 1 is described below.Fig. 7 shows Go out the diagram of the control example for illustrating the redundant digit for controlling analog to digital conversion circuit according to embodiment 1.Fig. 7 is described The comparison of three operates and used the redundancy ratio of redundant digit compared with the control between operation to first switch and second switch.In addition, In the figure 7, " 1 " indicates wherein to select hot side reference voltage V REFP state by first switch and second switch.Enter one Step, " 0 " indicates wherein to select high-low-position side reference voltage VREFN state by first switch and second switch.
As shown in fig. 7, in the 3rd of the comparison operation of wherein execution the 3rd compares so that by the P sides (example of the 3rd Such as, first compares wiring Wp sides) the reference voltages of first switch SW14 selections be switched to from low potential side reference voltage V REFN Hot side reference voltage V REFP.In the 3rd compares, perform compare operation in this state.When comparative result Cout is During low level, wherein perform it is deputy compare the 4th of operation and compare, the reference voltage that is selected by first switch SW14 Low potential side reference voltage V REFN is returned to from hot side reference voltage V REFP.On the other hand, the ratio in comparing when the 3rd When compared with result Cout being high level, wherein perform it is deputy compare the 4th of operation and compare, selected by first switch SW14 The reference voltage selected gives over to hot side reference voltage V REFP.
Next, in the 4th compares so that first on deputy P sides (for example, first compares wiring Wp sides) The reference voltage of switch SW13 selections is switched to hot side reference voltage V REFP from low potential side reference voltage V REFN. During four compare, perform compare operation in this state.When comparative result Cout is low level, redundant digit is performed wherein Compare the 5th of operation to compare, returned by the first switch SW13 reference voltages selected from hot side reference voltage V REFP To low potential side reference voltage V REFN.On the other hand, when the 4th comparative result Cout compared is high level, hold wherein During the 5th of the comparison operation of row redundant digit compares, hot side benchmark electricity is kept by the first switch SW13 reference voltages selected Press VREFP.
Next, in the 5th compares so that first on the P sides (for example, first compares wiring Wp sides) of redundant digit The reference voltage of switch SW12 selections is switched to hot side benchmark electricity in comparing the 5th from low potential side reference voltage V REFN Press VREFP.In addition, wherein perform redundancy ratio compared with the 5th compare, control is by N sides redundant digit (for example, second compares wiring Wn the reference voltage of second switch SW19 selections).Specifically, when the 4th comparative result Cout compared is low level, The reference voltage selected by second switch SW19 is set to be switched to hot side reference voltage from low potential side reference voltage V REFN VREFP.The process equivalent to negative weighting is obtained in equivalent manner, because the DAC on N sides is exported relative to the DAC on P sides Output becomes hot side.On the other hand, when the 4th comparative result Cout compared is high level, make by second switch SW19 The reference voltage of selection keeps low potential side reference voltage V REFN.
Therefore, in the analog to digital conversion circuit 1 according to embodiment 1, the sampling on being arranged therein performing input signal P sides (first compare wiring Wp sides) on switch, it is allowed to the first switch corresponding to position to be compared selects high potential side base Quasi- voltage VREFP.Then, according to transformation result, switch over, wherein by being opened corresponding to perform the position for comparing operation first The reference voltage for closing selection should be hot side reference voltage V REFP or low potential side reference voltage V REFN.In addition, on Corresponding to the second switch of redundant digit, based on the comparative result obtained in the comparison operation before immediately associative operation, enter Row is the switching for selecting hot side reference voltage V REFP or selection low potential side reference voltage V REFN.In addition, being based on Immediately before associative operation comparison operation obtained in comparative result, it is determined whether provide negative weight.
Next, the specific operation that above-mentioned switch control will be illustrated.Fig. 8 shows that explanation turns according to embodiment 1 to modulus Change the diagram of the switch control of the electric capacity DAC-circuit of circuit 1.In fig. 8 it is shown that first compares wiring Wp voltage waveform (Fig. 8 P sides) and second compare wiring Wn voltage waveform (Fig. 8 N sides).In addition, Fig. 8 shows correctly to perform thereon in figure Voltage waveform during the comparison operation of the 4th, and shown in its figure below when mistake performs the comparison operation of the 4th Voltage waveform.Therefore, in fig. 8, in the operation of the comparison of the 3rd (the 3rd compares) that the voltage on based on P sides is performed, P sides Voltage had differences between the situation of upper figure and the situation of figure below, the voltage on the P sides is based on the comparison of the 4th The result of operation is determined.
As shown in figure 8, in the analog to digital conversion circuit 1 according to embodiment 1, when execution, which is compared, operates without error, By be arranged on N sides second switch SW19 selection reference voltage wherein perform redundancy ratio compared with the 5th compare in do not become Change.Therefore, the voltage on N sides gives over to VCM.On the other hand, when there is error in one that compares operation, perform wherein superfluous It is remaining compare the 5th compare, make by the reference voltage of second switch SW19 selections being arranged on N sides from low potential side benchmark Voltage VREFN is switched to hot side reference voltage V REFP.Therefore, the reference voltage on N sides is sent out according to the weight of redundant digit Changing.That is, in the 5th compares, performed using reference voltage and compare operation, the value of the reference voltage and the 4th The value of reference voltage in comparing is different.In this way, in the analog to digital conversion circuit 1 according to embodiment 1, compare second The erroneous judgement effect of middle appearance is corrected.In addition, before the conversion according to the analog to digital conversion circuit 1 of embodiment 1 in result, it is right The position of the comparative result for the position that Ying Yu is compared before immediately redundant digit to it includes the high level of N sides redundant digit/low Level information (existence information for bearing weighting).Therefore, the error occurred in a high position is corrected.Shown in Fig. 8 In example, by performing redundancy ratio compared with spite of there is error, " 7 " can be obtained as transformation result.
Thus, in order to further elucidate the configuration feature of the analog to digital conversion circuit according to embodiment 1, as comparing Example, will be illustrated to comparing the analog to digital conversion circuit 100 without redundant digit on wiring Wn sides second.Fig. 9 shows basis The block diagram of the analog to digital conversion circuit 100 of comparative example.
As shown in figure 9, substitution is posted according to the electric capacity DAC-circuit 10 of the analog to digital conversion circuit 1 of embodiment 1 and gradually comparing Storage logic 12, includes electric capacity DAC-circuit 110 according to the analog to digital conversion circuit 100 of comparative example and gradually comparand register is patrolled Collect 112.In gradually comparand register logic 112, replace gradually the redundant digit control circuit 22 of comparand register logic 12, if Put adder 122.Adder 122 calculated with reduce when performed using redundant digit redundancy ratio compared with when the conversion that has determined As a result the digit in.
Figure 10 shows the circuit diagram of the electric capacity DAC-circuit 110 according to comparative example.As shown in Figure 10, according to the electricity of comparative example It is that the one of capacitor 39 and second switch SW19 is deleted from the electric capacity DAC-circuit 10 according to embodiment 1 to hold DAC-circuit 110 Individual example.In Fig. 10, capacitor 39 is deleted from redundant digit circuit 40 and second switch SW19 circuit is illustrated as redundancy Position circuit 140.
Next, will illustrate to be controlled according to the switch in the electric capacity DAC paths 110 of the analog to digital conversion circuit 100 of comparative example. Figure 11 illustrates the example of the control of the redundant digit to analog to digital conversion circuit 100 according to comparative example.Figure 11 is shown from the 3rd Comparison operation arrive the redundancy ratio using redundant digit compared with control of the operation to first switch and second switch.In addition, in fig. 11, " 1 " represents first switch selection hot side reference voltage V REFP state, and " 0 " represents first switch selection low potential Side reference voltage VREFN state.
As shown in figure 11, wherein performing the 3rd of the 3rd bit comparison operation for comparing and wherein performing deputy comparison The operation of first switch with being arranged on the P sides according to the analog to digital conversion circuit 1 of embodiment 1 described in Fig. 7 is identical.Cause This, by the description thereof will be omitted.On the other hand, wherein perform redundancy ratio using redundant digit compared with the 5th operation compared in embodiment In 1 analog to digital conversion circuit 1 with it is different in the analog to digital conversion circuit 100 of comparative example.Therefore, its operation is described below.
In the 5th according to comparative example compares, regardless of the 4th transformation result compared, make by corresponding to redundant digit First switch SW12 selection reference voltage be switched to hot side reference voltage from low potential side reference voltage V REFN VREFP.In addition, in the 5th according to comparative example compares, in response to the value of the 4th comparative result compared, change has determined For the value of transformation result.Specifically, when the 4th comparative result compared is low level, change is from the 4th to deputy Value.Specifically, the 4th value between second is made to become by from the value obtained by comparison processing thitherto Subtract the value drawn as " 2 " of the weight of redundant digit.On the other hand, when the 4th comparative result compared is high level, 4th value between second does not change.
Therefore, in the analog to digital conversion circuit 100 according to comparative example, in order to be obtained using the redundancy ratio of redundant digit compared with period Obtain weight, it is necessary to the value for the transformation result that change has determined.Further, in order to change described value, it is necessary to use addition The grade of device 122 is calculated.
As described above, in the analog to digital conversion circuit 1 according to embodiment 1, the second of reference voltage being produced wherein and is compared Connect up and redundant digit capacitor (for example, capacitor 39) is set in Wn, the reference voltage is the comparison operation in electric capacity DAC-circuit 10 In compares cycle in the comparison object of comparison voltage that changes.Then, based on immediately redundancy ratio compared with the ratio before operation The relatively comparative result of operation, reference voltage of the switching applied to the other end of redundant digit capacitor.In having according to embodiment 1 In the analog to digital conversion circuit 1 of such circuit configuration and handover operation, by true when not changing until redundancy ratio relatively operation Such circuit configuration and switch control are performed in the case of fixed transformation result, the conversion knot with negative weight is resulted in Really.Further, in order to perform the operation, if (all redundant digits as shown in Figure 4 control circuit using simple combinational circuit 22) this purpose can, be reached.Therefore, in the analog to digital conversion circuit 1 according to embodiment 1, because redundancy ratio is compared with opening in operation Time delay needed for closing control can be minimized, and then can be shortened the time needed for control and be realized at the conversion of high speed Reason.
In addition, in the analog to digital conversion circuit 1 according to embodiment 1, redundancy ratio is compared with prolonging needed for the switch control in operation The slow time can be fairly small.Therefore, even if allowing redundancy ratio identical with the period of other routine operations compared with the period of operation, But it can be enough to ensure that the output for electric capacity DAC-circuit 10 carries out the convergent time.Therefore, it is possible to make analog to digital conversion circuit Stable operation.
Conversion ratio when the redundancy ratio using redundant digit is compared with operation declines the problem of causing very big, and using single-ended Signal is as in input signal VIN single-ended analog to digital conversion circuit, improving efficiency pole of the redundancy ratio compared with the conversion ratio of operation It is high.
In addition, in order to also improve conversion accuracy in single-ended analog to digital conversion circuit, it is generally desirable to so that compare cloth first The total capacitance value of line Wp sides is equal in the second total capacitance value for comparing wiring Wn sides with capacitor.Thus, in basis In the analog to digital conversion circuit 1 of embodiment 1, compare the capacitor 39 that wiring Wn side structures are used as redundant digit capacitor second.So And, capacitor 39 and the total capacitance value as the capacitor 37 and 38 for adjusting capacitor and the capacitor as the first capacitor 30 to 36 total capacitance value is identical.That is, in the analog to digital conversion circuit 1 according to embodiment 1, comparing cloth even in second Redundant digit capacitor is set on line Wn sides, but the total capacitance value of capacitor is identical with the situation for not constructing redundant digit capacitor, and And without the size of increase semiconductor chip.
In addition, for example, when performed as the analog to digital conversion circuit 100 according to comparative example redundancy ratio compared with when, for pair In the case that the switch of position higher than redundant digit Ying Yu is switched over, there is current value because to corresponding to higher than redundant digit Position capacitor charging and discharging and occur the transient current of cataclysm.When there is such transient current, reference voltage because Wiring in semiconductor device, for making semiconductor chip first with encapsulating inductance parasitic in electric wire, packaging pin for couple etc. Element and change, cause the problem of conversion accuracy is reduced.However, in the analog to digital conversion circuit 1 according to embodiment 1, when holding When row redundancy ratio is relatively operated, the only one of which switch related to redundant digit changes the mesh of coupling when performing redundancy ratio compared with operation Mark.Therefore, rooty, according to the analog to digital conversion circuit 100 of comparative example, will not sent out in the analog to digital conversion circuit 1 according to embodiment 1 Raw transient current.Therefore, it is possible to control the change of reference voltage and improve conversion accuracy.
Here, in figure 3 in shown electric capacity DAC-circuit 10, second switch SW17 and SW18 are arranged for construction and existed Second compares the adjustment capacitor (for example, capacitor 37 and 37) in wiring Wn sides.However, giving the adjustment electric capacity of reference voltage Device sampling action and compare operation in any one in be all fixed.Therefore, this adjustment capacitor can be used in Other encapsulation process.As an example, the first modification of explanation and the second modification.
Figure 12 illustrates wiring diagram of the explanation according to the first modification of the electric capacity DAC-circuit of embodiment 1.Become according to first The electric capacity DAC-circuit 10a of type has between wiring Wn is compared in the wiring for being given low potential side reference voltage V REFN with second Capacitor 50.The capacitor 50 has the capacitance amounted to the capacitance of capacitor 37 and 38.Because being coupled to also such as The capacitance that the second of this circuit configuration compares wiring Wn is not different with electric capacity DAC-circuit 10, therefore it can realize and use The identical analog to digital conversion circuit of analog to digital conversion circuit 1 according to embodiment 1 of electric capacity DAC-circuit 10.
Figure 13 illustrates circuit diagram of the explanation according to the second modification of the electric capacity DAC-circuit of embodiment 1.Become according to second Capacitor 37 is coupled to and is given low potential side reference voltage by the electric capacity DAC-circuit 10b of type in the case of without switch VREFN wiring, and by capacitor 38 in the case of without switch coupled to being given hot side reference voltage VREFP wiring.Because the second capacitance for comparing wiring Wn coupled to yet such circuit configuration does not have with electric capacity DAC-circuit 10 Have any different, therefore it can be realized and the identical modulus of analog to digital conversion circuit 1 according to embodiment 1 using electric capacity DAC-circuit 10 Change-over circuit.
In addition, described above has respectively described capacitor 30 to 39 as a capacitor.However, capacitor can be with It is to arrange cell capaciator for example with same shape and identical capacitance values thereon and according to configuration to each serving as The type that the quantity of the cell capaciator of one capacitor is adjusted.Via the quantity of the unit capacitor by adjusting combination Constitute capacitor 30 to 39, it is possible to increase the comparison precision between capacitor.
Switch SW10 to SW19 and switch SW1 to SW2 are made up of transistor.In the two or more crystal being separately laid out In the case that pipe is in parallel, the transistor for switch can form a transistor.
Embodiment 2
In example 2, the another type of electric capacity DAC as the electric capacity DAC-circuit 10 according to embodiment 1 will be illustrated Circuit 60.Figure 14 shows the circuit diagram of the electric capacity DAC-circuit 60 according to embodiment 2.In addition, in the description of embodiment 2, it is identical Reference represent identical or equivalent element, and be not repeated here.
As shown in figure 14, the redundant digit circuit 40 of the electric capacity DAC-circuit 10 according to embodiment 1 is replaced, according to embodiment 2 Electric capacity DAC-circuit 60 includes redundant digit circuit 61.Redundant digit circuit 61 includes：Capacitor 62 to 65；First switch SW62 is extremely SW63；And second switch SW64 to SW65.
Capacitor 62 is the redundant digit with the 2C capacitance corresponding with the weight of the redundant digit corresponding to transformation result Capacitor.In addition, capacitor 62 has the capacitance identical electric capacity with the deputy capacitor 33 corresponding to transformation result Value.In the other end of capacitor 62, first switch SW62 is set.First switch SW62 selection input signals VIN, high potential side base One in quasi- voltage VREFP and low potential side reference voltage V REFN, and it is given to the other end of capacitor 62.
Capacitor 63 is the redundant digit with the 4C capacitance corresponding with the weight of the redundant digit corresponding to transformation result Capacitor.In addition, capacitor 63 has the capacitance identical electric capacity with the capacitor 34 of the 3rd corresponding to transformation result Value.In the other end preparation first switch SW63 of capacitor 63.First switch SW63 selection input signals VIN, high potential side base One in quasi- voltage VREFP and low potential side reference voltage V REFN, and it is given to the other end of capacitor 63.
Capacitor 64 is the redundant digit with the 2C capacitance corresponding with the weight of the redundant digit corresponding to transformation result Capacitor.In addition, capacitor 64 has the capacitance identical electric capacity with the deputy capacitor 33 corresponding to transformation result Value.In the other end of capacitor 64, second switch SW64 is set.Second switch SW64 selection common electric voltages VCM, high potential side base One in quasi- voltage VREFP and low potential side reference voltage V REFN, and it is given to the other end of capacitor 64.
Capacitor 65 is the redundant digit with the 4C capacitance corresponding with the weight of the redundant digit corresponding to transformation result Capacitor.In addition, capacitor 65 has the capacitance identical electric capacity with the capacitor 34 of the 3rd corresponding to transformation result Value.In the other end of capacitor 65, second switch SW65 is set.Second switch SW65 selection common electric voltages VCM, high potential side base One in quasi- voltage VREFP and low potential side reference voltage V REFN, and it is given to the other end of capacitor 65.
That is, being had according to the analog to digital conversion circuit of embodiment 2 in its transformation result between LSB and second The redundant digit of 2.Further, two redundant digits are had according to the analog to digital conversion circuit of embodiment 2.Therefore, mould is described below Operation of the number change-over circuit when it has two redundant digits.
Figure 15 shows to illustrate the diagram in the binary search path in the analog to digital conversion circuit according to embodiment 2.Such as Figure 15 institutes Show have according to the analog to digital conversion circuit of embodiment 2 and its weight is set to 4C redundant digit and its weight is set to 2C Redundant digit.Therefore, it can be formed in the analog to digital conversion circuit according to embodiment 2 than the analog-to-digital conversion electricity according to embodiment 1 The more complicated binary search path in the binary search path on road 1.
The switch control in the electric capacity DAC paths 60 according to the analog to digital conversion circuit of embodiment 2 is described below.Figure 16 shows Go out diagram of the description according to the control example for controlling the redundant digit in analog to digital conversion circuit of embodiment 2.Figure 16 is shown from the 3rd The control using the redundancy ratio of redundant digit compared with operation to first switch and second switch is arrived in the comparison operation of position.In addition, in Figure 16 In, " 1 " shows the state by first switch and second switch selection hot side reference voltage V REFP, and " 0 " is shown by the Two switches and second switch select low potential side reference voltage V REFN state.
As shown in figure 16, compare wherein performing the 3rd of the comparison operation of the 3rd and perform the of deputy operation Four operations compared and the first switch on the P sides being arranged in the analog to digital conversion circuit 1 according to embodiment 1 described in Fig. 7 Operation it is identical.Therefore, the description thereof will be omitted herein.On the other hand, wherein perform using redundant digit redundancy ratio compared with the 5th ratio Compared with and the 6th operation compared in the analog to digital conversion circuit 1 according to embodiment 1 with the analog to digital conversion circuit according to embodiment 2 In it is different.Therefore, its explanation is presented below.
In the 5th compares so that by being arranged at P sides (for example, the first ratio corresponding to the capacitor 63 with 4C weights Relatively wiring Wp sides) on the reference voltages of first switch SW63 selections be switched to high potential from low potential side reference voltage V REFN Side reference voltage VREFP.In addition, wherein perform redundancy ratio compared with the 5th compare, control by the N sides of redundant digit circuit 61 The reference voltage of second switch SW64 and SW65 selection on (for example, second compares wiring Wn).Specifically, compare when the 4th When comparative result Cout is low level, make the reference voltage selected by second switch SW64 and SW65 from low potential side reference voltage VREFN is switched to hot side reference voltage V REFP.On the other hand, when the 4th comparative result Cout compared is high level, Make to give over to low potential side reference voltage V REFN by the reference voltage that second switch SW64 and SW65 are selected.
Next, in the 6th compares, based on the 5th comparative result compared, it is determined that (first compares cloth by being arranged in P sides Line Wp sides) on first switch SW62 selection reference voltage.Specifically, when the 5th transformation result compared is low level, The reference voltage selected by first switch SW62 is set to return to low potential side reference voltage from hot side reference voltage V REFP VREFN.On the other hand, when the 5th transformation result compared is high level, the reference voltage selected by first switch SW62 is made Give over to hot side reference voltage V REFP.
In addition, in the 6th compares so that by the P sides that are set corresponding to the capacitor 63 with 2C weights (for example, first Compare wiring Wp sides) on the reference voltages of first switch SW62 selections be switched to high electricity from low potential side reference voltage V REFN Position side reference voltage VREFP.In addition, wherein perform redundancy ratio compared with the 6th compare, make by the N sides of redundant digit circuit 61 The reference voltage of second switch SW64 and SW65 selection on (for example, second compares wiring Wn) gives over to low potential side reference voltage VREFN, it is equal to the 5th reference voltage compared.
Therefore, in the analog to digital conversion circuit according to embodiment 2, the sampling of input signal is performed on being disposed therein Switch on P sides (first compares wiring Wp sides), it is allowed to which the first switch corresponding to position to be compared selects hot side benchmark Voltage VREFP.Then, according to transformation result, carry out on by being selected corresponding to the first switch that the position for comparing operation is performed to it The reference voltage selected should be hot side reference voltage V REFP or low potential side reference voltage V REFN switching.In addition, closing In the second switch corresponding to redundant digit, routinely compared based on the conventional more central last time performed than before in redundancy ratio Comparative result compared with obtained in, is changed to it, is being chosen hot side reference voltage V REFP or is being chosen low potential side It is switched between reference voltage V REFN.
As described above, by the way that in the analog to digital conversion circuit according to embodiment 2, with the redundant digit of 2, ratio can be formed More it is used for the searching route for reaching a final result according to the analog to digital conversion circuit of embodiment 1.Thus, according to embodiment 2 analog to digital conversion circuit has the correction efficiency higher than analog to digital conversion circuit according to embodiment 1.
In addition, in the analog to digital conversion circuit according to embodiment 2, comparing behaviour based on the routine performed than before in redundancy ratio The comparative result of work performs the control to redundant digit, and in the absence of the situation for the value for changing the position higher than redundant digit.Cause This, as the analog to digital conversion circuit 1 according to embodiment 1, can also realize conversion in the analog to digital conversion circuit according to embodiment 2 The acceleration of rate and the stability of reference voltage.
Embodiment 3
In embodiment 3, it will illustrate to be used as the electric capacity DAC of the another type of the electric capacity DAC-circuit 10 according to embodiment 1 Circuit 70.Figure 17 illustrates the circuit diagram of the electric capacity DAC-circuit 70 according to embodiment 3.In addition, in the explanation of embodiment 3, Constitution element same as Example 1 has reference marker same as Example 1, and the description thereof will be omitted.
As shown in figure 17, in the electric capacity DAC-circuit 70 according to embodiment 3, delete and be arranged according to embodiment 1 The first of electric capacity DAC-circuit 10 compares the corresponding capacitor 32 of redundant digit and first switch SW12 on wiring Wp sides.In addition, taking In generation, according to the redundant digit circuit 40 of the electric capacity DAC-circuit 10 of embodiment 1, includes redundancy according to the electric capacity DAC-circuit 70 of embodiment 3 Position circuit 71.Redundant digit circuit 71 has capacitor 72 and 73 and second switch SW72 and SW73.In addition, according to embodiment In 3 electric capacity DAC-circuit 70, first compares the total capacitance of the capacitor constituted on wiring Wp sides than the electric capacity according to embodiment 1 The small 2C of DAC10.In addition, in the electric capacity DAC-circuit 70 according to embodiment 3, second compares the capacitor constituted on wiring Wn sides Total capacitance than the small 2C of electric capacity DAC10 according to embodiment 1.Therefore, the capacitance sum of capacitor 37 and 38 becomes than basis The electric capacity DAC10 of embodiment 1 is smaller.
Capacitor 72 is the redundancy of the capacitance with the 2C corresponding with the weight of the redundant digit corresponding to transformation result Position capacitor.In addition, capacitor 72 has the capacitance identical electricity with the deputy capacitor 33 corresponding to transformation result Capacitance.In the other end of capacitor 72, second switch SW72 is set.Second switch SW72 is selected and is provided common electric voltage VCM, height Current potential side reference voltage VREFP or low potential side reference voltage V REFN, and it is given to the other end of capacitor 72.
Capacitor 73 is the redundant digit with the 4C capacitance corresponding with the weight of the redundant digit corresponding to transformation result Capacitor.In addition, capacitor 73 has the capacitance identical electric capacity with the capacitor 34 of the 3rd corresponding to transformation result Value.In the other end of capacitor 73, second switch SW73 is set.Second switch SW73 selection common electric voltages VCM, high potential side base One in quasi- voltage VREFP and low potential side reference voltage V REFN, and it is given to the other end of capacitor 73.
That is, according to the analog to digital conversion circuit of embodiment 3 in transformation result have between LSB and second 2 The redundant digit of position.In addition, having the redundant digit capacitor of weighted according to the analog to digital conversion circuit of embodiment 3.However, in root In analog to digital conversion circuit according to embodiment 3, by using the redundant digit of two redundant digit capacitor formation 1.Therefore, below will Illustrate the operation of the analog to digital conversion circuit according to embodiment 3.
Now, it will illustrate to be controlled according to the switch in the electric capacity DAC paths 70 of the analog to digital conversion circuit of embodiment 3.With regard to this For, Figure 18 illustrates the example of the control of the redundant digit to analog to digital conversion circuit according to embodiment 3.Figure 18 is shown from the 3rd Comparison operation in position arrives the redundancy ratio using redundant digit compared with the first switch of operation and the control of second switch.In addition, in figure In 18, " 1 " indicates to select hot side reference voltage V REFP state by first switch and second switch, and " 0 " indicate by The state of first switch and second switch selection low potential side reference voltage V REFN.
As shown in figure 18, in the analog to digital conversion circuit according to embodiment 3, start to compare operation, by be coupled extremely to be existed Start have the second of the capacitor 72 of associated weight during conversion operation among the capacitor 72 and 73 as redundant digit capacitor Switch SW72 selection hot side reference voltage Vs REFP.
Then, the 3rd in the comparison operation for wherein performing the 3rd compares, and makes the P sides by the 3rd (for example, first Compare wiring Wp sides) on the reference voltages of first switch SW14 selections be switched to high electricity from low potential side reference voltage V REFN Position side reference voltage VREFP.In the 3rd compares, perform compare operation in this state.When comparative result Cout is low electricity Usually, wherein perform it is deputy compare the 4th of operation compare in the reference voltage that is selected by first switch SW14 from high electricity Position side reference voltage VREFP returns to low potential side reference voltage V REFN.On the other hand, when the 3rd comparative result compared When Cout is high level, wherein perform it is deputy compare the 4th of operation compare in the benchmark that is selected by first switch SW14 Voltage gives over to hot side reference voltage V REFP.
Next, in the 4th compares, making first on deputy P sides (for example, first compares wiring Wp sides) to open The reference voltage for closing SW13 selections is switched to hot side reference voltage V REFP from low potential side reference voltage V REFN.The 4th In comparing, perform compare operation in this state.Then, when the 4th comparative result Cout compared is low level, make Wherein perform the 5th of the comparison operation of redundant digit compare in the reference voltage that is selected by second switch SW73 from low potential side base Quasi- voltage VREFN is switched to hot side reference voltage V REFP.On the other hand, when the 4th comparative result Cout compared is height During level, make to be stayed by the second switch SW73 reference voltages selected in the 5th of the comparison operation of wherein execution redundant digit comparing Make low potential side reference voltage V REFN.In addition, in the 5th compares, it is low electricity that the 4th comparative result Cout compared is not considered Flat or high level, makes the reference voltage selected by second switch SW72 be switched to low electricity from hot side reference voltage V REFP Position side reference voltage VREFN.
Therefore, in the analog to digital conversion circuit according to embodiment 3, based on the comparison knot obtained in most preceding comparison operation Really, also make to switch to selection hot side reference voltage V REFP or selection ground potential side corresponding to the second switch of redundant digit Reference voltage V REFN.
As described above, in the analog to digital conversion circuit according to embodiment 3, passing through the redundant digit capacitor including weighted And the reference voltage of redundant digit capacitor is given to by switching based on previous comparative result, it is able to carry out and according to implementation The redundancy ratio of the analog to digital conversion circuit of example 1 relatively operates identical redundancy ratio relatively to operate.That is, in the mould according to embodiment 3 In number change-over circuit, compare the comparative result of operation to perform to redundant digit also based on the routine performed than before in redundancy ratio Control, and the value of the position higher than redundant digit will not be changed.Therefore, in the analog to digital conversion circuit according to embodiment 3, as According to the analog to digital conversion circuit 1 of embodiment 1, faster conversion speed and the stability of reference voltage can be also realized.
In addition, in the analog to digital conversion circuit according to embodiment 3, the capacitance for the capacitor of electric capacity DAC-circuit 70 Sum is less than the capacitance of the electric capacity DAC-circuit 10 of the analog to digital conversion circuit 1 according to embodiment 1.Specifically, therefore, in root In analog to digital conversion circuit according to embodiment 3, the capacitance sum for the capacitor of the electric capacity DAC-circuit 70 according to embodiment 3 Than the small 4C of capacitance of the capacitor for electric capacity DAC-circuit 10.Capacitor is that very large area is occupied in semiconductor chip Element, and by reducing the capacitance sum of capacitor, can significantly reduce the area of semiconductor chip.
Embodiment 4
Embodiment 4 illustrates to be used as the electric capacity DAC-circuit of the still another form of the electric capacity DAC-circuit 10 according to embodiment 1 80.Therefore, figure 19 illustrates the wiring diagram of the electric capacity DAC-circuit 90 according to embodiment 4.In addition, in the explanation of embodiment 4 In, constitution element same as Example 1 has reference marker same as Example 1, and the description thereof will be omitted.
On the electric capacity DAC-circuit illustrated in embodiment 1 to 3, it has been described that bottom plate sampling type analog to digital conversion circuit, Its from determine translation bit weight capacitor 31 to 36 terminal among input have hot side reference voltage V REFP or low Current potential side reference voltage VREFN near-end input input signal.On the other hand, it is according to the analog to digital conversion circuit of embodiment 4 Top plate sampling type analog to digital conversion circuit, it is defeated from the first of the terminal for being coupled to capacitor 31 to 36 the near-end for comparing wiring Wp Enter input signal.In addition, Figure 19 shows redundant digit circuit 81 as the circuit corresponding to redundant digit circuit 40.Redundant digit circuit 81 In switch include first switch SW82 and second switch SW89.
In the electric capacity DAC-circuit 80 according to embodiment 4, as shown in figure 19, the electric capacity DAC electricity according to embodiment 1 is deleted The input wiring Win and common voltage wiring Wcm on road 10, and by first switch SW11 to SW16 and second switch SW17 First switch SW81 to SW86 and second switch SW87 to SW89 are substituted for SW19.In addition, in the electric capacity according to embodiment 4 In DAC-circuit 80, input signal VIN is given to first by sampling switch (for example, switch SW1) and compares wiring Wp.
First switch SW81 to SW86 and second switch SW87 to SW89 selection hot side reference voltage V REFP and Low potential side reference voltage V REFN, and accordingly provided.
Thus, in the analog to digital conversion circuit according to embodiment 4, the switch of electric capacity DAC-circuit 80 is controlled with working as Switch control during sampled input signal VIN from the first analog to digital conversion circuit for comparing wiring Wp sides output input signal VIN has Institute is different.However, when comparing processing to the input signal VIN of sampling application, opened for the analog to digital conversion circuit of embodiment 4 Control method is closed, can be using the control method identical method with embodiment 1.
As described above, in the analog to digital conversion circuit according to embodiment 4, in the analog to digital conversion circuit of top plate sample types In, the configuration of the capacitor for the determination weight that electric capacity DAC-circuit 80 includes and the switch to capacitor application reference voltage Also it is identical with those of electric capacity DAC-circuit 10.Therefore, in the analog to digital conversion circuit according to embodiment 4, as according to implementation In the analog to digital conversion circuit 1 of example 1, the conversion of more high speed and the stability of reference voltage can be also realized.
Although the present invention that the above is made by the present inventor has been described in detail on the basis of embodiment, the present invention It is not limited to above-described embodiment.It is self-evident, without departing from the scope of the subject in the invention, various changes can be made to it.

Claims (10)

1. a kind of semiconductor device, including：
Comparator, the comparator is cut based on the relative size relation between the voltage level to be input to two input terminals Change the logic level of output signal；
First compares wiring, and described first compares wiring couples with a terminal of the comparator；
Second compares wiring, and described second compares wiring couples with another terminal of the comparator；
Input wiring, input signal is sent to the input wiring；
Wired coupling is compared in each one end in multiple first capacitors, the multiple first capacitor with described first, The multiple first capacitor is each in sampled input signal, and the multiple first capacitor when starting conversion process It is respectively provided with the capacitance corresponding with the weight of position to be converted；And
Wired coupling is compared in each one end in multiple second capacitors, the multiple second capacitor with described second, And the capacitance sum of the multiple second capacitor is equal with the capacitance sum of first capacitor,
Wherein, second capacitor includes：
Redundant digit capacitor, the redundant digit capacitor has the capacitance corresponding with the weight of redundant digit, and
Capacitor is adjusted, the adjustment capacitor has described superfluous by being subtracted from the capacitance sum of first capacitor Capacitance obtained by the capacitance of remaining position capacitor.
2. semiconductor device according to claim 1,
Wherein, first capacitor includes the capacitor with the capacitance corresponding with the weight of the redundant digit.
3. semiconductor device according to claim 1,
Wherein, the redundant digit capacitor includes the capacitor with the capacitance corresponding from different weights.
4. semiconductor device according to claim 1, including：
Being each provided in multiple first switches, the multiple first switch is each in first capacitor, often Individual first switch selects one in the input signal, hot side reference voltage and low potential side reference voltage, and It is given to corresponding first capacitor；And
Second switch, the second switch is provided to the redundant digit capacitor, the second switch selection common electric voltage, institute One in hot side reference voltage and the low potential side reference voltage is stated, and is given to the redundant digit electricity The other end of container,
Wherein, by common electric voltage supply switching switch, common electric voltage is given to described first and compares wiring and described second Compare wiring.
5. semiconductor device according to claim 1, including：
Being each provided in multiple first switches, the multiple first switch is each in first capacitor, often Individual first switch selects one in the input signal, hot side reference voltage and low potential side reference voltage, and It is given to corresponding first capacitor；And
At the other end of the redundant digit capacitor, second switch, the second switch selection common electric voltage, the height are set One in current potential side reference voltage and the low potential side reference voltage, and it is given to the redundant digit capacitor The other end,
Wherein, by sampling switch, the input signal is given to described first and compares wiring, and
Wherein, by common electric voltage supply switching switch, common electric voltage is given to described second and compares wiring.
6. semiconductor device according to claim 1,
Wherein, the adjustment capacitor includes：
First adjustment capacitor, it is described first adjustment capacitor have by by the capacitance of second capacitor and divided by The capacitance of two gained；And
Second adjustment capacitor, the second adjustment capacitor has to be subtracted by the capacitance from second capacitor with The capacitance and the capacitance obtained by the capacitance sum of the redundant digit capacitor of the first adjustment capacitor are gone,
Wherein, respectively to the described first adjustment capacitor the other end and the other end of the second adjustment capacitor provides second Each selection common electric voltage, hot side reference voltage and low potential side reference voltage in switch, the second switch In one, and provided.
7. semiconductor device according to claim 1,
Wherein, second switch, the second switch selection common electric voltage, high potential are provided to the other end of the adjustment capacitor One in side reference voltage and low potential side reference voltage, and provided.
8. semiconductor device according to claim 1,
Wherein, the other end of the adjustment capacitor is coupled to fixed voltage wiring, and the fixed voltage wiring is fixed to Predetermined voltage.
9. a kind of semiconductor device, including：
Comparator, the comparator is cut based on the relative size relation between the voltage level to be input to two input terminals Change the logic level of output signal；
First compares wiring, and described first compares wiring couples with a terminal of the comparator, and public by first Common electric voltage is given to described first and compares wiring by voltage switch；
Second compares wiring, and described second compares wiring couples with another terminal of the comparator, and public by second Common-battery, which compresses switch, to be given to described second by the common electric voltage and compares wiring；
Input wiring, input signal is sent to the input wiring；
Wired coupling is compared in each one end in multiple first capacitors, the multiple first capacitor with described first, And each it is respectively provided with the capacitance corresponding with the weight of position to be converted in the multiple first capacitor；
Multiple first switches, the multiple first switch is supplied to first capacitor, and each first switch One in the input signal, hot side reference voltage and low potential side reference voltage is selected, and is given to The other end of corresponding first capacitor；And
Wired coupling is compared in each one end in multiple second capacitors, the multiple second capacitor with described second, And the capacitance sum of the multiple second capacitor is equal with the capacitance sum of first capacitor,
Wherein, second capacitor includes：
Redundant digit capacitor, the redundant digit capacitor has the capacitance corresponding with the weight of redundant digit；And
Capacitor is adjusted, the adjustment capacitor has described superfluous by being subtracted from the capacitance sum of second capacitor Capacitance obtained by the capacitance of remaining position capacitor, and
Wherein, second switch is set at the other end of the redundant digit capacitor, and the second switch selects the common electrical One in pressure, the hot side reference voltage and the low potential side reference voltage, and it is given to the redundancy The other end of position capacitor.
10. a kind of semiconductor device, including：
Comparator, the comparator is cut based on the relative size relation between the voltage level to be input to two input terminals Change the logic level of output signal；
First compares wiring, and described first compares wiring couples with a terminal of the comparator, and passes through input switch Input signal is given to described first and compares wiring；
Second compares wiring, and described second compares wiring couples with another terminal of the comparator, and passes through common electrical Compress switch and common electric voltage is given to described second compares wiring；
Wired coupling is compared in each one end in multiple first capacitors, the multiple first capacitor with described first, And each it is respectively provided with the capacitance corresponding with the weight of position to be converted in the multiple first capacitor；
Multiple first switches, the multiple first switch is supplied to first capacitor, and the multiple first One in each selection hot side reference voltage and low potential side reference voltage in switch, and it is given to correspondence The first capacitor the other end；And
Wired coupling is compared in each one end in multiple second capacitors, the multiple second capacitor with described second, And the capacitance sum of the multiple second capacitor is equal with the capacitance sum of first capacitor,
Wherein, second capacitor includes：
Redundant digit capacitor, the redundant digit capacitor has the capacitance corresponding with the weight of redundant digit；And
Capacitor is adjusted, the adjustment capacitor has described superfluous by being subtracted from the capacitance sum of second capacitor Capacitance obtained by the capacitance of remaining position capacitor, and
Wherein, second switch is set at the other end of the redundant digit capacitor, and the second switch selects the high potential One in side reference voltage and the low potential side reference voltage, and it is given to the described another of the redundant digit capacitor One end.
CN201710102441.6A 2016-03-07 2017-02-24 Semiconductor device with a plurality of semiconductor chips Active CN107171668B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-043276 2016-03-07
JP2016043276A JP6650788B2 (en) 2016-03-07 2016-03-07 Semiconductor device

Publications (2)

Publication Number Publication Date
CN107171668A true CN107171668A (en) 2017-09-15
CN107171668B CN107171668B (en) 2022-07-22

Family

ID=58231491

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710102441.6A Active CN107171668B (en) 2016-03-07 2017-02-24 Semiconductor device with a plurality of semiconductor chips

Country Status (4)

Country Link
US (2) US9843340B2 (en)
EP (1) EP3217561B1 (en)
JP (1) JP6650788B2 (en)
CN (1) CN107171668B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI649978B (en) * 2017-10-24 2019-02-01 財團法人工業技術研究院 Continuous approximation register analog to digital converter and its operation method
CN107733436B (en) * 2017-11-07 2018-11-30 深圳锐越微技术有限公司 N mixed structure analog-digital converters and the IC chip comprising it
JP7102515B2 (en) 2018-05-22 2022-07-19 オリンパス株式会社 Digital-to-analog converters, analog-to-digital converters, signal processing devices, solid-state imaging devices, and driving methods
GB2605466A (en) * 2021-06-21 2022-10-05 Nordic Semiconductor Asa Error-feedback SAR-ADC
US20230361780A1 (en) * 2022-05-04 2023-11-09 Nxp B.V. Analog-to-digital converter (adc) having calibration

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101662283A (en) * 2008-12-30 2010-03-03 香港应用科技研究院有限公司 Dual-purpose comparator/operational amplifier used as successive approximation analog-to-digital converter and digital-to-analog converter
US20100090873A1 (en) * 2008-10-10 2010-04-15 Linear Technology Corporation Systems and methods for characterizing component ratios and generating a digital representation of same
US20100123611A1 (en) * 2008-11-19 2010-05-20 Electronics And Telecommunications Research Institute Successive approximation register analog-digital converter and method of driving the same
CN102088290A (en) * 2009-12-04 2011-06-08 雅马哈株式会社 Successive aproximation A/D converter
CN102437850A (en) * 2011-09-28 2012-05-02 香港应用科技研究院有限公司 Charge compensation calibration of high-precision data conversion
US20120133541A1 (en) * 2010-11-30 2012-05-31 International Business Machines Corporation Analog-digital converter
US20130044014A1 (en) * 2011-08-15 2013-02-21 Himax Technologies Limited Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof
JP2013168870A (en) * 2012-02-16 2013-08-29 Fujitsu Semiconductor Ltd A/d conversion apparatus and correction method of a/d conversion apparatus
JP2014011768A (en) * 2012-07-03 2014-01-20 Renesas Electronics Corp A/d converter and semiconductor device
US20140070970A1 (en) * 2011-03-17 2014-03-13 Anacatum Design Ab Adc calibration
TW201427286A (en) * 2012-12-28 2014-07-01 Ind Tech Res Inst Analog to digital converter and capacitors weighting evaluating method of digital to analog converter thereof
CN103929178A (en) * 2014-04-29 2014-07-16 中国电子科技集团公司第二十四研究所 Successive approximation analog-digital converter and conversion method thereof
CN104734716A (en) * 2013-12-24 2015-06-24 瑞昱半导体股份有限公司 Successive-approximation temporary storage type analog-digital converter and control method thereof
CN104734718A (en) * 2015-02-03 2015-06-24 国网重庆市电力公司电力科学研究院 Hybrid DAC capacitor array structure
US20150263756A1 (en) * 2014-03-14 2015-09-17 Mediatek Inc. Calibration and noise reduction of analog to digital converters

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101309837B1 (en) * 2010-03-16 2013-09-23 한국전자통신연구원 Successive approximation register analog-digital converter and method for operating the same
WO2011149428A1 (en) * 2010-05-26 2011-12-01 Agency For Science, Technology And Research An analogue to digital converter, an integrated circuit and a medical device
CN102545900B (en) * 2010-12-20 2015-05-20 意法半导体研发（上海）有限公司 Analog/digital (A/D) conversion system and method
US8581770B2 (en) * 2011-05-04 2013-11-12 Texas Instruments Incorporated Zero-power sampling SAR ADC circuit and method
US8344930B2 (en) * 2011-05-04 2013-01-01 Himax Technologies Limited Successive approximation register analog-to-digital converter
US8638248B2 (en) * 2011-10-07 2014-01-28 Nxp, B.V. Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter
EP2882105B1 (en) * 2013-12-09 2016-09-07 Dialog Semiconductor B.V. Analog to digital converter circuit
US9197231B1 (en) * 2014-04-30 2015-11-24 Freescale Semiconductor, Inc. Systems and methods for data conversion
US9496888B1 (en) * 2014-12-12 2016-11-15 Infineon Technologies Ag Asynchronous SAR ADC with binary scaled redundancy
EP3059868B1 (en) * 2015-02-19 2020-06-03 Stichting IMEC Nederland Circuit and method for comparator offset error detection and correction in an adc
JP6703814B2 (en) * 2015-08-28 2020-06-03 ルネサスエレクトロニクス株式会社 AD converter and AD converter

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100090873A1 (en) * 2008-10-10 2010-04-15 Linear Technology Corporation Systems and methods for characterizing component ratios and generating a digital representation of same
US20100123611A1 (en) * 2008-11-19 2010-05-20 Electronics And Telecommunications Research Institute Successive approximation register analog-digital converter and method of driving the same
CN101662283A (en) * 2008-12-30 2010-03-03 香港应用科技研究院有限公司 Dual-purpose comparator/operational amplifier used as successive approximation analog-to-digital converter and digital-to-analog converter
CN102088290A (en) * 2009-12-04 2011-06-08 雅马哈株式会社 Successive aproximation A/D converter
US20120133541A1 (en) * 2010-11-30 2012-05-31 International Business Machines Corporation Analog-digital converter
US20140070970A1 (en) * 2011-03-17 2014-03-13 Anacatum Design Ab Adc calibration
US20130044014A1 (en) * 2011-08-15 2013-02-21 Himax Technologies Limited Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof
CN102437850A (en) * 2011-09-28 2012-05-02 香港应用科技研究院有限公司 Charge compensation calibration of high-precision data conversion
JP2013168870A (en) * 2012-02-16 2013-08-29 Fujitsu Semiconductor Ltd A/d conversion apparatus and correction method of a/d conversion apparatus
JP2014011768A (en) * 2012-07-03 2014-01-20 Renesas Electronics Corp A/d converter and semiconductor device
TW201427286A (en) * 2012-12-28 2014-07-01 Ind Tech Res Inst Analog to digital converter and capacitors weighting evaluating method of digital to analog converter thereof
CN104734716A (en) * 2013-12-24 2015-06-24 瑞昱半导体股份有限公司 Successive-approximation temporary storage type analog-digital converter and control method thereof
US20150263756A1 (en) * 2014-03-14 2015-09-17 Mediatek Inc. Calibration and noise reduction of analog to digital converters
CN103929178A (en) * 2014-04-29 2014-07-16 中国电子科技集团公司第二十四研究所 Successive approximation analog-digital converter and conversion method thereof
CN104734718A (en) * 2015-02-03 2015-06-24 国网重庆市电力公司电力科学研究院 Hybrid DAC capacitor array structure

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHANG A H等: "A 12b50MS/s 2.1 mW SAR ADC with Redundancy and Digital Background Calibration", 《PROCEEDINGS OF THE 39TH EUROPEAN SOLID-STATE CIRCUIT CONFERENCE》 *
万鑫等: "一种非二进制权重的高能效比逐次比较型模数转换器", 《固体电子学研究与进展》 *

Also Published As

Publication number Publication date
CN107171668B (en) 2022-07-22
EP3217561A1 (en) 2017-09-13
EP3217561B1 (en) 2018-10-17
US10075177B2 (en) 2018-09-11
JP2017163193A (en) 2017-09-14
US9843340B2 (en) 2017-12-12
JP6650788B2 (en) 2020-02-19
US20170257112A1 (en) 2017-09-07
US20180054212A1 (en) 2018-02-22

Similar Documents

Publication Publication Date Title
CN107171668A (en) Semiconductor device
CN104917524B (en) Analog-digital converter
CN106301377A (en) Successive approximation is simulated to digital converter
CN104967451B (en) Gradual approaching A/D converter
US8659459B2 (en) Digital-to-analog converter, analog-to-digital converter including same, and semiconductor device
CN206164507U (en) Successive approximation type adc with segmentation capacitor array
CN105811986B (en) A kind of Approach by inchmeal adc circuit of high-speed transitions
JP2009232281A (en) Successive approximation a/d converter
WO2005096503A1 (en) Programmable input range adc
CN104242942B (en) Six asynchronous gradually-appoximant analog-digital converters of tape comparator offset correction
CN110247659A (en) Method using shake and the analog-digital converter according to this method operation
CN105720979A (en) Calibration techniques for SAR ADCS with on-chip reservoir capacitors
CN105933004A (en) Novel high-precision capacitor self-calibration analog-to-digital converter of successive approximation type
CN108233936A (en) Analogue-to-digital converters circuit
CN109217874A (en) Surplus shifts loop, gradual approaching A/D converter and gain calibration methods thereof
CN112803946B (en) Capacitor mismatch and offset voltage correction method applied to high-precision successive approximation ADC (analog to digital converter)
CN101534115A (en) Stepped capacitor array for a full binary weight capacitor
US8947288B2 (en) Analog-digital converter
CN101093997B (en) Combined ad/da converting apparatus
US8576106B2 (en) Analog-digital converter
CN107181490A (en) Analog to digital conversion circuit
CN105375926B (en) The capacitive gradually-appoximant analog-digital converter of pseudo-differential
CN1671054B (en) Device and method for low non linearity A-D converter
CN114204942B (en) Successive approximation type analog-to-digital converter and conversion method
CN107835023A (en) A kind of successive approximation digital analog converter

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant