CN107784136A - The creation method and system of a kind of standard cell lib - Google Patents
The creation method and system of a kind of standard cell lib Download PDFInfo
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- CN107784136A CN107784136A CN201610721546.5A CN201610721546A CN107784136A CN 107784136 A CN107784136 A CN 107784136A CN 201610721546 A CN201610721546 A CN 201610721546A CN 107784136 A CN107784136 A CN 107784136A
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The embodiments of the invention provide a kind of creation method of standard cell lib and system, by the classification for determining basic logic unit, at least one taxon is generated, then determines the driving intensity quantity of each taxon again, finally determines the device size of the basic logic unit.It can be seen that this programme has carried out reasonable disposition to each basic logic unit in standard cell lib, it is ensured that chip sequential and the balance of area are effectively realized during ASIC design, avoids chip area caused by taking multiple units combinations because lacking respective drive from wasting.Except this, define the proportioning of basic logic unit, it is easy to quickly realize element circuit schematic diagram, the effective standard cell lib that shortens designs and develops the time, with good driving uniformity, be advantageous to the Fast Convergent of chip key path time sequence, substantially reduce the futile-iteration number of reparation sequential fault during logic synthesis and placement-and-routing, improve the efficiency of VLSI Design.
Description
Technical field
The present invention relates to IC design technical field, more specifically to a kind of establishment side of standard cell lib
Method and system.
Background technology
Standard cell lib is the set of combinatorial logic unit, sequential logic unit and special element；Comprising unit netlist,
The data such as unit symbol, cell layout, logic function model, comprehensive storehouse model, it is the basic number of VLSI Design
According to storehouse.ASIC design based on standard block can be greatly enhanced design efficiency, accelerate the time that product enters market, to have
The advantages that cost is low, the cycle is short.The performance of standard cell lib decides the characteristics such as area, sequential and the power consumption of chip.With list
The raising of piece integrated circuit integrated level and operating rate, design and develop high integration and the standard cell lib of high speed into
Necessary condition is designed for chip.The driving force of basic logic unit directly affects the sequential of integrated circuit in standard cell lib
Characteristic, including during rising edge, decline delay, rise the transition time, decline the transition time, settling time, hold time, during removal
Between and reset time.
The determinant that standard block driving force influences on circuit sequence characteristic is input stage electric capacity and the outside of unit
The aspect of load capacitance three.Input capacitance primarily inputs a grade transistor gate electric capacity, and it determines unit internal drive ability, simultaneously
And the output loading of upper level unit；Output stage transistor size influences the sequential of unit itself, while determines unit pair
The driving force of external loading.Therefore, in the standard cell lib design phase, the major influence factors of driving force are input stage crystalline substances
Body pipe size and output stage transistor size.
In integrated circuit design, the input capacitance of rear stage unit is the load capacitance of previous stage unit.Therefore, it is a set of
The driving force of basic logic unit influences each other restriction in standard cell lib, all basic logic unit driving forces
Uniformity is most important to the performance of a whole set of cell library.If basic logic unit does not have rational driving energy in standard cell lib
Power number amount and type will cause the waste of chip area；If the unit of different driving ability does not have accurate proportionate relationship to lead
Send a telegraph can not restraining for road key path time sequence, and the entire lowering of chip frequency.
Existing standard cell library is designed and developed, and is usually set by the several engineers of design team according to standard cell lib
Specification Full-custom design is counted to complete.So-called full custom is namely based on transistor level, all circuit theory diagrams, circuit simulation, device
Interconnection line and domain all use engineer.This method is relatively adapted to require that integrated level is high, speed is fast, area is small, low in energy consumption
Universal circuit design.
Inventor is had found, using existing method, the logic function and temporal characteristicses of standard block are determined by emulating, but
It is that the quantity distribution of standard cell lib entirety driving force and device size proportioning can not be drawn by circuit simulation.That is, it is existing
Driving force uniformity is poor in standard cell lib development process.How to improve the uniformity of the driving force of standard cell lib into
For a current big technical problem urgently to be resolved hurrily.
The content of the invention
In view of this, the embodiment of the present invention provides a kind of creation method and system of standard cell lib, improves standard list
The uniformity of the driving force in first storehouse.
To achieve the above object, the embodiment of the present invention provides following technical scheme：
A kind of creation method of standard cell lib, including：
The classification of basic logic unit is determined, generates at least one taxon；
It is determined that the quantity and driving force species of the driving intensity of each taxon；
Determine the device size of the basic logic unit.
Preferably, the classification for determining basic logic unit, generating at least one taxon includes：
According to Boolean logic and the use probability of the basic logic unit, the basic logic unit is divided into base
Plinth unit, simple combinatorial logic unit, complex combination logic unit, timing unit and special element；
The base unit comprises at least：Phase inverter and buffer；
The simple combinatorial logic unit comprises at least:With door, NAND gate, OR gate, nor gate；
The complex combination logic unit comprises at least:With OR gate, AOI or with or whether, XNOR, adder,
Selector；
The timing unit comprises at least：Latch, trigger, Clock gating；
The special element comprises at least：Substrate connection unit, fills unit, antenna element.
Preferably, the quantity of the driving intensity for determining each taxon includes：
According to formula N=k*i*j, the driving intensity quantity of the taxon is calculated；
Wherein, N be taxon driving intensity quantity, k be taxon in basic logic unit number of species, i
To drive the quantity of intensity, j is the quantity of driving force species.
Preferably, the driving force species includes：Rise and fall time balanced type, rise and fall average time are minimum
The complementary type and rise and fall transition time balanced type of type, average time minimum.
Preferably, the device size for determining the basic logic unit includes：
According to the driving intensity and driving force species of the basic logic unit, the basic logic unit is determined
Device size.
Preferably, the driving intensity and driving force species according to the basic logic unit, determines the base
The device size of this logic unit includes：
It is a preset reference value to define P/N ratios, and the P/N ratios are wide for the PMOS of phase inverter and the raceway groove of NMOS tube
Degree ratio；
Determine that the P/N ratios of each basic logic unit of the same driving type are identical；
The device size for determining each basic logic unit of same type different driving intensity is the X of the preset reference value
Times, X is the numerical value of the driving intensity of the basic logic unit.
A kind of establishment system of standard cell lib, including：
First determining module, for determining the classification of basic logic unit, generate at least one taxon；
Second determining module, for determining the driving intensity quantity of each taxon；
3rd determining module, for determining the device size of the basic logic unit.
Preferably, second determining module includes：
Computing unit, for the quantity for calculating the number of species of basic logic unit in the taxon, driving intensity
And the product of the quantity of driving type；
Definition unit, for defining the driving intensity quantity that the product is the taxon.
Preferably, the 3rd determining module includes：
Determining unit, for the driving intensity according to the basic logic unit and driving type, determine described basic
The device size of logic unit.
Preferably, the determining unit includes：
Subelement is defined, is a preset reference value for defining P/N ratios, the P/N ratios are the PMOS of phase inverter
With the channel width ratio of NMOS tube；
First determination subelement, for determining the P/N ratio phases of each basic logic unit in the same taxon
Together；
Second determination subelement, for determining that the device size of each basic logic unit in the same taxon is
X times of the preset reference value, X are the numerical value of the driving intensity of the basic logic unit.
Based on above-mentioned technical proposal, the embodiments of the invention provide a kind of creation method of standard cell lib and system, leads to
The classification for determining basic logic unit is crossed, at least one taxon is generated, then determines the drive of each taxon again
The quantity and driving force species of fatigue resistance, finally determine the device size of the basic logic unit.It can be seen that this programme is to mark
Each basic logic unit has carried out reasonable disposition in quasi- cell library, improves the uniformity of the driving force of standard cell lib.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 a are a kind of flow chart of the creation method of standard cell lib provided in an embodiment of the present invention；
Fig. 1 b are a kind of structural representation of the creating device of standard cell lib provided in an embodiment of the present invention；
Fig. 2 is a kind of classification schematic diagram of standard cell lib provided in an embodiment of the present invention；
Fig. 3 is a kind of schematic diagram of the elementary cell of standard cell lib provided in an embodiment of the present invention；
Fig. 4 is that a kind of flow of determination method of the device size of basic logic unit provided in an embodiment of the present invention is illustrated
Figure；
Fig. 5 is a kind of structural representation of the basic logic unit of standard cell lib provided in an embodiment of the present invention；
Fig. 6 is a kind of structural representation of the basic logic unit of standard cell lib provided in an embodiment of the present invention；
Fig. 7 is the flow chart of the creation method of another standard cell lib provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, all correspond to the scope of protection of the invention.
Fig. 1 a are a kind of schematic flow sheet of the creation method of standard cell lib provided in an embodiment of the present invention, and Fig. 1 b are this
A kind of structural representation of the creating device for standard cell lib that embodiment provides, wherein, creation method includes step：
S100：The classification of basic logic unit is determined, generates at least one taxon.
According to Boolean logic and the use probability of the basic logic unit, the basic logic unit is divided into base
Plinth unit, simple combinatorial logic unit, complex combination logic unit, timing unit and special element；
Referring to Fig. 2, specific dividing mode is as follows：
Base unit：Cellular logic is simple, the probability highest used in the chips, including 2 kinds of phase inverter and buffer
The basic logic unit of type；
Simple combinatorial logic unit：Cellular logic is relatively simple, and the probability used in the chips is higher, including with door,
The units such as NAND gate, OR gate and nor gate, the unit of about 25 kinds of logic functions；
Complex combination logic unit：Cellular logic is complex, and the probability used in the chips is moderate, including with or
Door, AOI or with or whether, the unit such as XNOR, adder, selector, about 40 kinds of basic logic units；
Timing unit：Cellular logic is more complicated, is mainly used in clock network in the chips, the probability and chip used
Purposes is relevant, including the unit such as latch, trigger, Clock gating, about 35 kinds of basic logic units；
Special element：This kind of Elementary Function is relatively special, or is not logic unit, or is served only for physical Design rank
Section.Including the units such as substrate connection unit, fills unit, antenna element and User Defined, about 10 kinds of basic logic units.
S110：It is determined that the driving intensity quantity of each taxon.
Calculate the number of species of basic logic unit in the taxon, drive the quantity and driving force kind of intensity
The product of class, define the driving intensity quantity that the product is the taxon.
Specifically, the quantity of driving intensity refers to 0.5 times, and 0.6 times, 0.7 times, 0.7 times, 0.8 times, 0.9 times, 1 times, 1.2 times,
1.4 times, 1.7 times, 2 times, 2.5 times, 3 times ... the 64 times numbers for waiting driving intensity.The species of driving force includes upper in the present invention
Rise fall time balanced type (B), rise and fall average time smallest (A), the complementary type (M) of average time minimum, under rising
The type of the driving forces such as transition time balanced type (E) drops.Per the driving intensity quantity N of class unit, multiply equal to unit species (k)
To drive the quantity (i) of intensity to be multiplied by the species (j) of driving force, i.e. N=k*i*j.The quantity M of every kind of unit driving force,
Quantity (i) equal to its driving intensity is multiplied by the species (j) of its driving force, i.e. M=i*j.Elementary cell drives intensity quantity
It is as follows with the allocative decision of driving force species：
The quantity of the larger then elementary cell driving intensity of standard cell lib is more, the scale is smaller of standard cell lib
The then negligible amounts of elementary cell driving intensity；The number of the more simple then unit driving intensity of its logical equation of type belonging to unit
Amount is more, and the quantity of the more complicated then unit driving intensity of its logical equation of type belonging to unit is fewer.
The species of the larger then elementary cell driving force of standard cell lib is more, the scale is smaller of standard cell lib
Then the species of elementary cell driving force is more；The kind of the more simple then unit driving force of its logical equation of type belonging to unit
Class is more, and the species of the more complicated then unit driving force of its logical equation of the type belonging to unit is fewer.
Hereafter by taking about 1000 units of standard cell lib scale as an example, the design side of the quantity of unit driving force is illustrated
Case, as shown in Figure 3.Related data does not form the constraint to present claims.
The driving intensity of two kinds of base units of phase inverter and buffer can specifically include but is not limited to：X0P5, X0P6,
X0P7, X0P8, X0P9, X1, X1P2, X1P4, X1P7, X2, X2P5, X3, X4, X5, X6, X7, X9, X11, X13, X16, X24,
X32, X48 and X64；Meanwhile each driving intensity separately designs 3 kinds of driving types：Rise and fall time balanced type (B), rise
Decline average time smallest (A), the complementary type (M) of average time minimum.Two kinds of units of phase inverter and buffer are ensured with this
The quantity of driving force at least more than 60.
It can include but is not limited to simple logic unit, specific driving forces such as door, NAND gate, OR gate and nor gates：
X0P5, X0P7, X1, X1P4, X2, X3, X4, X6 and X8；Each driving intensity separately designs 2~3 kinds of driving types：Rise and fall
Time balanced type (B), rise and fall average time smallest (A), the complementary type (M) of average time minimum.Ensured with this every kind of
The quantity of simple logic unit driving force at least more than 18.
With OR gate, AOI or with or whether can include with complex combination unit, specific driving forces such as XNORs
But it is not limited to：X0P5, X0P7, X1, X1P4, X2, X3, X4, X6 and X8；The driving type selecting rise and fall of each driving intensity
The complementary type (M) of average time smallest (A) or average time minimum.The quantity of every kind of complex combination unit driving force is about
For 9.
The timing units such as latch, trigger, Clock gating, specific driving force can include but is not limited to：X1, X2,
X3 and X4；The driving type of each driving intensity is average time minimum complementary type (M).Every kind of timing unit driving force
Quantity is about 4.
The special elements such as substrate connection unit, fills unit and antenna element do not have logic function not need a variety of driving energies
Power, corresponding cell width is designed according to different physical characteristics.
Above-mentioned base unit, simple combinatorial logic unit, complex combination logic unit, the actual driving force of timing unit
Quantity can be calculated according to the quantity equal proportion of the scale of cell library and type.
S120：Determine the device size of the basic logic unit.
According to the driving intensity of the basic logic unit and type is driven, determines the device of the basic logic unit
Size.Specifically, as shown in figure 4, it is achieved by the steps of：
It is a preset reference value to define P/N ratios, and the P/N ratios are wide for the PMOS of phase inverter and the raceway groove of NMOS tube
Degree ratio；
Determine that the P/N ratios of each basic logic unit of the same driving type are identical；
The device size for determining each basic logic unit of same type different driving intensity is the X of the preset reference value
Times, X is the numerical value of the driving intensity of the basic logic unit.
Such as：
The unit of same type different driving intensity, the P/N ratios of input stage and the P/N ratios of output stage all keep one
The numerical value of relative constancy；As shown in figure 5, the phase inverter INV_X1B of 1 times of driving intensity rise and fall time balanced type P/N ratios
Example is identical with the phase inverter INV_X8B of 8 times of driving intensity rise and fall time balanced types P/N ratios.
The unit of same type different driving intensity, the n times of output stage device size for driving intensity unit are that 1 times of driving is strong
N times of degree.Such as two input nand gate NAND2_X1A sizes of 1 times of driving intensity rise and fall average time smallest determine
Afterwards, 4 times driving intensity rise and fall time balanced type two input nand gate NAND2_X4A units output end device PMOS and
NMOS channel width is 4 times of NAND2_X1A units.
There is phase inverter in input stage in logic unit circuit, and the channel width of its PMOS and NMOS tube is that its is latter
The channel width and the geometric mean of the phase inverter of simulation intensity of level device, to ensure less input capacitance, and
The driving force enough to its rear stage device；There is phase inverter in output stage in logic unit circuit, its PMOS and
The channel width of NMOS tube is identical with the phase inverter of identical driving intensity, to ensure accurately driving intensity.
Input stage and output stage are as shown in Figure 6 for the circuit diagram of phase inverter.Such as 16 times of driving intensity rise and fall
The buffer BUF_X16B units PMOS of time balanced type and the channel width of NMOS tube：Output stage device size and 16 times of drives
The phase inverter INV_X16B units of fatigue resistance rise and fall time balanced type are identical, and input stage device size is its rear stage device
Channel width and simulation intensity phase inverter INV_X0P5B units geometric mean；
The channel width of remaining situation metal-oxide-semiconductor primarily determines that according to the P/N ratios and Logic effort of phase inverter.According to the above
Concrete scheme, the input stage and output stage MOS transistor device size of all basic logic units can be primarily determined that.
It can be seen that this programme has carried out reasonable disposition to each basic logic unit in standard cell lib, standard block is improved
The uniformity of the driving force in storehouse.
As shown in fig. 7, after step S120, step can also be included：
S130：Matched somebody with somebody according to the device size of standard cell lib design specification and step the S120 basic logic unit determined
Than carrying out the design of element circuit schematic diagram.Difference with traditional process is invention unit schematic diagram design process
In, the device size of unit input stage and output stage has initial standard, is easy to be rapidly completed the design of element circuit schematic diagram,
And it ensure that the uniformity of all elementary cell driving forces.
Step can also be included：The preceding emulation of element circuit function and sequential.If post-layout simulation results exhibit be unsatisfactory for function and
Timing requirements, then need return to step S130 modification circuit structures and device size；If post-layout simulation results exhibit meet function and when
Sequence requirement, then into step 207.
S140：Cell layout designs.Engineer carries out layout design according to circuit structure and device size, and completes physics
Checking, including DRC, domain schematic diagram comparison check, and parasitic parameter extraction.
S150：The post-simulation of element circuit function and sequential.If post-layout simulation results exhibit is unsatisfactory for function and timing requirements,
Need the layout and interconnection line of return to step S140 modification cell layouts；If post-layout simulation results exhibit meets function and timing requirements,
Then enter step S160.
S160：Standard cell lib characterizes modeling, forms standard cell lib design kit.The standard completed for above step
Unit carries out the feature extractions such as sequential, area, power consumption and noise, the characterization model of Erecting and improving.
Except this, the present embodiment additionally provides a kind of establishment system of standard cell lib, including：
First determining module, for determining the classification of basic logic unit, generate at least one taxon；
Second determining module, for determining the driving intensity quantity of each taxon；
3rd determining module, for determining the device size of the basic logic unit.
Preferably, second determining module includes：
Computing unit, for the quantity for calculating the number of species of basic logic unit in the taxon, driving intensity
And the product of the quantity of driving type；
Definition unit, for defining the driving intensity quantity that the product is the taxon.
Preferably, the 3rd determining module includes：
Determining unit, for the driving intensity according to the basic logic unit and driving type, determine described basic
The device size of logic unit.
Preferably, the determining unit includes：
Subelement is defined, is a preset reference value for defining P/N ratios, the P/N ratios are the PMOS of phase inverter
With the channel width ratio of NMOS tube；
First determination subelement, for determining the P/N ratio phases of each basic logic unit in the same taxon
Together；
Second determination subelement, for determining that the device size of each basic logic unit in the same taxon is
X times of the preset reference value, X are the numerical value of the driving intensity of the basic logic unit.
The principle of the establishment system of the standard cell lib is identical with embodiment of the method.
To sum up, the embodiments of the invention provide a kind of creation method of standard cell lib and system, by determining to patrol substantially
The classification of unit is collected, at least one taxon is generated, then determines the driving intensity quantity of each taxon again, most
The device size of the basic logic unit is determined afterwards.It can be seen that this programme is carried out to each basic logic unit in standard cell lib
Reasonable disposition, it is ensured that effectively realize chip sequential and the balance of area during ASIC design, avoid corresponding because lacking
Drive and take chip area caused by multiple units combinations to waste.Except this, the proportioning of basic logic unit is defined, is easy to fast
Speed realizes element circuit schematic diagram, and the effective standard cell lib that shortens designs and develops the time, has good driving uniformity, has
Beneficial to the Fast Convergent of chip key path time sequence, substantially reduce and repair what sequential broke rules during logic synthesis and placement-and-routing
Futile-iteration number, improve the efficiency of VLSI Design.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.For device disclosed in embodiment
For, because it is corresponded to the method disclosed in Example, so description is fairly simple, related part is said referring to method part
It is bright.
Professional further appreciates that, with reference to the unit of each example of the embodiments described herein description
And algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software, the composition and step of each example are generally described according to function in the above description.These
Function is performed with hardware or software mode actually, application-specific and design constraint depending on technical scheme.Specialty
Technical staff can realize described function using distinct methods to each specific application, but this realization should not
Think beyond the scope of this invention.
Directly it can be held with reference to the step of method or algorithm that the embodiments described herein describes with hardware, processor
Capable software module, or the two combination are implemented.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (10)
- A kind of 1. creation method of standard cell lib, it is characterised in that including：The classification of basic logic unit is determined, generates at least one taxon；It is determined that the quantity and driving force species of the driving intensity of each taxon；Determine the device size of the basic logic unit.
- 2. the creation method of standard cell lib according to claim 1, it is characterised in that the determination basic logic unit Classification, generating at least one taxon includes：Probability is used according to Boolean logic and the basic logic unit, will be single based on basic logic unit division Member, simple combinatorial logic unit, complex combination logic unit, timing unit and special element；The base unit comprises at least：Phase inverter and buffer；The simple combinatorial logic unit comprises at least:With door, NAND gate, OR gate, nor gate；The complex combination logic unit comprises at least:With OR gate, AOI or with or whether, XNOR, adder, selection Device；The timing unit comprises at least：Latch, trigger, Clock gating；The special element comprises at least：Substrate connection unit, fills unit, antenna element.
- 3. the creation method of standard cell lib according to claim 2, it is characterised in that described to determine each classification The quantity of the driving intensity of unit includes：According to formula N=k*i*j, the driving intensity quantity of the taxon is calculated；Wherein, N is the driving intensity quantity of taxon, and k is the number of species of basic logic unit in taxon, and i is drive The quantity of fatigue resistance, j are the quantity of driving force species.
- 4. the creation method of standard cell lib according to claim 1, it is characterised in that the driving force species bag Include：Rise and fall time balanced type, rise and fall average time smallest, the complementary type of average time minimum and rise and fall Transition time balanced type.
- 5. the creation method of standard cell lib according to claim 4, it is characterised in that described to determine the basic logic The device size of unit includes：According to the driving intensity and driving force species of the basic logic unit, the device of the basic logic unit is determined Size.
- 6. the creation method of standard cell lib according to claim 5, it is characterised in that described according to the basic logic The driving intensity and driving force species of unit, determining the device size of the basic logic unit includes：It is a preset reference value to define P/N ratios, and the P/N ratios are the PMOS of phase inverter and the channel width ratio of NMOS tube Example；Determine that the P/N ratios of each basic logic unit of the same driving type are identical；The device size for determining each basic logic unit of same type different driving intensity is X times of the preset reference value, X For the numerical value of the driving intensity of the basic logic unit.
- A kind of 7. establishment system of standard cell lib, it is characterised in that including：First determining module, for determining the classification of basic logic unit, generate at least one taxon；Second determining module, for determining the driving intensity quantity of each taxon；3rd determining module, for determining the device size of the basic logic unit.
- 8. the establishment system of standard cell lib according to claim 7, it is characterised in that the second determining module bag Include：Computing unit, for calculate the number of species of basic logic unit in the taxon, drive intensity quantity and Drive the product of the quantity of type；Definition unit, for defining the driving intensity quantity that the product is the taxon.
- 9. the establishment system of standard cell lib according to claim 8, it is characterised in that the 3rd determining module bag Include：Determining unit, for the driving intensity according to the basic logic unit and driving type, determine the basic logic The device size of unit.
- 10. the establishment system of standard cell lib according to claim 9, it is characterised in that the determining unit includes：Define subelement, be a preset reference value for defining P/N ratios, the P/N ratios for phase inverter PMOS with The channel width ratio of NMOS tube；First determination subelement, for determining that the P/N ratios of each basic logic unit in the same taxon are identical；Second determination subelement, for determining that the device size of each basic logic unit in the same taxon is described X times of preset reference value, X are the numerical value of the driving intensity of the basic logic unit.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108563899A (en) * | 2018-04-26 | 2018-09-21 | 武汉新芯集成电路制造有限公司 | The analogue system and method for standard block |
| CN109635436A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | A kind of circuit structure |
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| CN111241771A (en) * | 2019-01-29 | 2020-06-05 | 叶惠玲 | Method and system for establishing standard cell library, and chip design method and system |
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| CN114707443A (en) * | 2022-05-23 | 2022-07-05 | 北京芯愿景软件技术股份有限公司 | Method and device for simplifying basic unit library |
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| CN108563899A (en) * | 2018-04-26 | 2018-09-21 | 武汉新芯集成电路制造有限公司 | The analogue system and method for standard block |
| CN108563899B (en) * | 2018-04-26 | 2022-02-22 | 武汉新芯集成电路制造有限公司 | Simulation system and method for standard cell |
| CN110888038A (en) * | 2018-09-11 | 2020-03-17 | 中芯国际集成电路制造(上海)有限公司 | Standard unit test circuit layout, optimization method thereof and standard unit test structure |
| CN110888038B (en) * | 2018-09-11 | 2021-12-14 | 中芯国际集成电路制造(上海)有限公司 | Standard unit test circuit layout, optimization method thereof and standard unit test structure |
| CN109635436A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | A kind of circuit structure |
| CN109635436B (en) * | 2018-12-12 | 2023-08-18 | 上海华力集成电路制造有限公司 | Circuit structure |
| CN111241768A (en) * | 2019-01-29 | 2020-06-05 | 叶惠玲 | Method and system for establishing standard cell library, and chip design method and system |
| CN111241771A (en) * | 2019-01-29 | 2020-06-05 | 叶惠玲 | Method and system for establishing standard cell library, and chip design method and system |
| CN111241771B (en) * | 2019-01-29 | 2023-12-01 | 叶惠玲 | Method and system for establishing standard cell library, chip design method and system |
| CN111241768B (en) * | 2019-01-29 | 2023-06-30 | 叶惠玲 | Method and system for establishing standard cell library, chip design method and system |
| CN109948226A (en) * | 2019-03-13 | 2019-06-28 | 上海安路信息科技有限公司 | The processing method and processing system of activation bit |
| CN109948226B (en) * | 2019-03-13 | 2020-12-25 | 上海安路信息科技有限公司 | Method and system for processing drive information |
| CN112100158B (en) * | 2020-09-21 | 2022-11-22 | 海光信息技术股份有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| CN112100158A (en) * | 2020-09-21 | 2020-12-18 | 海光信息技术有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| TWI788220B (en) * | 2021-02-11 | 2022-12-21 | 台灣積體電路製造股份有限公司 | Adder tree circuit and adder circuit and operating method thereof |
| CN113158618A (en) * | 2021-05-25 | 2021-07-23 | 杨家奇 | Method for generating standard cell library layout |
| CN114707443B (en) * | 2022-05-23 | 2023-01-10 | 北京芯愿景软件技术股份有限公司 | Method and device for simplifying basic unit library |
| CN114707443A (en) * | 2022-05-23 | 2022-07-05 | 北京芯愿景软件技术股份有限公司 | Method and device for simplifying basic unit library |
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