CN102279899A - Method for optimizing simplified standard unit library - Google Patents
Method for optimizing simplified standard unit library Download PDFInfo
- Publication number
- CN102279899A CN102279899A CN2011100827364A CN201110082736A CN102279899A CN 102279899 A CN102279899 A CN 102279899A CN 2011100827364 A CN2011100827364 A CN 2011100827364A CN 201110082736 A CN201110082736 A CN 201110082736A CN 102279899 A CN102279899 A CN 102279899A
- Authority
- CN
- China
- Prior art keywords
- unit
- standard cell
- simplifying
- input
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000000694 effects Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000013461 design Methods 0.000 claims description 21
- 239000000945 filler Substances 0.000 claims description 14
- 230000015556 catabolic process Effects 0.000 claims description 13
- 208000019901 Anxiety disease Diseases 0.000 claims description 4
- 230000036506 anxiety Effects 0.000 claims description 4
- 238000000354 decomposition reaction Methods 0.000 abstract description 5
- 230000001010 compromised effect Effects 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- 230000008569 process Effects 0.000 description 8
- 238000005457 optimization Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000003786 synthesis reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 238000012938 design process Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a method for optimizing a simplified standard unit library. The method comprises the following steps of: selecting a basic unit for realizing a needed circuit function, wherein the basic unit at least comprises a phase inverter, a buffer, a basic gate unit, a mixed gate unit, an operation unit and a time sequence unit; arranging a delay unit, a pull-up/pull-down unit, a filling unit, a capacitance filling unit, a substrate link and an antenna effect restraining unit in the simplified standard unit library; selecting a multi-input logic by adopting a logical decomposition mode; and realizing a multi-driving capability by adopting a driving decomposition mode. In the method, the performance and the realizing complexity of a circuit are compromised, the quantity of domain pattern shapes is reduced, friendly photolithography is facilitated, the resolution is increased, the manufacturability and realizing efficiency of the circuit are improved, and the performance of the circuit is ensured to a certain degree.
Description
Technical field
The present invention relates to 65 nanometer integrated circuit fabrication process and layout design technical field, be specifically related to a kind of simplifying the method that standard cell lib is optimized.
Background technology
Standard cell lib is the necessary condition of LSI/VLSI The Automation Design, realizes supporting whole The Automation Design flow process from the front end functional simulation to the rear end domain.When the characteristic dimension of integrated circuit dropped to 65 nanometers, the IC manufacturing technology had run into unprecedented challenge, because design scale is increasing, complexity is more and more higher.Manufacturability has become a significant consideration of integrated circuit (IC) design, and from existing design cycle, the designing technique of 65 nanometer standard blocks also faces significant challenge.Standard cell lib carried out optimization is the step of a most critical at manufacturability.
The principle of setting up of traditional standard cell library is to wish to select abundant as far as possible cell type, makes the circuit synthesis instrument that more selection be arranged in combined process, realizes satisfying various constraint conditions such as speed, power consumption and area with the cost of minimum.But the graph data pattern was loaded down with trivial details when such standard cell lib made nanoprocessing, and data processing amount is huge, was unfavorable for the circuit photoetching, made the manufacturability problem face complicated more challenge, directly the efficient of influence production.
In fact, in containing 400 standard cell libs more than the unit, be not each unit for the realization of logic function all be essential.In general, the unit of high driving ability is that many input blocks then are in order to reduce area for satisfied nervous sequential requirement.For power consumption, generally each unit has all been designed the low-power consumption type in the standard cell lib, the driving force of this unit generally is minimum, and for the use of this unit certain skill is arranged, and generally is obsolete not having under the special low power dissipation design requirement situation.And the consistent view of industry is, the design of the following scale of millions of doors is not need low power dissipation design, so the utilization rate of low-power consumption unit is lower.And a standard cell lib must comprise which unit does not have a definite standard, all designs by experience, and the function of most of unit can realize with elementary cell.
Therefore, when the scale down of a standard cell lib arrived to a certain degree, it was in speed, and power consumption, area aspect still are acceptables, will simplify the manufacturability problem like this, reduce data processing amount, have improved production efficiency significantly.
Summary of the invention
(1) technical matters that will solve
For design and the manufacturability problem that solves advanced ASIC digital circuit in the prior art, the invention provides a kind of to simplifying the method that standard cell lib is optimized.
(2) technical scheme
In order to achieve the above object, the technical solution used in the present invention is:
A kind of to simplifying the method that standard cell lib is optimized, this method comprises:
Select to realize the elementary cell of required circuit function, this elementary cell comprises phase inverter, impact damper, elementary gate unit, combination gates unit, arithmetic element and timing unit at least;
In simplifying standard cell lib, increase delay cell, on draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit;
Adopt the logical breakdown mode to select many input logics; And
Adopt the driving is olation to realize many driving forces.
In the such scheme, described selection realizes the step of the elementary cell of required circuit function, be under the requirement of guaranteeing to realize required circuit function, to select the elementary cell that needs,, can travel through all complex logics by these elementary cells are carried out suitable logical combination.
In the such scheme, described delay cell, on draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit, be the design requirement that is used to satisfy the front and back end, guarantee to simplify the function that must realize in the standard cell lib and the functional unit that in simplifying standard cell lib, increases.
In the such scheme, described employing logical breakdown mode is selected in the step of many input logics, adopts by two 2 input logics for 4 input logics and realizes, perhaps adopts 13 input logic and one 1 input logic to realize.
In the such scheme, described employing logical breakdown mode is selected in the step of many input logics, adopts by one 2 input logic and one 3 input logic for 5 input logics and realizes.
In the such scheme, described employing drives is olation and realizes in the step of many driving forces, for phase inverter and impact damper, has designed X4, X8 and X16 separately, to alleviate the anxiety of sequential; Higher driving for other logic functions realizes that the mode that employing will have logic parallel connection or cascade now realizes the high logic that drives.
(3) beneficial effect
Compared with prior art, the beneficial effect of technical solution of the present invention generation is:
1, the present invention is by simplifying standard cell lib quantity, adopt unit the least possible, that really need to realize building of standard cell lib, reduced the number of domain graphics shape, help the photoetching close friend, distinguishable rate is strengthened, improved the manufacturability of circuit.
2, the utilization of the present invention thinking opposite with the traditional standard cell library, adopt unit the least possible, that frequently need to realize complicated as far as possible logic, thereby in the performance of circuit with do compromise above the implementation complexity, reduced the number of domain graphics shape, help the photoetching close friend, distinguishable rate is strengthened, improved the manufacturability of circuit and the high efficiency of realization, guaranteed the performance of circuit again to a certain extent.
Description of drawings
Fig. 1 is for simplifying the method flow diagram of standard cell lib according to the optimization of the embodiment of the invention;
Fig. 2 is for simplifying the synoptic diagram of standard cell lib unit list according to 65 nanometers of the embodiment of the invention;
Fig. 3 is for realizing the synoptic diagram of many driving forces according to the driving is olation of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention is under the situation that guarantees circuit performance, the unit kind that standard cell lib comprised is dropped to a critical numerical value, promptly adopt unit the least possible, that frequently need to travel through all complex logics as far as possible, thereby realize simplifying of cell library, simplify the manufacturability problem.
Provided by the invention to simplifying the method that standard cell lib is optimized, comprising: select to realize the elementary cell of required circuit function, this elementary cell comprises phase inverter, impact damper, elementary gate unit, combination gates unit, arithmetic element and timing unit at least; In simplifying standard cell lib, increase delay cell, on draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit; Adopt the logical breakdown mode to select many input logics; And adopt the driving is olation to realize many driving forces.
Traditional standard cell lib comprises up to a hundred unit, yet a lot of unit performance impact to circuit when circuit synthesis is little.But, phase inverter for example, Sheffer stroke gate, elementary cells such as rejection gate then often are used to, be make up circuit substantially must the unit.More complicated unit such as 8 input bonus point devices etc. seldom are used.The performance of circuit can not descend to some extent because of the minimizing of these unit.Because these complex unit utilization rates are very low, when really needing, the present invention can make up with basic simple unit, no matter be at circuit area, power consumption still is the sequential aspect, though with respect to complete standard cell lib loss is arranged like this, loss concentrates in this scope of 5%-10%, and being lost in the standard block zone in this scope is complete acceptable.Because reducing of characteristic dimension, in order to reduce the difficulty of manufacturability, the present invention expects to use the logical block of the least possible kind to realize circuit function.Want to reach this target, must adopt certain method choice criteria unit.
The method that standard cell lib is optimized provided by the invention has been used the thinking opposite with the traditional standard cell library, and complicated as far as possible logic is realized in the unit of frequently need selecting, and specifically may further comprise the steps:
At first, realize under the requirement of all required circuit functions the elementary cell of need selecting guaranteeing, such as phase inverter, impact damper, elementary gate unit, the combination gates unit, arithmetic element and timing unit, the suitable logical combination by these unit travels through all complex logics as far as possible.
Secondly, along with dwindling day by day of integrated circuit characteristic dimension, special process manufacturability problem has appearred in 65 nanometer nodes, as the standard cell lib of a practicality, the design requirement of consideration front and back end that must be complete, therefore the present invention introduces multiple special element, such as delay cell, on draw/drop-down unit, filler cells, the electric capacity filler cells, substrate link and antenna effect suppress the unit, to guarantee to simplify the function that must realize in the standard cell lib.
The 3rd, adopt logical breakdown mode (Decomposition) to select many input logics.For example, 4 input logics can be realized by two 2 input logics or 13 input logic and one 1 input logic, 5 input logics can be realized by one 2 input logic and one 3 input logic, so, for the many input logics role in cell library as 4 inputs and 5 are imported more is optimization aspect the area, be and import square being directly proportional of number that therefore, high input logic gate generally has been a negative interaction for postponing to optimize and gate delay is actual.And above-mentioned logical breakdown mode still is highly effective, can not introduce too many space wastage.
The 4th, adopt the driving is olation to realize many driving forces, in order to exceed the problem that solves driving force under the situation that increases the unit kind, the present invention takes following scheme: for phase inverter and impact damper, the present invention has designed X4 separately, X8 and X16, its objective is the anxiety of alleviating sequential, higher driving for other logic functions realizes, the present invention is still in line with the principle that does not increase the unit kind as far as possible, the present invention adopts the mode that will have logic parallel connection or cascade now to realize the high logic that drives, this mode can be introduced must additional delay, the still transit time that can improve output signal greatly.And gate delay actual be all related with the transit time of output load and input signal, the look-up table that the cell delay information in the .lib file that standard cell lib is done for the EDA synthesis tool is made according to input signal transit time and two indexs of output load just.So, should cascade high driving ability phase inverter for whether and impact damper should decide by synthesis tool.
The method of standard block library unit is simplified in optimization provided by the invention, the described standard cell lib of simplifying should comprise combinatorial logic unit, sequential logic unit and special applications unit, adopt logical breakdown mode (Decomposition) to select many input logics, adopt the driving is olation to realize many driving forces.Wherein, travel through whole design cell, and support the design of 65 nanometer special process circuit manufacturability effectively by combinatorial logic unit, the suitable combination in sequential logic unit and special applications unit.This method has reduced the number of domain graphics shape, helps the photoetching close friend, and distinguishable rate is strengthened, and has improved the manufacturability of circuit and the high efficiency of realization.
Referring to Fig. 1, Fig. 1 is for simplifying the method flow diagram of standard cell lib according to the optimization of the embodiment of the invention, this method is the selection principle of analytical standard cell library elementary cell at first, and be the design that standard block is carried out on the basis with 65 nanometer SPICE MODEL of typical process manufacturer and DFM technical papers and other technical paperss.Under the situation that guarantees circuit performance, the unit kind that standard cell lib comprised is dropped to a critical numerical value, promptly adopt unit the least possible, that frequently need to travel through all complex logics as far as possible.Thereby realize simplifying of cell library, simplify the manufacturability problem.
For the selection of simplifying the standard block library unit, phase inverter, impact damper, Sheffer stroke gate, rejection gate, XOR gate, trigger and latch often are used in the circuit design process, are basic necessary unit, must include in the standard cell lib, as shown in Figure 2.Seldom be used when the circuit design for some complicated unit, the performance impact to circuit when circuit synthesis is little, and the performance of circuit can not descend to some extent because of the minimizing of these unit.When real needs they the time, the present invention makes up with basic simple unit, no matter be at circuit area, power consumption still is the sequential aspect, though with respect to complete standard cell lib loss is arranged like this, but loss concentrates in this scope of 5%-10%, and being lost in the standard block zone in this scope is complete acceptable.For many input logics, the present invention adopts logical breakdown mode (Decomposition) to select.For example, 4 input logics can realize that 5 input logics can be realized by one 2 input logic and one 3 input logic by two 2 input logics or 13 input logic and one 1 input logic.Above-mentioned logical breakdown mode still is highly effective, can not introduce too many space wastage.This has added basic logical block so that carry out logical breakdown, and the unit kind mainly contains: different and non-unit, XNOR unit, selected cell, AOI unit and inclusive NAND unit.And these unit substantially all are 2 input and 3 input blocks.The present invention simplifies in the standard cell lib driver element that has also designed X4, X8 and X16 at phase inverter and impact damper, its objective is in order to alleviate the anxiety of sequential.Referring to Fig. 3, higher driving for other logic functions realizes, the present invention is still in line with the principle that does not increase the unit kind as far as possible, the present invention adopts the mode that will have logic parallel connection or cascade now to realize the high logic that drives, though this many driving forces is olation can be introduced must additional delay, postpone fully within the acceptable range.Simultaneously, because special process manufacturability problem has appearred in dwindling day by day of characteristic dimension, 65 nanometer nodes, as the standard cell lib of a practicality, the design requirement of consideration front and back end that must be complete, therefore the present invention introduces multiple special element, such as delay cell, on draw/drop-down unit, filler cells, the electric capacity filler cells, substrate link and antenna effect suppress the unit, to guarantee to simplify the function that must realize in the standard cell lib.
Simplify cell library and realize complicated as far as possible logic by adopting unit the least possible, that frequently need, thereby in the performance of circuit with do compromise above the implementation complexity, reduced the number of domain graphics shape, reduced the quantity of photoetching stage graphics process effectively, help the photoetching close friend, distinguishable rate is strengthened, improved the manufacturability of circuit, guaranteed the performance of circuit again to a certain extent.
With the present invention design simplify standard cell lib and traditional standard cell lib is applied on a plurality of benchmark test circuit, comprehensively compare sequential, area and power consumption performance.The present invention finds, aspect circuit delay, the present invention's design simplify standard cell lib and complete standard cell lib gap very little, basic controlling is in 5%; Aspect circuit area, simplify standard cell lib and concentrate in this scope of 5%-10% with respect to the loss of complete standard cell lib; Aspect power consumption, simplify standard cell lib and substantially all be controlled in 5% than the loss of complete standard cell lib.So, optimization of the present invention simplify that standard cell lib has must practical value.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. one kind to simplifying the method that standard cell lib is optimized, and it is characterized in that this method comprises:
Select to realize the elementary cell of required circuit function, this elementary cell comprises phase inverter, impact damper, elementary gate unit, combination gates unit, arithmetic element and timing unit at least;
In simplifying standard cell lib, increase delay cell, on draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit;
Adopt the logical breakdown mode to select many input logics; And
Adopt the driving is olation to realize many driving forces.
2. according to claim 1 to simplifying the method that standard cell lib is optimized, it is characterized in that, described selection realizes the step of the elementary cell of required circuit function, be under the requirement of guaranteeing to realize required circuit function, to select the elementary cell that needs, by these elementary cells are carried out suitable logical combination, can travel through all complex logics.
3. according to claim 1 to simplifying the method that standard cell lib is optimized, it is characterized in that, described delay cell, on draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit, be the design requirement that is used to satisfy the front and back end, guarantee to simplify the function that must realize in the standard cell lib and the functional unit that in simplifying standard cell lib, increases.
4. according to claim 1 to simplifying the method that standard cell lib is optimized, it is characterized in that, described employing logical breakdown mode is selected in the step of many input logics, adopt by two 2 input logics realizations for 4 input logics, perhaps adopt 13 input logic and one 1 input logic to realize.
5. according to claim 1ly it is characterized in that to simplifying the method that standard cell lib is optimized described employing logical breakdown mode is selected in the step of many input logics, adopt by one 2 input logic and one 3 input logic for 5 input logics and realize.
6. according to claim 1 to simplifying the method that standard cell lib is optimized, it is characterized in that described employing drives is olation and realizes in the step of many driving forces, for phase inverter and impact damper, X4, X8 and X16 have been designed separately, to alleviate the anxiety of sequential; Higher driving for other logic functions realizes that the mode that employing will have logic parallel connection or cascade now realizes the high logic that drives.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110082736 CN102279899B (en) | 2011-04-01 | 2011-04-01 | Method for optimizing simplified standard unit library |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110082736 CN102279899B (en) | 2011-04-01 | 2011-04-01 | Method for optimizing simplified standard unit library |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102279899A true CN102279899A (en) | 2011-12-14 |
| CN102279899B CN102279899B (en) | 2013-05-01 |
Family
ID=45105341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110082736 Active CN102279899B (en) | 2011-04-01 | 2011-04-01 | Method for optimizing simplified standard unit library |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102279899B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107784136A (en) * | 2016-08-24 | 2018-03-09 | 中国科学院微电子研究所 | The creation method and system of a kind of standard cell lib |
| CN108846160A (en) * | 2018-05-03 | 2018-11-20 | 上海华虹宏力半导体制造有限公司 | Standard cell lib circuit design method |
| CN108959696A (en) * | 2017-05-19 | 2018-12-07 | 台湾积体电路制造股份有限公司 | Extension includes the method and system of the standard block group in library |
| CN112100158A (en) * | 2020-09-21 | 2020-12-18 | 海光信息技术有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080295057A1 (en) * | 2007-05-22 | 2008-11-27 | Dar-Sun Tsien | Method for determining a standard cell for ic design |
| CN101990671A (en) * | 2008-02-05 | 2011-03-23 | 纳恩盖特公司 | Optimization of integrated circuit design and library |
-
2011
- 2011-04-01 CN CN 201110082736 patent/CN102279899B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080295057A1 (en) * | 2007-05-22 | 2008-11-27 | Dar-Sun Tsien | Method for determining a standard cell for ic design |
| CN101990671A (en) * | 2008-02-05 | 2011-03-23 | 纳恩盖特公司 | Optimization of integrated circuit design and library |
Non-Patent Citations (3)
| Title |
|---|
| LUO HAIYAN等: "A design method for process design kit based on a SMIC 65 nm process", 《JOURNAL OF SEMICONDUCTORS》 * |
| 宁涉洋: "深亚微米标准单元库设计与优化", 《中国优秀硕士学位论文全文数据库》 * |
| 高丽江: "UMC 0. 18um异步电路标准单元库建库技术研究", 《微电子学》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107784136A (en) * | 2016-08-24 | 2018-03-09 | 中国科学院微电子研究所 | The creation method and system of a kind of standard cell lib |
| CN107784136B (en) * | 2016-08-24 | 2021-02-12 | 中国科学院微电子研究所 | Method and system for creating standard cell library |
| CN108959696A (en) * | 2017-05-19 | 2018-12-07 | 台湾积体电路制造股份有限公司 | Extension includes the method and system of the standard block group in library |
| CN108959696B (en) * | 2017-05-19 | 2022-10-11 | 台湾积体电路制造股份有限公司 | Method, system and computer readable medium for extending a set of standard cells comprising a library |
| CN108846160A (en) * | 2018-05-03 | 2018-11-20 | 上海华虹宏力半导体制造有限公司 | Standard cell lib circuit design method |
| CN108846160B (en) * | 2018-05-03 | 2023-03-10 | 上海华虹宏力半导体制造有限公司 | Standard cell library circuit design method |
| CN112100158A (en) * | 2020-09-21 | 2020-12-18 | 海光信息技术有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| CN112100158B (en) * | 2020-09-21 | 2022-11-22 | 海光信息技术股份有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102279899B (en) | 2013-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9178518B2 (en) | Sub-threshold FPGA and related circuits and methods thereof | |
| Rasouli et al. | Low-power single-and double-edge-triggered flip-flops for high-speed applications | |
| CN102279899B (en) | Method for optimizing simplified standard unit library | |
| CN102487272A (en) | Integrated circuit, clock gate control circuit and method | |
| CN102684646A (en) | Single-edge master-slave D trigger | |
| Prakash et al. | Achieveing reduced area by multi-bit flip flop design | |
| US20110260764A1 (en) | Semiconductor integrated circuit, method for designing semiconductor integrated circuit, and computer readable recording medium | |
| CN102983841A (en) | Reversible master-slave RS flip-flop based on reversible logical gate | |
| CN101350612A (en) | Circuit for preventing gating clock bur | |
| CN102819418A (en) | FIFO data storage method and device of ultrafine particle gated clock | |
| Maity et al. | Design and implementation of low-power high-performance carry skip adder | |
| Rajagopal et al. | A novel high-performance hybrid full adder for VLSI circuits | |
| Bhattacharjee et al. | A variation-aware robust gated flip-flop for power-constrained FSM application | |
| CN102522950A (en) | Electronic chip with output signal slew rate control function | |
| Ismail et al. | Low power design of Johnson counter using clock gating | |
| CN102386908B (en) | Heat insulation domino circuit and heat insulation domino ternary AND gate circuit | |
| CN101689851A (en) | Logic state catching circuits | |
| US8418102B2 (en) | Optimization of library slew ratio based circuit | |
| Fan et al. | An efficient design of parallel and serial shift registers based on quantum-dot cellular automata | |
| Lee et al. | Low power null convention logic circuit design based on DCVSL | |
| Smith et al. | 14 Future of Asynchronous Logic | |
| Sudheer et al. | Design and implementation of embedded logic flip-flop for low power applications | |
| Sasamal et al. | Design of Registers and Memory in QCA | |
| Tambe et al. | Design and Analysis of (2x1) and (4x1) Multiplexer Circuit in Quantum dot Cellular Automata Approach | |
| CN104679216B (en) | A kind of data path means and its control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: WUXI ZHONGKE MICROELECTRONIC INDUSTRIAL TECHNOLOGY Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20120406 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100029 CHAOYANG, BEIJING TO: 214028 WUXI, JIANGSU PROVINCE |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20120406 Address after: 214028 Jiangsu province Wuxi District Road No. 200 Chinese Linghu Sensor Network International Innovation Park C Building 9 floor Applicant after: WUXI ZHONGKE MICROELECTRONIC INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Applicant before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |