CN110829984A - High-linearity power amplifier - Google Patents

High-linearity power amplifier Download PDF

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Publication number
CN110829984A
CN110829984A CN201810919495.6A CN201810919495A CN110829984A CN 110829984 A CN110829984 A CN 110829984A CN 201810919495 A CN201810919495 A CN 201810919495A CN 110829984 A CN110829984 A CN 110829984A
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pmos
tube
circuit
transistor
nmos
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CN110829984B (en
Inventor
任达明
刘览琦
逯召静
石琴琴
胡昂
杨阳
谭珍
张科峰
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Wuhan Syntek Ltd
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Wuhan Syntek Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/26—Push-pull amplifiers; Phase-splitters therefor
    • H03F3/265—Push-pull amplifiers; Phase-splitters therefor with field-effect transistors only

Abstract

The invention discloses a high-linearity power amplifier, which comprises a main body amplifying circuit (100) and a bias voltage generating circuit (200); the main body amplifying circuit (100) comprises a first push-pull power amplifying circuit (101) and a second push-pull power amplifying circuit (102), and the first push-pull power amplifying circuit (101) and the second push-pull power amplifying circuit (102) form a complementary symmetrical circuit; the bias voltage generating circuit (200) comprises a first bias voltage generating circuit (201) and a second bias voltage generating circuit (202); the main body amplifying circuit (100) is used for amplifying an input signal of the high-linearity power amplifier; the bias voltage generating circuit (200) is used for providing bias voltage for the main body amplifying circuit (100). The invention can reduce the third-order intermodulation point of the high-linearity power amplifier in large signal and improve the linearity of the high-linearity power amplifier.

Description

High-linearity power amplifier
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a high-linearity power amplifier.
Background
After the 21 st century, the contradiction between energy demand and supply becomes more and more prominent, and every industry all over the world strives to achieve high-efficiency utilization of energy, which puts high requirements on wireless communication integrated circuit systems and covers a series of harsher indexes such as low voltage, low power consumption, high performance, light weight, small volume and the like. At present, mobile communication devices are all designed by digital-analog hybrid integrated circuits, i.e. the front-end radio frequency receiving circuit part is an analog system, and the part behind the back-end a/D converter is a digital system. Due to the requirements of low voltage, low power consumption and small size, the single-chip integration of the front-end analog rf circuit and the back-end digital circuit is becoming the mainstream trend. The working voltage and power consumption of the present digital system can be made very low, while the low voltage of the digital circuit is not suitable for the analog rf circuit to work, because when the analog rf circuit and the back-end digital circuit share the same voltage, the dynamic range, linearity, working frequency and gain of the rf circuit will be limited by the voltage drop. The Power Amplifier (PA) is located at the final stage of the transmitter, and amplifies the modulated signal to a certain power value, and sends the amplified signal to the antenna for transmission, so that the relevant receiver can receive satisfactory signal level, and meanwhile, the normal operation of other adjacent wireless communication systems is not interfered. The power amplifier determines the quality of the output signal, and with the continuous development of communication systems, the power amplifier has higher and higher requirements on linearity, so that the integrity of a transmitted signal is ensured.
The current techniques for improving the linearity of the power amplifier mainly include digital predistortion and envelope injection. The digital predistortion technique is the most common linearity improvement technique in use today, but its feedback loop causes area and power loss; envelope injection techniques can improve the linearity of a power amplifier over a sufficiently wide bandwidth, but the injected signal cannot be accurately controlled and can artificially distort the signal. In the design of a broadband power amplifier, the push-pull amplifier is used as a common structure, so that the chip area and the power consumption of the power amplifier can be saved. However, the use of the push-pull amplifier has a problem that the linearity of the push-pull power amplifier is low when a large signal is used.
Disclosure of Invention
Aiming at the problem of strong compromise among linearity, power consumption and chip area in the existing widely-applied power amplifier, the invention provides a power amplifier with high linearity, which reduces the third-order intermodulation point of the power amplifier when a large signal is generated and improves the linearity of the power amplifier.
The invention provides a power amplifier with high linearity, which comprises a main body amplifying circuit and a bias voltage generating circuit, wherein the main body amplifying circuit comprises a main body amplifier and a bias voltage generating circuit;
the main body amplifying circuit consists of two complementary symmetrical circuits and comprises a first push-pull power amplifying circuit and a second push-pull power amplifying circuit;
the main body amplifying circuit comprises a first push-pull power amplifying circuit and a second push-pull power amplifying circuit, and the first push-pull power amplifying circuit and the second push-pull power amplifying circuit form a complementary symmetrical circuit;
the first push-pull power amplification circuit comprises two MOS tubes with complementary tube types: a first PMOS tube and a first NMOS tube;
the second push-pull power amplification circuit comprises two MOS tubes with complementary tube types: a second PMOS tube and a second NMOS tube;
the bias voltage generating circuit comprises a first bias voltage generating circuit and a second bias voltage generating circuit;
the first bias voltage generation circuit provides grid voltage for the first PMOS tube, and the first PMOS tube is biased in a linear region by adjusting the impedance value of components in the first bias voltage generation circuit;
the second bias voltage generating circuit provides grid voltage for the second PMOS tube, and the second PMOS tube is biased in a linear region by adjusting the impedance value of components in the second bias voltage generating circuit;
the main body amplifying circuit is used for amplifying the input signal of the high-linearity power amplifier.
Preferably, the source electrode of the first PMOS transistor is connected to the source electrode of the second PMOS transistor; the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube;
the first PMOS tube and the first NMOS tube form a primary amplifier circuit;
the first PMOS tube is used for amplifying a positive half cycle of the high-linearity power amplifier input signal;
the first NMOS transistor is used for amplifying a negative half cycle of the high linearity power amplifier input signal;
the half-cycle signals output by the first PMOS tube and the first NMOS tube are combined into an output signal of a complete cycle at the connection position of the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube;
the second PMOS tube and the second NMOS tube form another stage of amplifier circuit;
the second PMOS tube is used for amplifying the positive half cycle of the input signal of the high-linearity power amplifier;
the second NMOS tube is used for amplifying the negative half cycle of the input signal of the high-linearity power amplifier;
and the half-cycle signals output by the second PMOS tube and the second NMOS tube are combined into an output signal of another complete cycle at the joint of the drain electrode of the first PMOS tube and the drain electrode of the second NMOS tube.
Preferably, the first bias voltage circuit comprises a third PMOS transistor, a third NMOS transistor and a first resistor; the third PMOS tube, the third NMOS tube and the first resistor form a voltage division circuit;
when the grid voltage of the first PMOS tube is smaller than the difference between the source voltage and the grid voltage of the first PMOS tube, the first PMOS tube is biased in a linear region by adjusting the impedance values of a third PMOS tube, a third NMOS tube and a first resistor;
preferably, the second bias voltage circuit comprises a fourth PMOS transistor, a fourth NMOS transistor and a second resistor; the fourth PMOS tube, the fourth NMOS tube and the second resistor form a voltage division circuit;
and when the grid voltage of the second PMOS tube is smaller than the difference between the source voltage and the grid voltage of the second PMOS tube, the second PMOS tube is biased in a linear region by adjusting the impedance values of the fourth PMOS tube, the fourth NMOS tube and the second resistor.
Preferably, the first bias voltage generating circuit includes a third PMOS transistor, a third NMOS transistor, and a first resistor;
the second bias voltage generating circuit comprises a fourth PMOS tube, a fourth NMOS tube and a second resistor;
the source electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube;
the drain electrode of the third PMOS tube is connected with the grid electrode of the first PMOS tube;
the source electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube;
the drain electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube;
the source electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube;
the drain electrode of the fourth PMOS tube is connected with the grid electrode of the second PMOS tube;
the source electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube;
and the drain electrode of the fourth NMOS tube is connected with the grid electrode of the second NMOS tube.
Preferably, the first NMOS transistor and the second NMOS transistor always operate in a saturation region.
Preferably, when the input voltage of the first PMOS transistor is greater than the threshold voltage of the first PMOS transistor, the first PMOS transistor is used for compensating the gain of the first NMOS transistor;
when the input voltage of the second PMOS tube is greater than the threshold voltage of the second PMOS tube, the second PMOS tube is used for compensating the gain of the second NMOS tube;
preferably, the input voltages of the first push-pull power amplifying circuit and the second push-pull power amplifying circuit have opposite polarities and equal magnitudes;
the output end voltages of the first push-pull power amplifying circuit and the second push-pull power amplifying circuit are opposite in polarity and equal in size.
Preferably, in a large signal, a first derivative and a second derivative of transconductance of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are superimposed, so that when the first derivative and the second derivative of transconductance of the power amplifier approach to 0, the first PMOS transistor and the second PMOS transistor are biased in a linear region.
One or more technical schemes provided by the invention at least have the following technical effects or advantages:
the first PMOS tube in the first push-pull power amplifying circuit and the second PMOS tube in the second push-pull power amplifying circuit are biased in a linear region, and when a signal is large, after the first derivative and the second derivative of transconductance of the first PMOS tube and the second PMOS tube and transconductance of the first NMOS tube and the second NMOS tube are superposed, the first derivative and the second derivative of transconductance of the high-linearity power amplifier are close to 0, so that second harmonic components and Third harmonic components output by the power amplifier are reduced to reduce Third-Order Intermodulation points (IMD 3) of the power amplifier. And the structure is simple, and the occupied area and the power consumption of the chip are saved.
Drawings
In order to more clearly illustrate the operation principle and the technical scheme of the invention, the following briefly describes the operation principle and the attached drawings needed in the technology. It is obvious that the drawings in the following description are only some working examples of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a block diagram of a high linearity power amplifier of the present invention;
FIG. 2 is a circuit schematic of a high linearity power amplifier of the present invention;
FIG. 3(a) is a simulation diagram of the transconductance curve of a high linearity power amplifier of the present invention;
FIG. 3(b) is a simulation diagram of the transconductance first derivative curve of a high linearity power amplifier of the present invention;
FIG. 3(c) is a simulation diagram of the transconductance second derivative curve of a high linearity power amplifier according to the present invention;
fig. 4 is a graph of IMD3 simulation results for a high linearity power amplifier of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the operation principle of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The present invention provides a power amplifier with high linearity, as shown in fig. 1, comprising a main body amplifying circuit 100 and a bias voltage generating circuit 200;
the main body amplifying circuit 100 comprises a first push-pull power amplifying circuit 101 and a second push-pull power amplifying circuit 102, wherein the first push-pull power amplifying circuit 101 and the second push-pull power amplifying circuit 102 form a complementary symmetrical circuit;
the bias voltage generating circuit 200 includes a first bias voltage generating circuit 201 and a second bias voltage generating circuit 202;
the main body amplifying circuit 100 is configured to amplify an input signal of the high-linearity power amplifier;
the bias voltage generating circuit 200 is used for providing a bias voltage for the main body amplifying circuit 100.
Specifically, the first push-pull power amplifier circuit 101 and the second push-pull power amplifier circuit 102 have the same circuit structure.
Specifically, the input voltages of the first push-pull power amplifier circuit 101 and the second push-pull power amplifier circuit 102 have opposite polarities and equal magnitudes.
Specifically, the output voltages of the first push-pull power amplifier circuit 101 and the second push-pull power amplifier circuit 102 have opposite polarities and equal magnitudes.
Specifically, the first bias voltage generating circuit 201 and the second bias voltage generating circuit 202 have the same circuit structure.
In a specific embodiment, as shown in fig. 2:
the first push-pull power amplifying circuit 101 includes two MOS transistors of complementary tube types: a first PMOS transistor PM1 and a first NMOS transistor NM 1. The second push-pull power amplifying circuit 102 includes two MOS transistors of complementary tube types: a second PMOS transistor PM2 and a second NMOS transistor NM 2. The source electrode of the first PMOS tube PM1 is butted with the source electrode of the second PMOS tube PM2, and the butting end is connected with a first voltage source VDD; the drain electrode of the first PMOS tube PM1 is butted with the drain electrode of the first NMOS tube NM1, and the butted end is connected with one end VOUT + of the differential output end; the drain electrode of the second PMOS tube PM2 is butted with the drain electrode of the second NMOS tube NM2, and the butted end is connected with the other end VOUT < - > of the differential output end; the source of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2, and the connection terminal is grounded VGND.
Specifically, a first PMOS transistor PM1 and a first NMOS transistor NM1 constitute a one-stage amplifier circuit; the first PMOS pipe PM1 is used for amplifying the positive half cycle of the input signal of the power amplifier with high linearity; the first NMOS transistor NM1 is used to amplify the negative half cycle of the input signal of the high linearity power amplifier; half-cycle signals output by the first PMOS transistor PM1 and the first NMOS transistor NM1 are combined into an output signal of a complete cycle at the connection of the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM 1.
Specifically, the first NMOS transistor NM1 operates in the saturation region at all times.
Specifically, when the input voltage of the first PMOS transistor PM1 is greater than the threshold voltage of the first PMOS transistor PM1, the first PMOS transistor PM1 is used to compensate the gain of the first NMOS transistor NM 1.
Since the circuit structures of the first push-pull power amplifying circuit 101 and the second push-pull power amplifying circuit 102 are completely the same, the characteristics of the circuit components in the second push-pull power amplifying circuit 102 are the same as those of the circuit components in the first push-pull power amplifying circuit 101, and the working principle is also the same.
In a specific embodiment, as shown in fig. 2:
the first bias voltage circuit 201 comprises a third PMOS transistor PM3, a third NMOS transistor NM3 and a first resistor R1; the second bias voltage circuit 202 includes a fourth PMOS transistor PM4, a fourth NMOS transistor NM4, and a second resistor R2. The source electrode of the third PMOS transistor PM3 is connected with the source electrode of the first PMOS transistor PM 1; the grid electrode and the drain electrode of the third PMOS pipe PM3 are connected; the drain electrode of the third PMOS pipe PM3 is connected with one end of the first resistor R1 and one end of the third resistor R3; the grid electrode of the first PMOS pipe PM1 is connected with the other end of the third resistor R3; the grid electrode and the drain electrode of the third NMOS tube NM3 are connected; the source of the third NMOS transistor NM3 is connected to the source of the first NMOS transistor NM 1; the drain of the third NMOS transistor NM3 is connected to the other end of the first resistor R1 and one end of the fifth resistor R5; the grid electrode of the first NMOS tube NM1 is connected with the other end of the fifth resistor R5; the source electrode of the fourth PMOS transistor PM4 is connected with the source electrode of the second PMOS transistor PM 2; the grid electrode and the drain electrode of the fourth PMOS pipe PM4 are connected; the drain of the fourth PMOS transistor PM4 is connected to one end of the second resistor R2 and one end of the fourth resistor R4; the grid electrode of the second PMOS pipe PM2 is connected with the other end of the fourth resistor R4; the grid electrode and the drain electrode of the fourth NMOS tube NM4 are connected; the source of the fourth NMOS transistor NM4 is connected to the source of the second NMOS transistor NM 2; the drain of the fourth NMOS transistor NM4 is connected to the other end of the second resistor R2 and one end of the sixth resistor R6; the gate of the second NMOS transistor NM2 is connected to the other end of the sixth resistor R6.
Specifically, the third PMOS transistor PM3, the third NMOS transistor NM3 and the first resistor R1 form a voltage divider circuit, which shares the voltage of the first voltage source VDD and provides the gate voltage for the first PMOS transistor PM 1; the fourth PMOS transistor PM4, the fourth NMOS transistor NM4, and the second resistor R2 form another voltage divider circuit, which shares the voltage of the first voltage source VDD and provides the gate voltage for the second PMOS transistor PM 2.
Specifically, the bias voltage generating circuit in the invention adopts the third PMOS transistor PM3, the third NMOS transistor NM3, the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4, so that the influence of process and temperature on the bias voltage of the push-pull amplifier can be reduced, and the PM1 and the PM2 are ensured to be biased in a linear region under different process angles and temperatures, thereby ensuring the normal function of the whole circuit.
In this embodiment, the first PMOS transistor PM1 may be biased in the linear region by controlling the magnitudes of the resistance values of the third PMOS transistor PM3, the third NMOS transistor NM3, and the first resistor R1. This is because the third PMOS transistor PM3, the third NMOS transistor NM3 and the first resistor R1 form a voltage divider circuit, which shares the voltage of the first voltage source VDD and provides the gate voltage for the first PMOS transistor PM 1. When the gate voltage of the first PMOS transistor PM1 is less than the difference between the source voltage and the gate voltage of the first PMOS transistor PM1, the first PMOS transistor PM1 is biased in the linear region. Similarly, the second PMOS transistor PM2 may be biased in the linear region by controlling the magnitudes of the resistance values of the fourth PMOS transistor PM4, the fourth NMOS transistor NM4, and the second resistor R2.
Output AC leakage current i of the inventive circuitdsAfter expansion by taylor series, as shown in formula (1):
Figure BDA0001763831010000081
Figure BDA0001763831010000082
wherein Vgs is input DC signal swing, Ids is output DC leakage current, gmkThe derivative of the order k-1, gm, of the transconductance of the circuitkThe calculation method of (2) is shown in formula (3):
gmk＝gmk-N+gmk-P(3)
wherein, gmk_NIs the transconductance sum, gm, of a first NMOS transistor NM1 and a second NMOS transistor NM2 in the circuitk_PIs the transconductance sum of the first PMOS transistor PM1 and the second PMOS transistor PM2 in the circuit.
The power amplifier is a nonlinear device, and in order to improve the linearity of the power amplifier, the harmonic component of the output of the power amplifier, namely the k-1 order derivative of the transconductance of the circuit, is reduced.
Therefore, it can be known from equations (1), (2) and (3) that the absolute values of the first and second derivatives of the transconductance in equation (1) need to be close to 0 if the linearity of the circuit is to be improved.
FIGS. 3 (a-c) show the transconductance gm of the whole circuit when the first PMOS transistor PM1 and the second PMOS transistor PM2 in the PA circuit of the present invention are biased in the linear region and the saturation region, respectivelykThe voltage of the first PMOS transistor PM1 and the second PMOS transistor PM2 is set to 1034mV, and the voltage of the first NMOS transistor NM1 and the second NMOS transistor NM2 is set to 575 mV. As can be seen from fig. 3(a), when PM1 and PM2 are biased in the linear region, the curve of transconductance gm1 is smoother when the input signal is greater than 230 mV; as can be seen from fig. 3(b), (c), when PM1 and PM2 are biased in the linear region, the curves of the transconductance first derivative gm2 and the transconductance second derivative gm3 are closer to 0. Therefore, it is shown that in large signals, the linearity of the circuit when PM1 and PM2 are biased in the linear region is better than that when PM1 and PM2 are biased in the saturation region, and as a result of simulation, as shown in fig. 4, when the input power is greater than-16 dBm, IMD3 of the circuit when PM1 and PM2 are biased in the linear region is far lower than IMD3 of the circuit when PM1 and PM2 are biased in the saturation region, and the difference is at most 21.7 dBc.
The invention mainly aims at the problem of strong compromise among linearity, power consumption and chip area in the widely applied power amplifier, the PMOS is biased in a linear region while adopting a push-pull power amplifier structure, and when a signal is large, after the first derivative and the second derivative of transconductance of a first PMOS tube, a second PMOS tube and a first NMOS tube and a second NMOS tube are superposed, the first derivative and the second derivative of the transconductance of the power amplifier with high linearity in the invention approach to 0, thereby reducing second harmonic component and third harmonic component output by the power amplifier to reduce IMD3 of the power amplifier. It can be proved that the circuit can realize high linearity performance and save the chip area and power consumption of the power amplifier.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. A high linearity power amplifier, comprising a body amplifying circuit (100) and a bias voltage generating circuit (200);
the main body amplifying circuit (100) comprises a first push-pull power amplifying circuit (101) and a second push-pull power amplifying circuit (102), and the first push-pull power amplifying circuit (101) and the second push-pull power amplifying circuit (102) form a complementary symmetrical circuit;
the first push-pull power amplification circuit (101) comprises two MOS tubes with complementary tube types: a first PMOS transistor (PM1) and a first NMOS transistor (NM 1);
the second push-pull power amplification circuit (102) comprises two MOS tubes with complementary tube types: a second PMOS transistor (PM2) and a second NMOS transistor (NM 2);
the bias voltage generating circuit (200) comprises a first bias voltage generating circuit (201) and a second bias voltage generating circuit (202);
the first bias voltage generation circuit (201) provides a gate voltage for the first PMOS transistor (PM1), and the impedance value of components in the first bias voltage generation circuit (201) is adjusted to bias the first PMOS transistor (PM1) in a linear region;
the second bias voltage generation circuit (202) provides a gate voltage for the second PMOS transistor (PM2), and the impedance value of components in the second bias voltage generation circuit (202) is adjusted to bias the second PMOS transistor (PM2) in a linear region;
the main body amplifying circuit (100) is used for amplifying an input signal of the high-linearity power amplifier.
2. The power amplifier of claim 1, wherein the source of the first PMOS transistor (PM1) is connected to the source of the second PMOS transistor (PM 2); the drain electrode of the first PMOS pipe (PM1) is connected with the drain electrode of the first NMOS pipe (NM 1); the drain electrode of the second PMOS pipe (PM2) is connected with the drain electrode of the second NMOS pipe (NM 2); the source electrode of the first NMOS transistor (NM1) is connected with the source electrode of the second NMOS transistor (NM 1);
the first PMOS tube (PM1) and the first NMOS tube (NM1) form a first-stage amplifier circuit;
the first PMOS transistor (PM1) is used for amplifying the positive half cycle of the high-linearity power amplifier input signal;
the first NMOS transistor (NM1) is used for amplifying the negative half cycle of the high-linearity power amplifier input signal;
the half-cycle signals output by the first PMOS transistor (PM1) and the first NMOS transistor (NM1) are combined into an output signal of a complete cycle at the connection position of the drain electrode of the first PMOS transistor (PM1) and the drain electrode of the first NMOS transistor (NM 1);
the second PMOS tube (PM2) and the second NMOS tube (NM2) form another stage of amplifier circuit;
the second PMOS tube (PM2) is used for amplifying the positive half cycle of the high-linearity power amplifier input signal;
the second NMOS transistor (NM2) is used for amplifying the negative half cycle of the input signal of the power amplifier with high linearity;
the half-cycle signals output by the second PMOS transistor (PM2) and the second NMOS transistor (NM2) are combined into an output signal of another complete cycle at the connection position of the drain electrode of the first PMOS transistor (PM1) and the drain electrode of the second NMOS transistor (NM 2).
3. The power amplifier of high linearity of claim 1, wherein the first bias voltage circuit (201) comprises a third PMOS transistor (PM3), a third NMOS transistor (NM3) and a first resistor (R1); the third PMOS tube (PM3), the third NMOS tube (NM3) and the first resistor (R1) form a voltage division circuit;
when the grid voltage of the first PMOS tube (PM1) is smaller than the difference between the source voltage and the grid voltage of the first PMOS tube (PM1), the first PMOS tube (PM1) is biased in a linear region by adjusting the impedance values of a third PMOS tube (PM3), a third NMOS tube (NM3) and a first resistor (R1).
4. The power amplifier of high linearity of claim 1, wherein the second bias voltage circuit (202) comprises a fourth PMOS transistor (PM4), a fourth NMOS transistor (NM4) and a second resistor (R2); a fourth PMOS tube (PM4), a fourth NMOS tube (NM4) and a second resistor (R2) form a voltage division circuit;
when the gate voltage of the second PMOS transistor (PM2) is smaller than the difference between the source voltage and the gate voltage of the second PMOS transistor (PM2), the second PMOS transistor (PM2) is biased in the linear region by adjusting the impedance values of the fourth PMOS transistor (PM4), the fourth NMOS transistor (NM4) and the second resistor (R2).
5. The power amplifier of high linearity as claimed in claim 1 or 2, wherein the first bias voltage generating circuit (201) comprises a third PMOS transistor (PM3), a third NMOS (NM3) transistor and a first resistor (R1);
the second bias voltage generating circuit (202) comprises a fourth PMOS transistor (PM4), a fourth NMOS transistor (NM4) and a second resistor (R2);
the source electrode of the third PMOS tube (PM3) is connected with the source electrode of the first PMOS tube (PM 1);
the drain electrode of the third PMOS tube (PM3) is connected with the gate electrode of the first PMOS tube (PM 1);
the source electrode of the third NMOS tube (NM3) is connected with the source electrode of the first NMOS tube (NM 1);
the drain electrode of the third NMOS tube (NM3) is connected with the grid electrode of the first NMOS tube (NM 1);
the source electrode of the fourth PMOS tube (PM3) is connected with the source electrode of the second PMOS tube (PM 1);
the drain electrode of the fourth PMOS tube (PM3) is connected with the gate electrode of the second PMOS tube (PM 1);
the source electrode of the fourth NMOS transistor (NM3) is connected with the source electrode of the second NMOS transistor (NM 1);
the drain electrode of the fourth NMOS tube (NM3) is connected with the grid electrode of the second NMOS tube (NM 1).
6. The power amplifier of claim 2, wherein the first NMOS transistor (NM1) and the second NMOS transistor (NM2) always operate in saturation.
7. The high linearity power amplifier of claim 2, wherein when the input voltage of the first PMOS transistor (PM1) is greater than the threshold voltage of the first PMOS transistor (PM1), the first PMOS transistor (PM1) is used for compensating the gain of the first NMOS transistor (NM 1);
when the input voltage of the second PMOS tube (PM2) is greater than the threshold voltage of the second PMOS tube (PM2), the second PMOS tube (PM2) is used for compensating the gain of the second NMOS tube (NM 2).
8. The power amplifier of high linearity as claimed in claim 1, wherein the input voltages of the first push-pull power amplifying circuit (101) and the second push-pull power amplifying circuit (102) are opposite in polarity and equal in magnitude;
the output end voltages of the first push-pull power amplification circuit (101) and the second push-pull power amplification circuit (102) are opposite in polarity and equal in size.
9. The power amplifier of claim 1, wherein the first derivative and the second derivative of the transconductance of the first PMOS transistor (PM1), the second PMOS transistor (PM2), the first NMOS transistor (NM1), and the second NMOS transistor (NM2) are added to each other at large signals, so that the first derivative and the second derivative of the transconductance of the power amplifier approach to 0, and the first PMOS transistor (PM1) and the second PMOS transistor (PM2) are biased in a linear region.
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