CN110785830B - Soi晶圆的制造方法 - Google Patents

Soi晶圆的制造方法 Download PDF

Info

Publication number
CN110785830B
CN110785830B CN201880038871.9A CN201880038871A CN110785830B CN 110785830 B CN110785830 B CN 110785830B CN 201880038871 A CN201880038871 A CN 201880038871A CN 110785830 B CN110785830 B CN 110785830B
Authority
CN
China
Prior art keywords
soi
oxidation
wafer
film thickness
thickness distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880038871.9A
Other languages
English (en)
Other versions
CN110785830A (zh
Inventor
阿贺浩司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of CN110785830A publication Critical patent/CN110785830A/zh
Application granted granted Critical
Publication of CN110785830B publication Critical patent/CN110785830B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02334—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment in-situ cleaning after layer formation, e.g. removing process residues
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68764—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本发明涉及一种SOI晶圆的制造方法，其具有对SOI晶圆实施牺牲氧化处理而对SOI层进行减厚调节的工序，其特征在于，实施牺牲氧化处理的SOI晶圆具有单侧流动形状的膜厚分布，通过使用立式热处理炉，组合非旋转氧化及旋转氧化进行牺牲氧化处理的热氧化，由此以抵消SOI层的单侧流动形状的膜厚分布的方式，在SOI层的表面形成具有单侧流动形状的膜厚分布的热氧化膜，去除该形成的热氧化膜，从而制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆。由此，提供一种SOI晶圆的制造方法，其通过对具有单侧流动形状的SOI层膜厚分布的SOI晶圆实施牺牲氧化处理，使SOI晶圆具有单侧流动形状的膜厚分布被消除的SOI层。

Description

SOI晶圆的制造方法
技术领域
本发明涉及一种SOI晶圆的制造方法。
背景技术
利用离子注入剥离法制作SOI晶圆时，为了维持刚剥离后的SOI层的膜厚均匀性并降低剥离面的表面粗糙度，正在进行通过进行高温热处理来代替研磨以改善表面粗糙度的平坦化热处理。
平坦化热处理后，通常会进行用于将SOI层调节至期望的膜厚的牺牲氧化处理，但在该牺牲氧化中，作为可得到面内分布优异的氧化膜厚的热氧化炉，通常使用能够边旋转晶圆边进行热氧化的立式热处理炉。
与利用研磨(接触抛光)的平坦化相比，改善表面粗糙度的平坦化热处理的最大的优点为不使SOI层的膜厚均匀性变差，但是由于平坦化热处理也会略微地进行SOI层的蚀刻，因此与刚剥离后的膜厚均匀性相比，不可避免地会出现一定程度的恶化。
当刚进行平坦化热处理后的SOI层的膜厚分布为同心圆形状时，通过适用专利文献1中记载的方法，能够通过平坦化热处理后的牺牲氧化处理改善SOI层的膜厚分布。
专利文献1中记载了，对于同心圆形状的SOI膜厚分布，通过使用具有晶圆旋转结构的间歇式热处理炉，在升温中或降温中的至少一者下进行牺牲氧化处理中的热氧化，从而形成同心圆形状的氧化膜厚分布，由此抵消SOI膜厚分布，从而改善SOI膜厚分布。
此外，专利文献2中记载了，测定SOI层的膜厚分布，基于预先求出的薄膜化工序中的面内加工余量分布，为了在薄膜化工序后改善SOI层的膜厚分布，在以使晶圆旋转而进行了配置的状态下进行薄膜化。其中，作为对象的薄膜化工序为SC-1清洗。
此外，专利文献3中记载了，在对SOI层进行热氧化处理前，测定面内膜厚分布，基于该测定值，以使SOI层膜厚中较厚的区域的SOI层的面内温度高于较薄的区域的方式，调节灯输出，进行热氧化处理。
现有技术文献
专利文献
专利文献1：日本特开2013-125909号公报
专利文献2：日本特开2016-66692号公报
专利文献3：日本特开2007-242972号公报
发明内容
本发明要解决的技术问题
如上所述，刚进行平坦化热处理后的SOI层的膜厚分布为同心圆形状时，通过适用专利文献1中记载的方法，能够通过平坦化热处理后的牺牲氧化处理来改善SOI层的膜厚分布。
另一方面，发现了根据进行平坦化热处理的热处理炉的温度分布特性等，有时平坦化热处理后的SOI层的膜厚分布会成为单侧流动的形状(SOI膜厚以特定的方向倾斜的形状)。
由于即使进行使用具有旋转结构的立式热处理炉而使晶圆旋转从而在具有这样的单侧流动形状的膜厚分布的SOI层上形成面内分布优异的氧化膜的牺牲氧化处理，SOI层的单侧流动形状也维持原样，因此无法通过牺牲氧化处理改善SOI层的膜厚分布。
本发明鉴于上述情况而完成，本发明的目的在于提供一种SOI晶圆的制造方法，其通过对具有单侧流动形状的SOI层膜厚分布的SOI晶圆实施牺牲氧化处理而使SOI晶圆具有单侧流动形状的膜厚分布被消除的SOI层。
解决技术问题的技术手段
为了解决上述技术问题，本发明提供一种SOI晶圆的制造方法，其特征在于，其具有通过对SOI晶圆实施将SOI层表面热氧化并去除所形成的热氧化膜的牺牲氧化处理，从而对所述SOI晶圆的SOI层进行减厚调节的工序，该方法中：
将实施所述牺牲氧化处理的SOI晶圆设为所述SOI层具有以特定的方向倾斜的单侧流动形状的膜厚分布的晶圆，
通过使用具有使晶圆表面以水平方向旋转的结构的立式热处理炉，组合不旋转所述SOI晶圆而进行热氧化的非旋转氧化和边旋转所述SOI晶圆边进行热氧化的旋转氧化，进行所述牺牲氧化处理中的热氧化，由此，以抵消所述SOI层的单侧流动形状的膜厚分布的方式，在所述SOI层的表面形成具有单侧流动形状的氧化膜厚分布的热氧化膜，
去除该形成的热氧化膜，从而制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆。
根据这样的SOI晶圆的制造方法，能够通过牺牲氧化处理中的热氧化，形成与SOI层的单侧流动形状一致的单侧流动形状的氧化膜厚分布，其结果，能够抵消SOI层的单侧流动形状的膜厚分布，能够制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆。
此外，此时，作为所述牺牲热氧化处理中的热氧化，优选在进行所述非旋转氧化后进行所述旋转氧化。
如此，通过在进行非旋转氧化后切换成旋转氧化，能够简便地形成与SOI层的单侧流动形状一致的单侧流动形状的氧化膜厚分布，因而优选。
此外，此时，通过施加用于使利用离子注入剥离法而在离子注入层剥离的SOI层表面平坦化的平坦化热处理，能够制作所述SOI层具有单侧流动形状的膜厚分布的所述SOI晶圆。
如此，在进行基于离子注入剥离法的剥离后施加平坦化热处理，其结果，能够将SOI层成为单侧流动形状的膜厚分布的SOI晶圆用作实施牺牲氧化处理的SOI晶圆。
发明效果
根据本发明的SOI晶圆的制造方法，通过组合非旋转氧化和旋转氧化进行牺牲氧化处理中的热氧化，能够形成与SOI层的单侧流动形状一致的单侧流动形状的氧化膜厚分布，其结果，能够抵消SOI层膜厚分布，从而能够制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆。
附图说明
图1为示出本发明的SOI晶圆的制造方法的一个例子的流程图。
图2为示出本发明中实施牺牲氧化处理且SOI层具有以特定的方向倾斜的单侧流动形状的膜厚分布的SOI晶圆的一个例子的图。
图3为示出将图2所示的SOI晶圆用作实施牺牲氧化处理的SOI晶圆时的本发明的SOI晶圆的制造方法中的各工序后的A-A’截面图。
图4为示出在实施例、比较例中所使用的立式热处理炉中，仅利用非旋转氧化而在监测晶圆上形成的氧化膜厚分布的图。
具体实施方式
如上所述，存在以下问题：由于即使进行使用具有旋转结构的立式热处理炉而使晶圆旋转从而在具有单侧流动形状的膜厚分布的SOI层上形成面内分布优异的氧化膜的牺牲氧化处理，SOI层的单侧流动形状也维持原样，因此无法通过牺牲氧化处理改善SOI层的膜厚分布。
本申请的发明人为了解决上述问题而反复进行努力研究，结果发现，使用具有晶圆旋转结构的立式热处理炉对具有单侧流动形状的SOI层膜厚分布的SOI晶圆进行牺牲氧化时，通过组合不旋转SOI晶圆而进行热氧化的非旋转氧化和边旋转SOI晶圆边进行热氧化的旋转氧化进行牺牲氧化，在SOI层的表面形成具有抵消SOI层膜厚分布的单侧流动形状的氧化膜厚分布的热氧化膜，由此能够在牺牲氧化处理后，制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆，从而完成了本发明。
即，本发明提供一种SOI晶圆的制造方法，其特征在于，其具有对SOI晶圆实施将SOI层表面热氧化并去除所形成的热氧化膜的牺牲氧化处理，从而对所述SOI晶圆的SOI层进行减厚调节的工序，该方法中：
将实施所述牺牲氧化处理的SOI晶圆设为所述SOI层具有以特定的方向倾斜的单侧流动形状的膜厚分布的晶圆，
通过使用具有使晶圆表面以水平方向旋转的结构的立式热处理炉，组合不旋转所述SOI晶圆旋转而进行热氧化的非旋转氧化和边旋转所述SOI晶圆旋转边进行热氧化的旋转氧化，进行所述牺牲氧化处理中的热氧化，
由此，以抵消所述SOI层的单侧流动形状的膜厚分布的方式，在该SOI层的表面形成具有单侧流动形状的氧化膜厚分布的热氧化膜，
去除该形成的热氧化膜，从而制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆。
以下，对本发明的SOI晶圆的制造方法进行说明。图1示出了表示本发明的SOI晶圆的制造方法的一个例子的流程图。
本发明中，首先，准备SOI层2具有以特定的方向倾斜的单侧流动形状的膜厚分布的SOI晶圆1作为实施牺牲氧化处理的SOI晶圆(图1的(A)、图3的(A))。例如，可使用具有具有图2所示的等厚线的单侧流动形状的SOI层膜厚分布的SOI晶圆1。另外，图3为使用图2所示的SOI晶圆1时的各工序后的A-A’截面图。
作为具有这样的单侧流动形状的膜厚分布的SOI层2的SOI晶圆1的制作方法没有特别限定，通过高温长时间的平坦化热处理，使通过离子注入剥离法进行了剥离的SOI晶圆的剥离面平坦化，由此可使用SOI层成为单侧流动形状的膜厚分布的SOI晶圆。
作为进行这样的平坦化热处理的高温热处理炉，能够使用不具备晶圆旋转结构的热处理炉。由于根据炉内温度分布及热处理条件等条件，平坦化热处理后的SOI层成为单侧流动形状，因此预先通过实验把握形成单侧流动形状的SOI层膜厚分布的热处理炉及热处理条件。
此外，在进行在离子注入层的剥离后、平坦化热处理前，多数情况下会去除离子注入层的损伤并以提高结合强度为目的进行作为结合热处理的牺牲氧化。此时，根据离子注入时的注入角度(偏离角)等的注入条件，有时刚进行剥离后的SOI层也会成为单侧流动形状的膜厚分布。此时，能够将本发明中的牺牲氧化处理适用于所述作为结合热处理的牺牲氧化。
此外，即使在通过研磨(接触抛光)进行平坦化时，根据研磨条件，有时刚完成研磨后的SOI层也会成为单侧流动形状的膜厚分布。此时，能够将研磨后的SOI晶圆用作SOI层2成为单侧流动形状的膜厚分布的SOI晶圆1。
接着，对SOI层2具有以特定方向倾斜的单侧流动形状的膜厚分布的SOI晶圆1进行牺牲氧化处理。牺牲氧化处理通过进行热氧化(图1的(B))并去除热氧化膜(图1的(C))而进行。
本发明中的牺牲氧化处理的热氧化(图1的(B))使用具有晶圆旋转结构的立式热处理炉而进行。
在本发明中，预先利用具有所使用的旋转结构的氧化炉，使用监测晶圆进行非旋转氧化，并测定由非旋转氧化生产的氧化膜厚分布，由此能够正确地形成具有与SOI层的单侧流动形状一致的单侧流动形状的氧化膜厚分布的热氧化膜。
本发明中的牺牲氧化处理的热氧化通过组合不旋转SOI晶圆而进行热氧化的非旋转氧化和边旋转SOI晶圆边进行热氧化的旋转氧化而进行，由此能够在SOI层2’的表面形成具有单侧流动形状的氧化膜厚分布的热氧化膜3(图1的(B)、图3的(B))。另外，非旋转氧化和旋转氧化的顺序没有特别限定，但最初进行非旋转氧化，然后切换至旋转氧化的方法比较简便，因而优选。
最初进行非旋转氧化时，预先测定实施牺牲氧化处理的SOI晶圆(具有单侧流动形状的膜厚分布的SOI晶圆1)的SOI层2的膜厚分布，以使SOI层膜厚中最大的位置(最小的位置)与所述监测晶圆的氧化膜厚分布中最大的位置(最小的位置)一致的方式，旋转晶圆的放入方向后，将晶圆设置于立式热处理炉的晶舟。
将设置于晶舟的SOI晶圆投入至立式热处理炉(氧化炉)，通过非旋转进行规定时间的氧化，然后切换至旋转氧化进行规定时间的氧化。由非旋转氧化切换至旋转氧化的时间(即，非旋转氧化的氧化时间)，能够以使牺牲氧化处理后的SOI层的膜厚分布为最小的方式，考虑氧化前的SOI层膜厚分布，通过实验而求得。
此外，在本发明中，非旋转氧化和旋转氧化的顺序并没有特别限定，只要能把握非旋转氧化开始时的晶圆的停止位置，则可在进行旋转氧化后进行非旋转氧化，也可交替重复多次。
接着，通过去除所形成的热氧化膜3(图1的(C)、图3的(C))，制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆。关于热氧化膜的去除方法并没有特别限定，能够使用氢氟酸清洗等公知的方法。
即使氧化前的SOI层膜厚分布为一定程度大时，本发明对于进行用于抵消通过离子注入剥离法所形成的最大数为nm左右的面内范围(典型为1nm以下)的SOI层的偏差的牺牲氧化处理也特别有效。
另外，虽然在以高温长时间进行平坦化热处理的热处理炉中设置旋转结构时，可得到平坦化热处理后的SOI层为接近同心圆形状的SOI晶圆，但当为不具备旋转结构的进行高温长时间热处理的热处理炉时，不用担心因设置旋转结构而导致装置自身变贵，此外，不用担心因热处理管的变形等影响而容易发生故障等，因而优选。
对此，若为用于牺牲氧化处理的热氧化的立式热处理炉(氧化炉)，则由于通常较多情况下以小于1100℃、主要以1050℃以下进行热氧化，因此与平坦化热处理相比，热负荷小，在设置旋转结构时不会发生技术问题。
此外，即使在使用设置有旋转结构的热处理炉作为以高温长时间进行平坦化热处理的热处理炉时，根据炉内温度分布、旋转中心位置的错位或热处理条件等条件，也可能会略微地形成单侧流动形状的膜厚分布。即使在该情况下，也能适用本发明，且通过将非旋转氧化时间设置得较短，能够得到SOI层膜厚分布的校正效果。
实施例
以下，示出实施例及比较例，对本发明进行更具体的说明，但本发明并不受这些实施例的限定。
[实施例1]
＜具有单侧流动形状的SOI层膜厚分布的SOI晶圆的制作＞
以下述离子注入条件在下述键合晶圆(附有热氧化膜)的表面形成离子注入层，隔着热氧化膜与下述衬底晶圆的表面贴合后，以下述条件进行剥离热处理，在离子注入层剥离键合晶圆，由此制作具有SOI层的SOI晶圆，以下述条件对该SOI晶圆实施结合热处理及平坦化热处理，由此制作SOI晶圆。
[键合晶圆]
单晶硅晶圆，直径300mm，＜100＞，p型，10Ωcm
附有25nm的热氧化膜
[衬底晶圆]
单晶硅晶圆，直径300mm，＜100＞、
[离子注入条件]
H+离子，50keV，6×1016/cm2
[剥离热处理]500℃，30分钟，氮气氛围
[结合热处理]1050℃，1小时，氧化性氛围
[平坦化处理]1200℃，3小时，H2气体100％
平坦化热处理后的SOI膜厚分布为如图2所示的单侧流动分布(切口朝下，膜厚由左方向至右方向变薄的分布)，膜厚范围(Max-Min)为0.7nm。
＜进行牺牲氧化的立式热处理炉的特性确认＞
对上述SOI晶圆进行的牺牲氧化条件(1000℃，加热合成氧化(pyrogenicoxidation)、形成约410nm的氧化膜)中，使用监测晶圆(单晶硅晶圆，直径300mm，＜100＞，p型，10Ωcm)，测定仅以非旋转氧化形成的氧化膜厚分布。其结果，确认到氧化膜厚范围为约5nm，其分布形状为如图4所示的氧化膜由炉的跟前侧至炉内深处方向变薄的单侧流动形状。
＜牺牲氧化的实施：非旋转氧化+旋转氧化＞
以使SOI晶圆的SOI膜厚的最厚的位置位于炉的跟前侧的方式将其设置于晶舟上，在该状态下进行30分钟的非旋转氧化(1000℃，加热合成氧化)后，立刻以1rpm的转速旋转晶舟，以该状态进行2小时的旋转氧化(1000℃，加热合成氧化)。将完成牺牲氧化后的SOI晶圆浸渍于稀氢氟酸，从而去除SOI层表面的氧化膜后，测定SOI层膜厚分布。其结果，SOI层的单侧流动形状的膜厚分布被消除，且膜厚范围(Max-Min)被改善至0.5nm。
[比较例1]
除了仅以旋转氧化(1rpm)进行牺牲氧化以外，以与实施例1相同的条件进行牺牲氧化处理，并测定SOI层膜厚分布。其结果，SOI层的单侧流动形状的膜厚分布未被消除，且膜厚范围(Max-Min)变差，为0.9nm。
[实施例2、比较例2～4]
除了将牺牲氧化中的非旋转氧化及旋转氧化(1rpm)的时间设定为如表1所示以外，以与实施例1相同的条件进行牺牲氧化处理，并测定SOI层膜厚分布。在实施例2中，SOI层的单侧流动形状，与牺牲氧化处理前相比，消除得以进行，成为几乎均匀的形状，且膜厚范围(Max-Min)也被改善至0.6nm。此外，在比较例2～4中，超出SOI层的单侧流动形状的膜厚分布的抵消，单侧流动形状逆向倾斜，且膜厚范围(Max-Min)也变差。
将实施例1、2及比较例1～4所制造的SOI晶圆的膜厚范围及SOI层膜厚分布形状归纳并示于表1。
[表1]
比较例1 实施例2 实施例1 比较例2 比较例3 比较例4
非旋转氧化时间(分) 0 15 30 45 60 150
旋转氧化时间(分) 150 135 120 105 90 0
SOI膜厚范围 0.9nm 0.6nm 0.5nm 0.7nm 1.2nm 2.5nm
SOI膜厚分布形状 单侧流动 均匀 均匀 单侧流动 单侧流动 单侧流动
另外，本发明并不限定于上述实施方式。上述实施例为例示，任何与本发明的权利要求书所记载的技术构思具有实质相同的构成并发挥同样的作用效果的技术方案均包含于本发明的技术范围内。

Claims (4)

1.一种SOI晶圆的制造方法，其特征在于，具有对SOI晶圆实施将SOI层表面热氧化并去除所形成的热氧化膜的牺牲氧化处理，从而对所述SOI晶圆的SOI层进行减厚调节的工序，该方法中：
将实施所述牺牲氧化处理的SOI晶圆设为所述SOI层具有以特定的方向倾斜的单侧流动形状的膜厚分布的晶圆，
预先使用具有使晶圆表面以水平方向旋转的结构的立式热处理炉，使用监测晶圆进行非旋转氧化，并测定由非旋转氧化产生的氧化膜厚分布，
通过使用具有使所述晶圆表面以水平方向旋转的结构的立式热处理炉，组合不旋转所述SOI晶圆而进行热氧化的非旋转氧化和边旋转所述SOI晶圆边进行热氧化的旋转氧化，进行所述牺牲氧化处理中的热氧化，
由此，以抵消所述SOI层的单侧流动形状的膜厚分布的方式，在所述SOI层的表面形成具有单侧流动形状的氧化膜厚分布的热氧化膜，
去除该形成的热氧化膜，从而制造具有单侧流动形状的膜厚分布被消除的SOI层的SOI晶圆。
2.根据权利要求1所述的SOI晶圆的制造方法，其特征在于，作为所述牺牲氧化处理中的热氧化，在进行所述非旋转氧化后进行所述旋转氧化。
3.根据权利要求1或2所述的SOI晶圆的制造方法，其特征在于，通过施加用于使利用离子注入剥离法而在离子注入层剥离的SOI层表面平坦化的平坦化热处理，制作所述SOI层具有单侧流动形状的膜厚分布的所述SOI晶圆。
4.根据权利要求1或2所述的SOI晶圆的制造方法，其特征在于，利用使用了不具备晶圆旋转结构的热处理炉的平坦化热处理，形成所述SOI层具有以特定的方向倾斜的单侧流动形状的膜厚分布的所述SOI晶圆。
CN201880038871.9A 2017-06-23 2018-05-30 Soi晶圆的制造方法 Active CN110785830B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2017123117A JP6747386B2 (ja) 2017-06-23 2017-06-23 Ｓｏｉウェーハの製造方法
JP2017-123117 2017-06-23
PCT/JP2018/020640 WO2018235548A1 (ja) 2017-06-23 2018-05-30 Ｓｏｉウェーハの製造方法

Publications (2)

Publication Number Publication Date
CN110785830A CN110785830A (zh) 2020-02-11
CN110785830B true CN110785830B (zh) 2023-09-22

Family

ID=64737470

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880038871.9A Active CN110785830B (zh) 2017-06-23 2018-05-30 Soi晶圆的制造方法

Country Status (8)

Country Link
US (1) US11244851B2 (zh)
EP (1) EP3644346A4 (zh)
JP (1) JP6747386B2 (zh)
KR (1) KR102554190B1 (zh)
CN (1) CN110785830B (zh)
SG (1) SG11201911688XA (zh)
TW (1) TWI774781B (zh)
WO (1) WO2018235548A1 (zh)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242972A (ja) * 2006-03-09 2007-09-20 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750234A (ja) * 1993-08-04 1995-02-21 Komatsu Electron Metals Co Ltd 半導体ウェーハ製造装置および製造方法
US20040087042A1 (en) * 2002-08-12 2004-05-06 Bruno Ghyselen Method and apparatus for adjusting the thickness of a layer of semiconductor material
AU2003263391A1 (en) * 2002-08-12 2004-02-25 S.O.I.Tec Silicon On Insulator Technologies A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine
JP2007123643A (ja) 2005-10-31 2007-05-17 Matsushita Electric Ind Co Ltd 成膜装置、成膜方法、成膜装置のモニタリングプログラムおよびその記録媒体
JP2010153809A (ja) 2008-11-26 2010-07-08 Sumco Corp シリコンウェーハの表面に形成された所定の膜厚を有する層の膜厚分布を均一化する処理方法及びシリコンウェーハの厚み分布を均一化する処理方法
JP5927894B2 (ja) 2011-12-15 2016-06-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR3007891B1 (fr) 2013-06-28 2016-11-25 Soitec Silicon On Insulator Procede de fabrication d'une structure composite
JP6107709B2 (ja) * 2014-03-10 2017-04-05 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6086105B2 (ja) * 2014-09-24 2017-03-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242972A (ja) * 2006-03-09 2007-09-20 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法

Also Published As

Publication number Publication date
JP6747386B2 (ja) 2020-08-26
US11244851B2 (en) 2022-02-08
TWI774781B (zh) 2022-08-21
KR102554190B1 (ko) 2023-07-12
EP3644346A1 (en) 2020-04-29
WO2018235548A1 (ja) 2018-12-27
SG11201911688XA (en) 2020-01-30
EP3644346A4 (en) 2021-03-17
US20200111701A1 (en) 2020-04-09
KR20200019142A (ko) 2020-02-21
TW201905962A (zh) 2019-02-01
JP2019009257A (ja) 2019-01-17
CN110785830A (zh) 2020-02-11

Similar Documents

Publication Publication Date Title
JP5927894B2 (ja) Ｓｏｉウェーハの製造方法
KR102361311B1 (ko) 접합웨이퍼의 제조방법
TWI573173B (zh) Method for manufacturing conformable SOI wafers
EP3309819B1 (en) Bonded soi wafer manufacturing method
JPWO2005024925A1 (ja) Ｓｏｉウェーハの作製方法
EP2717294B1 (en) Method for manufacturing bonded wafer
CN109690733B (zh) 贴合式soi晶圆的制造方法
JP2016201454A (ja) Ｓｏｉウェーハの製造方法
CN110785830B (zh) Soi晶圆的制造方法
JP2010153488A (ja) Ｓｏｉウエハの製造方法およびｓｏｉウエハ
JP2007242972A (ja) Ｓｏｉウェーハの製造方法
KR102241303B1 (ko) Soi웨이퍼의 제조방법
JP2006013179A (ja) Ｓｏｉウェーハの製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant