CN110676223A - 封装件和形成封装件的方法 - Google Patents

封装件和形成封装件的方法 Download PDF

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CN110676223A
CN110676223A CN201910454567.9A CN201910454567A CN110676223A CN 110676223 A CN110676223 A CN 110676223A CN 201910454567 A CN201910454567 A CN 201910454567A CN 110676223 A CN110676223 A CN 110676223A
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dies
dummy
die
reconstituted wafer
functional
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CN110676223B (zh
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余振华
郭庭豪
蔡豪益
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括将多个功能管芯放置在载体上、将多个伪管芯放置在载体上，将多个功能管芯和多个伪管芯封装在密封剂中，以及在多个功能管芯上形成再分配线并使多个功能管芯互连。再分配线、多个功能管芯、多个伪管芯和密封剂组合形成重建晶圆。多个功能管芯位于重建晶圆的中心区域中，且多个伪管芯位于重建晶圆的外围区域中，同时外围区域环绕中心区域。重建晶圆从载体上脱粘。重建晶圆接合至封装组件，封装组件选自基本上由中介层、封装衬底、印刷电路板、热模块及其组合组成的群组。本发明的实施例还涉及用于减少封装件中的翘曲的伪管芯。本发明的实施例还涉及封装件和形成封装件的方法。

Description

封装件和形成封装件的方法
技术领域
本发明的实施例涉及封装件和形成封装件的方法，更具体地，涉及用于减少封装件中的翘曲的伪管芯。
背景技术
在三维集成电路的形成中，管芯通常粘合在半导体晶圆上。粘合工艺通常包括选择已知良好的管芯(顶部管芯)，和使用倒装管芯粘合将顶部管芯接合至底部晶圆中的底部芯片。每个底部芯片可接合至一个或多个顶部管芯。在粘合之后，将底部填充剂分配到顶部管芯和底部芯片之间的空间中，并将模塑料模塑至顶部管芯和底部晶圆上。在模塑料模塑后，由于模塑料的收缩，封装可能会发生翘曲。因此，可产生应力并将其施加到底部晶圆和上面的顶部管芯。
当封装变得越来越大时，情况进一步恶化。随着封装尺寸的增加，封装件的一个点到另一个点的距离增加，这导致应力可累积的距离增加，导致应力增加并因此增加翘曲出现。
在常规封装件的形成中，使用伪管芯来减少翘曲，并将伪管芯和功能管芯模塑在一起。在形成连接至功能管芯的RDL之后，将重建晶圆锯切成多个封装。移除靠近重建晶圆边缘的伪管芯。得到的封装可包括或不包括伪管芯。得到的封装件中的伪(如果有的话)与功能管芯并排放置。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：将多个功能管芯放置在载体上；将多个伪管芯放置在所述载体上；将所述多个功能管芯和所述多个伪管芯封装在密封剂中；在所述多个功能管芯上形成再分配线，所述再分配线互连所述多个功能管芯，其中所述再分配线、所述多个功能管芯、所述多个伪管芯和所述密封剂组合形成重建晶圆，其中所述多个功能管芯位于所述重建晶圆的中心区域中，且所述多个伪管芯位于所述重建晶圆的外围区域中，同时所述外围区域环绕所述中心区域；将所述重建晶圆从所述载体上脱粘；以及将所述重建晶圆接合至封装组件，所述封装组件选自由中介层、封装衬底、印刷电路板、热模块及其组合组成的群组。
本发明的另一实施例提供了一种形成封装件的方法，包括：将多个逻辑管芯放置在载体上；将多个输入-输出(IO)管芯放置在所述载体上；将多个伪管芯放置在所述载体上，其中所述多个伪管芯分布在所述多个逻辑芯片和所述多个输入-输出芯片所在的区域周围；将所述多个逻辑管芯、所述多个输入-输出管芯和所述多个伪管芯封装在密封剂中；在所述多个逻辑管芯和所述多个输入-输出管芯上形成再分配线，所述再分配线电耦合至所述多个逻辑管芯和所述多个输入-输出管芯以形成重建晶圆，所述重建晶圆包括所述多个逻辑管芯、所述多个输入-输出管芯、所述多个伪管芯、所述密封剂和所述再分配线；以及将所述重建晶圆从所述载体上脱粘。
本发明的又一实施例提供了一种封装件，包括：重建晶圆，包括：多个伪管芯；多个功能管芯，所述多个功能管芯位于所述封装件的中心区域中，其中对准环绕所述多个功能管芯的环来分配所述多个伪管芯；密封剂，所述密封剂中封装所述多个伪管芯和所述多个功能管芯；以及多个再分配线(RDL)，所述多个再分配线位于所述多个功能管芯上，其中所述多个再分配线将所述封装件中的所有功能管芯互连至集成系统中。
附图说明
当与附图一起阅读时，从下面的详细描述可以最好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，各个部件没有被按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以被任意增加或减少。
图1至图9示出了根据一些实施例的封装件形成中的中间阶段的截面图。
图10示出了根据一些实施例的封装件的截面图。
图11A和图11B示出了根据一些实施例的包括中心区域和外围区域的重建晶圆的顶视图。
图12A、图12B和图13至图23是根据一些实施例的一些重建晶圆的顶视图。
图24示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开为实现本发明的不同功能提供了诸多不同的实施例或者实例。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。此外，本发明可能会在各种实例中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间关系术语来描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语意欲包括使用或操作过程中的器件的不同方位。该装置可以以其它方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可同样地作相应地解释。
根据一些实施例所述提供了一种封装及其形成方法。根据一些实施例所述示出了形成封装件的中间阶段。讨论了一些实施例的一些变型。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。根据本发明公开的一些实施例，伪管芯放置在重建晶圆的外围区域中，且伪管芯可围绕功能管芯。
图1至图9示出了根据本发明公开的一些实施例所述，封装件形成中的中间阶段的截面图。图1至图9所示的工艺也在工艺流程200中示意性地反映，如图24所示。
图1示出了载体20和在载体20上形成的离型膜22。载体20可以是玻璃载体、陶瓷载体等。载体20可具有圆形顶视图形状，并可具有典型硅晶圆的尺寸。例如，载体20可具有8英寸直径、12英寸直径等。离型膜22可由基于聚合物的材料(比如，光-热-转换(LTHC)材料)形成，其可与载体20一起从将在后续工艺中形成的上覆结构中移除。根据本发明公开的一些实施例，离型膜22由环氧基热释放材料形成。离型膜22上形成管芯附着膜(DAF)24。DAF 24是粘合膜，并可进行涂覆或层压。
图1还示出了封装组件26(包括26A和26B)在载体20上的放置。相应的工艺被示为图24中所示的工艺流程中的工艺202。根据本发明公开的一些实施例，封装组件26包括逻辑管芯(比如，计算管芯)、存储管芯(比如，动态随机存取存储器(DRAM)管芯或静态随机存取存储器(SRAM)管芯)、光子管芯、封装(包括已经封装件的器件管芯)、输入输出(IO)管芯、数字管芯、模拟管芯、表面安装无源器件、诸如高带宽存储器(HBM)块的管芯堆栈等。根据本发明公开的一些实施例，封装组件26A是逻辑管芯，而封装组件26B是存储管芯、IO管芯、集成无源器件(IPD)，比如，电容器(例如多层陶瓷电容器(MLCC))、电阻器、电感器等。在整个说明中，封装组件26被称为功能管芯26，因为它们具有电功能。功能管芯26可具有约20mm2至约900mmmm2的面积。这些面积的一些示例是100mm2和大约400mm2。
根据本发明公开的一些实施例，功能管芯26包括半导体衬底28，其可以是硅衬底、锗衬底、或由例如GaAs、InP、GaN、InGaAs、InAlAs等形成的III-V族化合物半导体衬底。诸如晶体管、二极管、电阻器、电容器、电感器等的集成电路器件(未示出)可形成在表面上或衬底28上。在介电层中形成的诸如金属线和通孔的互连结构形成在集成电路器件上并电耦合至集成电路器件。导电柱30形成在相应的功能管芯26的表面处，并通过互连结构电耦合至功能管芯26中的集成电路器件。根据本发明公开的一些实施例，诸如焊料、铝等的相对柔软的导电材料用于在导电柱30上形成导电层33。导电层33用于探测功能管芯26，以确保功能管芯26没有缺陷。可在从相应晶圆分割功能管芯26之前执行探测。由于导电层33比下面的金属柱30更软，所以由于探测器件的探测卡和导电层33之间的接触得到改善，探测则更容易。形成介电层32以覆盖导电层33和金属柱30。介电层32可由诸如聚酰亚胺、聚苯并恶唑(PBO)等聚合物形成。参考图11A、图11B、图12A、图12B和图13至图23详细讨论功能管芯26的布置。
图2示出了DAF 24上的伪管芯36的放置。相应的工艺被示为图24中所示的工艺流程中的工艺204。伪管芯36不具有电功能，并不与功能管芯26电连接。伪管芯36可由导电材料形成，比如，金属或金属合金、半导体材料、介电材料等。伪管芯36的材料可具有小于随后分配的密封剂38(图3)的CTE的热膨胀系数(CTE)。例如，伪管芯36可由硅、玻璃、石英、铜、SiC等形成。根据本发明公开的一些实施例，一个或多个伪管芯36整个由均质材料形成，该材料可选自上述材料。根据本发明公开的一些实施例，伪管芯36的高度小于功能管芯26的高度。根据本发明公开的一些实施例，伪管芯36的高度接近或大于功能管芯26的高度。例如，虚线表示可能存在或可能不存在的伪管芯36的部分。参考图11A、图11B、图12A、图12B和图13至图23详细讨论伪管芯36的布置。伪管芯36可具有约1mm2至约400mmmm2的面积。这些面积的一些示例是约9mm2和大约100mm2。功能管芯26之间的间距、伪管芯36之间的间距以及功能管芯26与相邻的伪管芯36之间的间距可在约20μm至约15mm的范围内。该间距的一些示例为约50um或约1mm。
接下来，参考图3，密封剂38被封装(有时称为模制)在功能管芯26和伪管芯36上。相应的工艺被示为图24中所示的工艺流程中的工艺206。密封剂38填充相邻功能管芯26和伪管芯36之间的间隙，并还可覆盖组件功能管芯26和伪管芯36。密封剂38可包括模塑料、模塑底部填料等。密封剂38可包括基础材料，该材料可以是聚合物、环氧树脂和/或树脂和混合在基础材料中的填料颗粒。填料颗粒可由二氧化硅、氧化铝等形成，并可具有球形形状。
在随后的步骤中，也如图3所示，执行平面化工艺，比如，化学机械抛光(CMP)工艺或机械研磨工艺。相应的工艺被示为图24中所示的工艺流程中的工艺208。通过平坦化工艺降低密封剂38的顶表面，直到露出金属柱30。由于平坦化，所以金属柱30的顶表面基本上与密封剂38的顶表面共面。根据本发明公开的一些实施例，伪管芯36的顶表面低于密封剂38的顶表面，因此在平坦化工艺之后，密封剂38的一些部分覆盖伪管芯36。可在平坦化工艺中去除导电层33(图2)，或者可留下导电层33的一些底部来覆盖金属柱30。根据本发明公开的一些实施例，伪管芯36的顶部也被抛光，并在平坦化工艺之后，伪管芯36的顶表面与密封剂38的顶表面共面。根据又一些实施例，一些伪管芯36具有与密封剂38的顶表面共面的表面，且一些其他伪管芯36具有低于密封剂38的顶表面的顶表面。
图4至图7示出了正侧再分配线(RDL)和相应的介电层的形成。参考图4，形成了介电层40。相应的工艺被示为图24中所示的工艺流程中的工艺210。根据本发明公开的一些实施例，介电层40由诸如PBO、聚酰亚胺等的光敏聚合物形成。根据本发明公开的又一些实施例，介电层40由诸如氮化硅、氧化硅等的无机材料形成。例如，使用光刻工艺图案化介电层40，从而形成开口42。通过开口42露出功能管芯26的金属柱30。
形成RDL以电连接至金属柱30。相应的工艺也被示为图24中所示的工艺流程中的工艺210。根据本发明公开的一些实施例，如图5所示，形成覆盖金属种子层44，其包括延伸至开口42中的一些部分，以及介电层40上的一些其他部分。金属种子层44可由钛、铜、镍等形成。根据本发明公开的一些实施例，金属种子层44包括钛层和钛层上的铜层。然后在金属种子层44上形成电镀掩模46，然后将其图案化以形成开口48，从而露出金属种子层44的一些部分。此外，开口42也露出至电镀掩模46中的开口48。电镀掩模46可由光致抗蚀剂形成。
参考图6，执行电镀工艺以形成RDL 50。电镀工艺可包括电化学电镀、化学镀等。电镀材料可包括金属或金属合金，其包括钛、铜、镍、铝、钨、其多层和/或其合金。例如，在随后的工艺中，在灰化工艺中去除电镀掩模46。然后蚀刻预先由电镀掩模46覆盖的覆盖铜种子层44的部分。金属种子层44的剩余部分被认为是RDL 50的一部分。RDL 50包括介电层40中的通孔部分和介电层40上的迹线(线)部分。迹线部分可包括窄部分和宽部分，其中宽部分可用作金属焊盘。
参考图7，根据本发明公开的一些实施例，形成更多的介电层和相应的RDL层。相应的工艺被示为图24中所示的工艺流程中的工艺212。应理解，取决于设计要求，介电层和RDL层的数量可比所示的更多或更少。根据本发明公开的一些实施例，使用选自用于形成介电层40的类似候选材料群组的材料来形成介电层52。形成RDL 54以电耦合至功能管芯26。可使用用于形成RDL 50的类似材料和方法来形成RDL 54。介电层40和52以及RDL 50和54组合形成互连结构56，该互连结构将封装件中的所有功能管芯26电互连至集成系统中。
图8示出了电连接器57的形成。根据本发明公开的一些实施例，电连接器57是焊接区域。根据又一些实施例，电连接器57包括金属柱和金属柱上方的焊接区域。电连接器57的形成可包括将焊球放置在顶部RDL层中的RDL焊盘的露出部分上，然后回流该焊球以形成焊接区域。根据本发明公开的又一些实施例，电连接器57的形成包括执行电镀工艺以在金属柱上形成金属柱和焊接区域，然后回流电镀的焊接区域。在整个说明中，DAF 24上的部件组合称为封装组件58，该封装组件可以是重建晶圆58。
根据其他实施例，封装组件58可以是重建面板、重建衬底等。例如，在封装组件58的平面图中，封装组件58可具有圆形形状、矩形形状等。封装组件26可布置为重建面板或重建衬底中的阵列。
在随后的工艺中，重建晶圆58从载体20上卸下，例如，通过在离型膜22上投射光，并使光(该激光束)穿透透明载体20。相应的工艺被示为图24中所示的工艺流程中的工艺214。因此，分解离型膜22，并将重建晶圆58从载体20释放。可在清洁工艺中移除DAF 24。因此，重建晶圆58形成为分立的组件。
图9示出了封装件60的形成，其中结合了重建晶圆58。相应的工艺被示为图24中所示的工艺流程中的工艺216。根据本发明公开的一些实施例，从载体20脱粘的重建晶圆58在没有被锯切的情况下用在封装件60中，且载体20上的所有功能管芯26和伪管芯36(如图7中所示)保留在封装件60中。还可修整重建晶圆58，例如，通过去除一些没有功能管芯26、伪管芯36和RDL的边缘部分。例如，图12A示出了修整线71，其中修整了由虚线71标记的区域之外的重建晶圆58的外部部分。根据一些实施例，不修整重建晶圆58的至少一些边缘部分。图9示出了封装件60包括两个重建晶圆58作为示例。应理解，封装可包括一个或多于两个重建晶圆。此外，当具有多于一个重建晶圆58时，重建晶圆58可具有相同结构或不同结构。
根据本发明公开的一些实施例，多个封装组件62(包括但不限于封装、电压调节器模块、电源模块(两种更具体的封装类型)、IPD、IO连接器(比如用于封装件60的IO的插座)等的结构)接合至重建晶圆58。重建晶圆58可通过热界面材料(TIM)66附接至热模块64。螺钉68、螺栓69和加强件/支架70可用于将重建晶圆58固定至热模块64。可在重建晶圆58和热模块64中钻孔，使得螺栓69可穿过重建晶圆58和热模块64。热模块64可包括散热槽、散热器、制冷板等。当使用制冷板时，冷却剂可以是水、油等。
图10示出了封装72的形成，其中结合了重建晶圆58。根据本发明公开的一些实施例，重建晶圆58通过倒装芯片粘合与封装组件74粘合。封装组件74可以是封装衬底、中介层、印刷电路板等。封装组件62可接合至封装组件74。热模块64、重建晶圆58和封装组件74可通过螺钉68和螺栓69固定在一起。在图9和图10所示的结构中，螺栓69可穿过封装58而不穿过伪管芯36。替代地，一些螺栓69可穿过伪管芯36，如图9中的虚线所示，以表明其存在或不存在。类似地，图10中的螺栓69可或可不穿过伪管芯36。
封装件60(图9)和72(图10)可以是高性能计算(HPC)封装、人工智能(AI)服务器的加速器、用于数据中心应用的其他性能要求高的计算封装，或用于服务器的封装。
参考图11A、图11B、图12A、图12B和图13至图23讨论功能管芯26和伪管芯36的放置中的细节(如前述实施例中所讨论的)。重建晶圆58可以是大晶圆，其可具有大于约10000mm2的面积。重建晶圆58的面积也可在约10000mm2至约70686mm2的范围内。图11A和图11B示出了根据一些实施例所述，重建晶圆58的中心区域和外围区域。参考图11A，重建晶圆58具有矩形顶视图形状。重建晶圆58具有中心59。可绘制从中心59指向重建晶圆58的任何边缘或角落的箭头。如果箭头具有长度L1，则箭头与中心区域58A的外边界61相遇。从中心59到中心区域58A的边界61的距离L2将是L2，且比率L2/L1等于2/3。重建晶圆58中位于中心区域58A外部的的区域是外围区域58B。因此，外围区域58B环绕中心区域58A，中心区域58A和外围区域58B之间的界面显示为57。
图11B示出了当重建晶圆具有圆形顶视图形状时的中心区域58A和外围区域58B。中心区域58A具有半径R2，且重建晶圆58具有半径R1。比率R2/R1等于2/3。在图12A和图12B至图23中，示出了矩形或圆形57，其中矩形或圆形57内的区域是相应的重建晶圆58的中心区域，矩形或圆形57外的区域是相应的重建晶圆58的外围区域。
根据本发明公开的一些实施例，如图12A、图12B和图13至图23所示，伪管芯36主要放置在重建晶圆58的外围区域58B中。中心区域58A可没有伪管芯36，或可包括一些伪管芯36。外围区域58B可没有功能管芯26，或可包括一些功能管芯26。假设在区域(中心区域58A或外围区域58B)中，所有功能管芯26的总顶视图面积等于F，且所有伪管芯36的总顶视图面等于D。在重建晶圆58的中心区域58A中，比率D/F可在约0和约1之间的范围内，并可在约0.25和约0.5之间的范围内。在重建晶圆58的外围区域58B中，比率F/D可在约0和约2/3之间的范围内，并可在约0.2和约2/3之间的范围内。例如，在外围区域中，比率F/D可在约0.3和约0.5之间的范围内。
应理解，载体20(图8)可具有与重建晶圆58的形状和尺寸相同(或类似)的形状和尺寸。因此，载体20也可被分成与重建晶圆58相同的中心区域和外围区域。在重建晶圆58从载体20拆卸之前，重建晶圆58的中心区域58A和外围区域58B分别与载体20的中心区域和外围区域重叠。
应理解，如图12A、图12B和图13至图23所示的重建晶圆58可以是已在封装件60(图9)或72(图10)中的晶圆，因此不再对重建晶圆58进行单片化和修整。如图12A、图12B和图13至图23所示的一些重建晶圆58可被修整(但不单片化)，如图12A中作为示例所示，然后用于形成封装件60(图9)或72(图10)。然而，将不会从重建晶圆58修整伪管芯和功能管芯。在如图12A、图12B和图13至图23所示的整个实施例中，伪管芯36可具有彼此相同或彼此不同的尺寸。而且，伪管芯36的放置可遵循某些图案，比如，阵列或其他重复图案，或可以随机布局放置。在外围区域58B中，伪管芯36可基本均匀地分布并具有基本均匀的密度。在图12A、图12B和图13至图23中，例如可能存在外围区域58B中示出的一些空位。这些空位可留下并用于螺栓的连接，或也可用于放置伪管芯。而且，一些螺栓69(参见图12A作为示例)可穿透伪管芯36，且一些其他螺栓69可穿透重建晶圆58而不穿透伪管芯36。替代地，没有一个螺栓69穿透伪管芯36。螺栓69通过伪管芯36的穿透(或非穿透)也适用于图12B和图13至图23中的实施例，尽管在这些图中未示出螺栓69。
在图12A、图12B和图13至图23中，管芯26A表示逻辑管芯，比如，计算管芯(例如用于数据计算)或其他类型的管芯，比如，无源管芯、光子管芯等，管芯26B表示IO管芯并可表示其他类型的管芯，比如，无源管芯、光子管芯等。IO管芯26B用于重建晶圆58和外部组件之间的数据输入和输出。根据本发明公开的一些实施例，IO管芯26B放置成与逻辑/计算管芯26A周围的环对准，以最小化计算管芯26A之间的布线距离，从而提高性能。多个逻辑/计算管芯26A可彼此相同，或可彼此不同。而且，并非标记出图12A、图12B和图13至图23中的所有管芯，而是可参考它们相应的阴影图案找到管芯是逻辑/计算管芯、IO管芯还是伪管芯。
图12A示出了根据一些实施例所述，重建晶圆58的顶视图，其中重建晶圆58具有圆形顶视图形状。根据本发明公开的一些实施例，如图12A所示，重建晶圆58的边缘是整圆。根据本发明公开的替代实施例，重建晶圆58具有一些修整的边缘部分，其中修整的部分由虚线71标记。根据替代实施例，重建晶圆58的所有边缘部分被修整，而没有修整功能管芯或伪管芯。因此，修整的重建晶圆58的新边缘更靠近伪管芯36。应理解，尽管使用图12A作为示例来讨论重建晶圆58的修整，但是上面讨论的修整(或不修整)方案也可应用于图12B和图13至图23中的实施例。圆圈57表示中心区域58A和外围区域58B之间的边界。根据本发明公开的一些实施例，所有伪管芯36位于外围区域58B中。大多数功能管芯26位于中心区域58A中，其余功能管芯26位于外围区域58B中。
图12B示出了根据一些实施例所述，重建晶圆58的顶视图，其中重建晶圆58具有矩形顶视图形状。矩形57表示中心区域58A和外围区域58B之间的边界。根据本发明公开的一些实施例，所有伪管芯36位于外围区域58B中。大多数功能管芯26位于中心区域58A中，其余功能管芯26位于外围区域58B中。而且，所有IO管芯26B可位于外围区域58B中。
图13、图14和图15示出了具有圆形顶视图形状的重建晶圆58。在图13中，包括所有计算管芯26A和IO管芯26B的所有功能管芯26位于中心区域58A中。一些伪管芯延伸到中心区域58A中，而其余部分位于外围区域58B中。在图14中，一些功能管芯26位于中心区域58A中，一些功能管芯26延伸进外围区域58B中。此外，根据本发明公开的一些实施例，一些IO管芯26B位于中心区域58A中，一些IO管芯26B位于外围区域58B中。所有伪管芯36位于外围区域58B中。在图15中，所有IO管芯26B位于外围区域58B中，一些逻辑/计算管芯26A位于中心区域58A中，其余的则位于外围区域58B中。所有伪管芯36位于外围区域58B中。
在图12A、图12B和图13至图15中，逻辑/计算管芯26A被布置为阵列，且没有IO管芯和伪管芯被插入到阵列中。图16至图23示出了作为群组布置的管芯(如图16中所示的GD)。群组GD可具有彼此相同的结构。每个群组GD可包括逻辑/计算管芯26A，并可包括或不包括其他类型的管芯，比如，IO管芯26B、伪管芯36、无源器件管芯和/或类似物。替代地，该设置可被认为是功能管芯26被分组，并可插入或不插入伪管芯36以填充群组之间的空间。同一群组中的逻辑/计算管芯26A之间的组内间距可等于或小于群组之间的组间间距。例如，图16示出了组内间距S1小于组间间距S2。图17示出了放置在功能管芯26之间的伪管芯36。在图17中，如果伪管芯36被认为是群组的一部分，则组内间距S1可等于组间间隔S2。替代地，如果伪管芯36不被认为是群组的一部分，则组内间距S1将小于组间间距，且伪管芯36插入在这些群组之间。
参考图16，每个群组GD包括逻辑/计算管芯26A，并不包括IO管芯和伪管芯。在图17所示的实施例中，每个群组GD包括逻辑/计算管芯26A，并不包括IO管芯。图18和图19分别示出了与图16和图17中类似的布置，除了图16和图17中的重建晶圆58具有圆形顶视图形状，而图18和图19中的重建晶圆58具有矩形顶视图形状。
图20示出了每个群组GD包括逻辑/计算管芯26A和IO管芯26B，且群组中没有伪管芯。如替代性所述，无伪管芯插入在群组之间。图21示出了每个群组GD包括逻辑/计算管芯26A、IO管芯26B和伪管芯36，或如替代性所述，如果伪管芯36不被视为群组的一部分，则伪管芯36插入在群组GD之间。图22和图23分别示出了与图20和图21中类似的布置，除了图20和图21中的重建晶圆58具有圆形顶视图形状，而图22和图23中的重建晶圆58具有矩形顶视图形状。
在上述实施例中，根据本发明公开的一些实施例讨论了一些工艺和部件。还可包括其他部件和工艺。例如，可包括测试结构以帮助3D封装或3D IC器件的验证测试。例如，测试结构可包括在再分配层中或在允许测试3D封装或3D IC、使用探针和/或探针卡的衬底上形成的测试焊盘。验证测试可在中间结构以及最终结构上执行。另外，本发明公开的结构和方法可与包含已知良好管芯的中间验证的测试方法结合使用，以提高产量并降低成本。
本发明公开的实施例具有一些有利特征。通过在重建晶圆中布置伪管芯，否则将被诸如模塑料的密封剂占据的空间则被伪管芯占据。由于伪管芯的CTE更接近功能管芯的CTE而不是密封剂，因此添加伪管芯可减小重建晶圆的应力和翘曲。此外，伪管芯包括围绕功能管芯的外围区域中的至少一些部分，在外围区域中添加伪管芯可提高封装工艺中的产量，因为重建晶圆可能具有翘曲，这导致重建晶圆的边缘部分在光刻过程中失去焦点。用伪管芯占据重建晶圆的边缘部分不仅减少了翘曲，而且还留下了一些未使用的去焦点的边缘部分，因此提高了产量。
根据本发明公开的一些实施例，一种方法包括将多个功能管芯放置在载体上、将多个伪管芯放置在所述载体上、将所述多个功能管芯和所述多个伪管芯封装在密封剂中，以及在所述多个功能管芯上形成再分配线并使其互连；其中所述再分配线、所述多个功能管芯、所述多个伪管芯和所述密封剂组合形成重建晶圆，其中所述多个功能管芯位于所述重建晶圆的中心区域中，且所述多个伪管芯位于所述重建晶圆的外围区域中，同时所述外围区域环绕所述中心区域；将所述重建晶圆从所述载体上脱粘，以及将所述重建晶圆接合至封装组件，所述封装组件选自基本上由中介层、封装衬底、印刷电路板、热模块及其组合组成的群组。在一个实施例中，所述多个伪管芯基本上均匀地分布在所述外围区域中。在一个实施例中，接合至所述封装组件的所述重建晶圆具有圆形顶视图形状。在一个实施例中，所述重建晶圆在接合至所述封装组件之前是未锯切的。在一个实施例中，所述方法还包括通过穿透所述重建晶圆的螺栓将所述重建晶圆固定至所述封装组件。在一个实施例中，所述螺栓穿过所述多个伪管芯中的一个伪管芯。在一个实施例中，所述封装包括分配所述密封剂以及平坦化所述密封剂，其中在所述平坦化中抛光所述多个伪管芯中的伪管芯。在一个实施例中，所述多个伪管芯比所述多个功能管芯薄，并且所述封装包括分配所述密封剂以及平坦化所述密封剂，其中在所述平坦化之后，所述密封剂层覆盖所述多个伪管芯。在一个实施例中，所述多个功能管芯放置为多个群组，同时同一群组中的管芯之间的组内间距小于所述多个群组中的相邻群组之间的组间间隔。在一个实施例中，所述方法还包括将额外的多个伪管芯放置在所述多个群组之间。在一个实施例中，所述多个群组中的一个群组中的管芯包括计算管芯和输入-输出管芯。在一个实施例中，所述方法还包括将多个输入-输出管芯放置在所述多个功能管芯周围。
根据本发明公开的一些实施例，一种方法包括将多个逻辑管芯放置在载体上、将多个IO管芯放置在所述载体上、将多个伪管芯放置在所述载体上，其中所述多个伪管芯分布在所述多个逻辑芯片和所述多个IO芯片所在的区域周围；将所述多个逻辑管芯、所述多个IO管芯和所述多个伪管芯封装在密封剂中；在所述多个逻辑管芯和所述多个IO管芯上形成再分配线并电耦合以形成重建晶圆，所述重建晶圆包括所述多个逻辑管芯、所述多个IO管芯、所述多个伪管芯、所述密封剂和所述再分配线；以及将所述重建晶圆从所述载体上脱粘。在一个实施例中，所述方法还包括将所述重建晶圆接合至封装组件上而不锯切所述重建晶圆。在一个实施例中，所述方法还包括在所述封装之前，在所述多个逻辑管芯中的两个逻辑管芯之间插入伪管芯。在一个实施例中，所述多个逻辑管芯放置为多个群组的一部分，同时同一群组中的管芯之间的组内间距小于所述多个群组中的相邻群组之间的组间间隔。在一个实施例中，所述多个IO管芯放置为所述多个群组的一部分。
根据本发明公开的一些实施例，一种封装包括重建晶圆，所述重建晶圆包括多个伪管芯、位于所述封装件的中心区域中的多个功能管芯，其中对准环绕所述多个功能管芯的环来分配所述多个伪管芯；其中封装所述多个伪管芯和所述多个功能管芯的密封剂；以及位于所述多个功能管芯上的多个RDL，其中所述多个RDL将所述封装件中的所有功能管芯互连进集成系统中。在一个实施例中，所述封装还包括封装组件，所述封装组件接合至所述重建晶圆，其中所述封装组件选自基本上由中介层、封装衬底、印刷电路板、热模块及其组合组成的群组。在一个实施例中，接合至所述封装组件的所述重建晶圆具有圆形顶视图形状。
前述概述了若干实施例的特征，使得本领域技术人员可更好地理解本公开的各方面。本领域技术人员应当理解，他们可以容易地使用本公开作为设计或修改其他过程和结构的基础，以实现相同的目的和/或实现本发明介绍的实施例的相同优点。本领域技术人员还应该认识到，这样的等同构造不脱离本公开的精神和范围，并且在不脱离本公开的精神和范围的情况下，它们可以在本发明中进行各种改变、替换和变更。

Claims (10)

1.一种形成封装件的方法，包括：
将多个功能管芯放置在载体上；
将多个伪管芯放置在所述载体上；
将所述多个功能管芯和所述多个伪管芯封装在密封剂中；
在所述多个功能管芯上形成再分配线，所述再分配线互连所述多个功能管芯，其中所述再分配线、所述多个功能管芯、所述多个伪管芯和所述密封剂组合形成重建晶圆，其中所述多个功能管芯位于所述重建晶圆的中心区域中，且所述多个伪管芯位于所述重建晶圆的外围区域中，同时所述外围区域环绕所述中心区域；
将所述重建晶圆从所述载体上脱粘；以及
将所述重建晶圆接合至封装组件，所述封装组件选自由中介层、封装衬底、印刷电路板、热模块及其组合组成的群组。
2.根据权利要求1所述的方法，其中，所述多个伪管芯均匀地分布在所述外围区域中。
3.根据权利要求1所述的方法，其中，接合至所述封装组件的所述重建晶圆具有圆形顶视图形状。
4.根据权利要求1所述的方法，其中，所述重建晶圆在接合至所述封装组件之前是未锯切的。
5.根据权利要求1所述的方法，还包括通过穿透所述重建晶圆的螺栓将所述重建晶圆固定至所述封装组件。
6.根据权利要求5所述的方法，其中，所述螺栓穿过所述多个伪管芯中的一个伪管芯。
7.根据权利要求1所述的方法，其中，所述封装包括：
分配所述密封剂；以及
平坦化所述密封剂，其中在所述平坦化中抛光所述多个伪管芯中的伪管芯。
8.根据权利要求1所述的方法，其中，所述多个伪管芯比所述多个功能管芯薄，并且其中，所述封装包括：
分配所述密封剂；以及
平坦化所述密封剂，其中在所述平坦化之后，所述密封剂的层覆盖所述多个伪管芯。
9.一种形成封装件的方法，包括：
将多个逻辑管芯放置在载体上；
将多个输入-输出(IO)管芯放置在所述载体上；
将多个伪管芯放置在所述载体上，其中所述多个伪管芯分布在所述多个逻辑芯片和所述多个输入-输出芯片所在的区域周围；
将所述多个逻辑管芯、所述多个输入-输出管芯和所述多个伪管芯封装在密封剂中；
在所述多个逻辑管芯和所述多个输入-输出管芯上形成再分配线，所述再分配线电耦合至所述多个逻辑管芯和所述多个输入-输出管芯以形成重建晶圆，所述重建晶圆包括所述多个逻辑管芯、所述多个输入-输出管芯、所述多个伪管芯、所述密封剂和所述再分配线；以及
将所述重建晶圆从所述载体上脱粘。
10.一种封装件，包括：
重建晶圆，包括：
多个伪管芯；
多个功能管芯，所述多个功能管芯位于所述封装件的中心区域中，其中对准环绕所述多个功能管芯的环来分配所述多个伪管芯；
密封剂，所述密封剂中封装所述多个伪管芯和所述多个功能管芯；以及
多个再分配线(RDL)，所述多个再分配线位于所述多个功能管芯上，其中所述多个再分配线将所述封装件中的所有功能管芯互连至集成系统中。
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