CN110660656A - Ion implantation method of P-type well, P-type well structure and CMOS device manufacturing method - Google Patents
Ion implantation method of P-type well, P-type well structure and CMOS device manufacturing method Download PDFInfo
- Publication number
- CN110660656A CN110660656A CN201910937992.3A CN201910937992A CN110660656A CN 110660656 A CN110660656 A CN 110660656A CN 201910937992 A CN201910937992 A CN 201910937992A CN 110660656 A CN110660656 A CN 110660656A
- Authority
- CN
- China
- Prior art keywords
- ion implantation
- type well
- layer
- carbon
- implantation process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005468 ion implantation Methods 0.000 title claims abstract description 135
- 238000000034 method Methods 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 229910052799 carbon Inorganic materials 0.000 claims description 60
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 24
- 238000002955 isolation Methods 0.000 claims description 20
- 230000002401 inhibitory effect Effects 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- -1 carbon ion Chemical class 0.000 claims description 8
- 230000001629 suppression Effects 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 239000000243 solution Substances 0.000 description 5
- 238000005280 amorphization Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to an ion implantation method of a P-type well, a P-type well structure and a CMOS device manufacturing method, and relates to a semiconductor integrated circuit manufacturing process.
Description
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing processes, and more particularly, to an ion implantation method for a P-type well, a P-type well structure, and a CMOS device manufacturing method.
Background
With the rapid development of very large scale integrated circuit technology, the dimensions of MOSFET devices such as channel length and gate oxide thickness are continuously scaled down, and the improvement of the performance of future semiconductor devices will face three challenges: 1. the method comprises the following steps of increasing leakage current of a device, increasing source/drain resistance, and reducing mismatch of device parameters and debugging window of a device manufacturing process. The leakage current, in which the device rapidly increases, is a major factor affecting the operating performance of the device.
Fig. 1 is a schematic diagram illustrating the generation of leakage current of a semiconductor device, which is mainly increased by gate-induced drain leakage current (GIDL), tunneling current (BTBT), leakage current (junction leakage and Iwell) caused by PN junction capacitance formed between a source/drain and a well, and leakage current (Ich) between the source and the drain, which causes significant Short Channel Effect (SCE). In order to reduce the leakage current between the source and the drain, Ich & Isub is controlled by a method of inversely doping a well, wherein a well structure is formed by using III group elements for NMOS or V group elements for PMOS. However, the conventional well structure causes large parasitic capacitance between the source and drain regions and the well, so that the operating frequency of the device is reduced. In order to reduce the parasitic capacitance, a graded junction is formed between the source/drain and the well of the device by adopting a high-energy and low-dose ion implantation process during the source-drain implantation process so as to reduce the parasitic capacitance, but the ion implantation in this step can cause the device to have a poor short channel effect and the high-energy ion implantation can break down polysilicon (poly), so that the threshold voltage of the device is reduced, and the leakage current of the device is increased. Fig. 2 is a schematic diagram of a capacitance structure of a device, in fig. 2, PN junction parasitic capacitances Csb and Cdb are formed between a source/drain and a well, the magnitude of the PN junction parasitic capacitances Csb and Cdb has a strong correlation with AC performance (AC performance) of the device, such as cut-off frequency and speed, and occupies a considerable proportion of the parasitic capacitance of the entire device, and in order to improve the performance of the semiconductor device, it is desirable that the smaller the PN junction parasitic capacitances Csb and Cdb formed between the source/drain and the well, the better.
Disclosure of Invention
The invention aims to provide an ion implantation method of a P-type well, which can effectively reduce PN junction capacitance.
The invention provides an ion implantation method of a P-type well, which comprises the following steps: s1: performing a well isolation ion implantation process on a P-type well region on a semiconductor substrate to form a well isolation ion implantation layer in the P-type well region; s2: performing punch-through ion implantation inhibiting process on the trap to form a punch-through ion implantation inhibiting layer; s3: performing a carbon ion implantation process to form a carbon ion implanted layer; and S4: and performing a threshold voltage adjustment ion implantation process to form a threshold voltage adjustment ion implantation layer.
Further, the energy of the carbon ion implantation process ranges from 10k to 150 k.
Further, the dosage of the carbon ion implantation process is in the range of 1e13cm-2To 9e15cm-2In the meantime.
Further, the deflection angle of the carbon ion implantation process ranges from 0 degree to 45 degrees.
Furthermore, the energy range of the carbon ion implantation process is between 10k and 150k, and the dose range is 1e13cm-2To 9e15cm-2Between 0 and 45 degrees.
The present invention also provides a P-type well structure, comprising: the semiconductor device includes a well isolation ion implantation layer formed on a semiconductor substrate, a punch-through suppression ion implantation layer formed on the well isolation ion implantation layer, a carbon ion implantation layer formed on the punch-through suppression ion implantation layer, and a threshold voltage adjustment ion implantation layer formed on the carbon ion implantation layer.
Furthermore, the semiconductor substrate is a silicon substrate.
Furthermore, the energy passing range of the carbon ion implantation layer is between 10k and 150k, and the dosage range is 1e13cm-2To 9e15cm-2And a deflection angle ranging from 0 to 45 degrees.
The invention also provides a CMOS device manufacturing method, which comprises the following steps: s10: providing a semiconductor substrate, performing a shallow trench isolation process, and forming a plurality of active regions on the semiconductor substrate; s11: performing ion implantation of the well to form a P-type well structure, comprising: s111: performing a well isolation ion implantation process on a P-type well region on a semiconductor substrate to form a well isolation ion implantation layer in the P-type well region; s112: performing punch-through ion implantation inhibiting process on the trap to form a punch-through ion implantation inhibiting layer; s113: performing a carbon ion implantation process to form a carbon ion implanted layer; and S114: performing a threshold voltage adjustment ion implantation process to form a threshold voltage adjustment ion implantation layer; s12: carrying out ion implantation of the trap to form an N-type trap structure; s13: manufacturing a grid oxide layer and depositing a grid material, and photoetching the grid material to form a grid; s14: performing NMOS light doping injection in the P-type well structure region to form an NMOS device drain light doping structure; s15: performing PMOS light doping injection in the N-type well structure region to form a PMOS device drain light doping structure; s16: manufacturing a first side wall of the grid; s17: manufacturing a second side wall of the grid; s18: performing source-drain injection to form a source-drain electrode; and S19: and carrying out back-end interconnection process manufacturing.
Further, the gate material is polysilicon.
Furthermore, the formation of the first side wall includes the oxidation of the gate material and the deposition and etching of SiN.
Further, the formation of the second side wall includes deposition and etching of SiO2 and SiN.
Further, the energy of the carbon ion implantation process ranges from 10k to 150 k.
Further, the dosage of the carbon ion implantation process is in the range of 1e13cm-2To 9e15cm-2In the meantime.
Further, the deflection angle of the carbon ion implantation process ranges from 0 degree to 45 degrees.
Furthermore, the energy of the carbon ion implantation process ranges from 10k to 150k, and the dose ranges from 1e13cm-2To 9e15cm-2Between 0 and 45 degrees.
The invention provides an ion implantation method of a P-type well, a P-type well structure and a CMOS device manufacturing method.
Drawings
Fig. 1 is a schematic diagram of generation of a leakage current of a semiconductor device.
Fig. 2 is a schematic diagram of the capacitor structure of the device.
Fig. 3 is a schematic diagram illustrating the influence of the carbon ion implantation process on the PN junction capacitance.
FIG. 4 is a schematic diagram of a P-well structure according to an embodiment of the present invention.
The reference numerals of the main elements in the figures are explained as follows:
410. a semiconductor substrate; 420. a well isolation ion implantation layer; 430. a punch-through ion implantation inhibiting layer; 440. a carbon ion implanted layer; 450. a threshold voltage adjusting ion implantation layer; 400. and a P-type well structure.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, an ion implantation method for a P-type well is provided. Specifically, the ion implantation method of the P-type well comprises the following steps: s1: performing well isolation ion implantation (wellion implantation) process on the P-type well region on the semiconductor substrate to form a well isolation ion implantation layer in the P-type well region; s2: performing punch-through ion implantation (punch-through implantation) to form a punch-through ion implantation inhibiting layer; s3: performing a carbon ion implantation process to form a carbon ion implanted layer; and S4: a threshold voltage adjusting ion implantation process (Vtimplant) is performed to form a threshold voltage adjusting ion implantation layer.
The carbon ion implantation process is added between the punch-through ion implantation inhibiting process and the threshold voltage adjusting ion implantation process of the trap, so that an amorphous layer of the carbon ion implantation layer is formed between the punch-through ion implantation inhibiting layer and the threshold voltage adjusting ion implantation layer, the amorphous layer can inhibit ions of the punch-through ion implantation inhibiting layer from diffusing to the threshold voltage adjusting ion implantation layer, the concentration of the side, with shallower doping, of the PN junction is kept unchanged, and the increase of the parasitic capacitance of the PN junction is prevented.
Specifically, referring to fig. 3, fig. 3 is a schematic diagram illustrating an influence of a carbon ion implantation process on a PN junction capacitance, as shown in fig. 3, comparing a size of the PN junction capacitance between a source drain and a P-type well of a device after a carbon ion implantation process is not introduced into the P-type well and a carbon ion implantation process is introduced into the P-type well, which is shown in fig. 3 "╳The shape mark is the magnitude of the PN junction capacitance (Csb or Cdb) between the source and drain and the P-type of a conventional well implant without introducing carbon ion implantation, and the "+" mark is the value of the PN junction capacitance after introducing carbon ion implantation. It can be seen that the capacitance of the PN junction formed between the source/drain and the P-type well is smaller after the carbon ion implantation process is introduced in the P-type well ion implantation process than that formed between the source/drain and the P-type well without the carbon ion implantation process, i.e., the capacitance of the PN junction is effectively reduced after the carbon ion implantation process is introduced.
Specifically, in an embodiment of the present invention, the energy of the carbon ion implantation process is in a range from 10k to 150 k.
Specifically, in an embodiment of the present invention, the dosage of the carbon ion implantation process is in the range of 1e13cm-2To 9e15cm-2In the meantime.
Specifically, in an embodiment of the present invention, the deflection angle of the carbon ion implantation process is in a range from 0 degree to 45 degrees.
Specifically, in an embodiment of the present invention, the energy of the carbon ion implantation process is in a range from 10k to 150k, and the dose is in a range from 1e13cm-2To 9e15cm-2Between 0 and 45 degrees.
In an embodiment of the present invention, a P-type well structure is further provided. Specifically, referring to fig. 4, fig. 4 is a schematic diagram of a P-well structure according to an embodiment of the invention, as shown in fig. 4, the P-well structure 400 includes: a well-isolating ion-implanted layer 420 formed on the semiconductor substrate 410, a punch-through suppressing ion-implanted layer 430 formed on the well-isolating ion-implanted layer 420, a carbon ion-implanted layer 440 formed on the punch-through suppressing ion-implanted layer 430, and a threshold voltage adjusting ion-implanted layer 450 formed on the carbon ion-implanted layer 440.
As shown in fig. 4, an amorphization layer of the carbon ion implantation layer 440 is formed between the punch-through ion implantation suppression layer 430 and the threshold voltage adjusting ion implantation layer 450, and the amorphization layer can suppress the diffusion of the ions of the punch-through ion implantation layer 430 toward the threshold voltage adjusting ion implantation layer 450, keep the concentration of the PN junction on the side with the shallow doping, and prevent the increase of the parasitic capacitance of the PN junction.
Specifically, in an embodiment of the present invention, the semiconductor substrate 410 is a silicon substrate.
Specifically, in an embodiment of the present invention, the energy passing through the carbon ion implantation layer 440 ranges from 10k to 150k, and the dose ranges from 1e13cm-2To 9e15cm-2And a deflection angle ranging from 0 to 45 degrees.
In an embodiment of the invention, a method for manufacturing a CMOS device is also provided. Specifically, the method for manufacturing the CMOS device comprises the following steps:
s10: providing a semiconductor substrate, performing a shallow trench isolation process, and forming a plurality of active regions on the semiconductor substrate;
s11: performing ion implantation of the well to form a P-type well structure, comprising:
s111: performing a well isolation ion implantation process on a P-type well region on a semiconductor substrate to form a well isolation ion implantation layer in the P-type well region;
s112: performing punch-through ion implantation inhibiting process on the trap to form a punch-through ion implantation inhibiting layer;
s113: performing a carbon ion implantation process to form a carbon ion implanted layer; and
s114: performing a threshold voltage adjustment ion implantation process to form a threshold voltage adjustment ion implantation layer;
s12: carrying out ion implantation of the trap to form an N-type trap structure;
s13: manufacturing a grid oxide layer and depositing a grid material, and photoetching the grid material to form a grid;
s14: performing NMOS light doping injection in the P-type well structure region to form an NMOS device drain light doping structure;
s15: performing PMOS light doping injection in the N-type well structure region to form a PMOS device drain light doping structure;
s16: manufacturing a first side wall of the grid;
s17: manufacturing a second side wall of the grid;
s18: performing source-drain injection to form a source-drain electrode; and
s19: and carrying out back-end interconnection process manufacturing.
Specifically, in an embodiment of the present invention, the gate material is polysilicon.
Specifically, in an embodiment of the present invention, the forming of the first sidewall spacers includes oxidizing the gate material and depositing and etching SiN.
Specifically, in an embodiment of the present invention, the forming of the second sidewall spacers includes depositing and etching SiO2 and SiN.
Specifically, in an embodiment of the present invention, the energy of the carbon ion implantation process is in a range from 10k to 150 k.
Specifically, in an embodiment of the present invention, the dosage of the carbon ion implantation process is in the range of 1e13cm-2To 9e15cm-2In the meantime.
Specifically, in an embodiment of the present invention, the deflection angle of the carbon ion implantation process is in a range from 0 degree to 45 degrees.
Specifically, in an embodiment of the present invention, the energy of the carbon ion implantation process is in a range of 10k to 150k, and the dose is in a range of 1e13cm-2To 9e15cm-2Between 0 and 45 degrees.
Specifically, in an embodiment of the present invention, the semiconductor substrate is a silicon substrate.
The CMOS device formed by the CMOS process is subjected to WAT test, and PN junction capacitance parameters between the source/drain of the device and the P-type well are compared, so that PN junction parasitic capacitances Csb and Cdb formed between the source/drain and the well of the CMOS device formed by the method are obviously reduced.
In summary, in the ion implantation process of the P-type well structure, a carbon ion implantation process is added between the punch-through suppression ion implantation process and the threshold voltage adjustment ion implantation process of the well, so as to form an amorphization layer of the carbon ion implantation layer between the punch-through suppression ion implantation layer and the threshold voltage adjustment ion implantation layer, and the amorphization layer can suppress ions of the punch-through suppression ion implantation layer from diffusing to the threshold voltage adjustment ion implantation layer, keep the concentration of the shallower doped side of the PN junction unchanged, and prevent the increase of the parasitic capacitance of the PN junction.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (16)
1. A method for implanting ions into a P-type well, comprising:
s1: performing a well isolation ion implantation process on a P-type well region on a semiconductor substrate to form a well isolation ion implantation layer in the P-type well region;
s2: performing punch-through ion implantation inhibiting process on the trap to form a punch-through ion implantation inhibiting layer;
s3: performing a carbon ion implantation process to form a carbon ion implanted layer; and
s4: and performing a threshold voltage adjustment ion implantation process to form a threshold voltage adjustment ion implantation layer.
2. The method of claim 1, wherein the energy of the carbon ion implantation process is in a range of 10k to 150 k.
3. The method of claim 1, wherein the carbon ion implantation process has a dose in the range of 1e13cm-2To 9e15cm-2In the meantime.
4. The method of claim 1, wherein the carbon ion implantation process has a deflection angle in a range of 0 to 45 degrees.
5. The method of claim 1, wherein the energy of the carbon ion implantation process is in the range of 10k to 150k, and the dose is in the range of 1e13cm-2To 9e15cm-2Between 0 and 45 degrees.
6. A P-type well structure, comprising: the semiconductor device includes a well isolation ion implantation layer formed on a semiconductor substrate, a punch-through suppression ion implantation layer formed on the well isolation ion implantation layer, a carbon ion implantation layer formed on the punch-through suppression ion implantation layer, and a threshold voltage adjustment ion implantation layer formed on the carbon ion implantation layer.
7. The P-type well structure of claim 6, wherein the semiconductor substrate is a silicon substrate.
8. The P-type well structure of claim 6, wherein the carbon ion implantation layer has a pass energy ranging from 10k to 150k and a dose ranging from 1e13cm-2To 9e15cm-2And a deflection angle ranging from 0 to 45 degrees.
9. A CMOS device manufacturing method is characterized by comprising the following steps:
s10: providing a semiconductor substrate, performing a shallow trench isolation process, and forming a plurality of active regions on the semiconductor substrate;
s11: performing ion implantation of the well to form a P-type well structure, comprising:
s111: performing a well isolation ion implantation process on a P-type well region on a semiconductor substrate to form a well isolation ion implantation layer in the P-type well region;
s112: performing punch-through ion implantation inhibiting process on the trap to form a punch-through ion implantation inhibiting layer;
s113: performing a carbon ion implantation process to form a carbon ion implanted layer; and
s114: performing a threshold voltage adjustment ion implantation process to form a threshold voltage adjustment ion implantation layer;
s12: carrying out ion implantation of the trap to form an N-type trap structure;
s13: manufacturing a grid oxide layer and depositing a grid material, and photoetching the grid material to form a grid;
s14: performing NMOS light doping injection in the P-type well structure region to form an NMOS device drain light doping structure;
s15: performing PMOS light doping injection in the N-type well structure region to form a PMOS device drain light doping structure;
s16: manufacturing a first side wall of the grid;
s17: manufacturing a second side wall of the grid;
s18: performing source-drain injection to form a source-drain electrode; and
s19: and carrying out back-end interconnection process manufacturing.
10. The CMOS device fabrication method of claim 9, wherein the gate material is polysilicon.
11. The method for manufacturing a CMOS device as claimed in claim 9, wherein the forming of the first sidewall comprises oxidation of a gate material and deposition and etching of SiN.
12. The method for manufacturing the CMOS device as claimed in claim 9, wherein the forming of the second side wall comprises deposition and etching of SiO2 and SiN.
13. The method of claim 9, wherein the energy of the carbon ion implantation process is in a range of 10k to 150 k.
14. The CMOS device fabrication method of claim 9, wherein the carbon ion implantationThe dosage range of the preparation method is 1e13cm-2To 9e15cm-2In the meantime.
15. The method of claim 9, wherein the carbon ion implantation process has a deflection angle in a range of 0 to 45 degrees.
16. The method of claim 9, wherein the carbon ion implantation process has an energy ranging from 10k to 150k and a dose ranging from 1e13cm-2To 9e15cm-2Between 0 and 45 degrees.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910937992.3A CN110660656A (en) | 2019-09-30 | 2019-09-30 | Ion implantation method of P-type well, P-type well structure and CMOS device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910937992.3A CN110660656A (en) | 2019-09-30 | 2019-09-30 | Ion implantation method of P-type well, P-type well structure and CMOS device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110660656A true CN110660656A (en) | 2020-01-07 |
Family
ID=69040123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910937992.3A Pending CN110660656A (en) | 2019-09-30 | 2019-09-30 | Ion implantation method of P-type well, P-type well structure and CMOS device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110660656A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104916539A (en) * | 2014-03-12 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor devices |
| CN106449405A (en) * | 2015-08-12 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN107564817A (en) * | 2016-06-30 | 2018-01-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of FinFET |
| CN107591328A (en) * | 2016-07-07 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2019
- 2019-09-30 CN CN201910937992.3A patent/CN110660656A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104916539A (en) * | 2014-03-12 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor devices |
| CN106449405A (en) * | 2015-08-12 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN107564817A (en) * | 2016-06-30 | 2018-01-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of FinFET |
| CN107591328A (en) * | 2016-07-07 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7651920B2 (en) | Noise reduction in semiconductor device using counter-doping | |
| US7989297B2 (en) | Asymmetric epitaxy and application thereof | |
| US6297098B1 (en) | Tilt-angle ion implant to improve junction breakdown in flash memory application | |
| US11152505B2 (en) | Drain extended transistor | |
| KR100638546B1 (en) | Method of forming transistor structure and transistor structure | |
| CN110120346B (en) | LDMOS transistor and manufacturing method thereof | |
| KR20080020401A (en) | A semiconductor for a dual gate cmos and method for fabricating the same | |
| US20090170269A1 (en) | High voltage mosfet devices containing tip compensation implant | |
| JP2933796B2 (en) | Method for manufacturing semiconductor device | |
| KR20010016838A (en) | Method of forming impurity doped region of MOS transistor | |
| CN110660656A (en) | Ion implantation method of P-type well, P-type well structure and CMOS device manufacturing method | |
| US10490651B2 (en) | Semiconductor structures and fabrication methods thereof | |
| KR19980079311A (en) | Semiconductor device and manufacturing method thereof | |
| JP2004221223A (en) | Mis semiconductor device and its manufacturing method | |
| US7696053B2 (en) | Implantation method for doping semiconductor substrate | |
| CN109920853B (en) | Semiconductor device and method for manufacturing the same | |
| KR100334968B1 (en) | Method for fabricating buried channel type PMOS transistor | |
| KR100271801B1 (en) | Manufacturing Method of Semiconductor Device | |
| US20080057657A1 (en) | Method for fabrication of semiconductor device | |
| CN116314002A (en) | Implementation mode of PDSOI body contact structure | |
| CN113555362A (en) | CMOS device and process method | |
| KR100815964B1 (en) | Semiconductor device and method for manufacturing having the same | |
| KR20100111021A (en) | Semiconductor device and method for manufacturing the same | |
| KR20060077160A (en) | Method for manufacturing transistor in semiconductor device | |
| CN111129141A (en) | Preparation method of semiconductor device and semiconductor device obtained by preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200107 |
|
| RJ01 | Rejection of invention patent application after publication |