KR20100111021A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve vertical and lateral internal pressure without changing a design rule. CONSTITUTION: A first conductive well is formed on a semiconductor substrate(100). A first conductive drift region(130) with low density and a second conductive drift region(140) with low density are separately formed on the first conductive well. A first conductive drift region(132) with high density is formed on the first conductive drift region with low density. A second conductive drift region(142) with high density is formed on the second conductive drift region with low density.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same, which can improve vertical and lateral resistances without changing design rules.

Ideally, the power semiconductor device is preferably a device capable of operating at a high voltage close to the theoretical breakdown voltage of the semiconductor.

Accordingly, when an external system using high voltage is controlled by an integrated circuit, the integrated circuit needs an element for high voltage control therein, and such an element requires a structure having a high breakdown voltage. do.

That is, in the drain or the source of the transistor to which the high voltage is integrated, the punch-through voltage between the drain and the source and the semiconductor substrate and the breakdown voltage between the drain and the source and the well or the substrate should be greater than the high voltage. .

Among high voltage semiconductor devices, LDMOS (lateral diffused MOS), which is a high voltage MOS, has a structure suitable for high voltage because the channel region and the drain electrode are separated by a drift region and controlled by the gate electrode.

1 is a cross-sectional view showing the structure of a general LDMOS transistor.

As shown in FIG. 1, an LDMOS transistor forms a deep N well region 10 in a semiconductor substrate (not shown) in which an isolation layer 12 is formed, and a P-type body formed in the deep N well region 10. A P-type body 20 and an N-type drift region 25, and sidewall spacers 42 on a semiconductor substrate (not shown) between the P-type body region 20 and the N-type drift region 25. The poly gate 40 is formed. The first LDD region 36 and the source region 30 are formed in the P-type body region 20, and the second LDD region 38 and the drain region 32 are formed in the N-type drift region 25.

These LDMOS transistors have a lot of difficulties in designing high voltage devices because they have to control the concentration and length of the drift region based on fundamentally given design rules in order to improve the breakdown voltage (BV) and on-resistance characteristics. This exists.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device and a method of manufacturing the same, which may improve vertical and lateral resistances without changing design rules.

The semiconductor device according to the embodiment of the present invention for achieving the above object is a low-concentration first conductivity-type drift region and a low-concentration second semiconductor substrate formed with a first conductivity type well, spaced apart from each other in the first conductivity type well A conductive drift region, a high concentration first conductivity type drift region formed in the low concentration first conductivity type drift region, a high concentration second conductivity type drift region formed in the low concentration second conductivity type drift region, a low concentration first conductivity type drift region, and A poly gate including sidewall spacers formed on the semiconductor substrate between the low concentration second conductivity type drift regions, and a high concentration first conductivity type drift region and a high concentration second conductivity type drift region on both sides of the poly gate including the sidewall spacers. Source and drain regions to be formed, and high concentration first conductivity type drift region And first and second LDD regions formed on surfaces of the high concentration second conductivity type drift regions, respectively.

A method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object is to form a first conductivity type well on a semiconductor substrate, and to form a first conductivity type drift region in the first conductivity type well Forming a second conductivity type drift region in the first conductivity type well so as to be spaced apart from the first conductivity type drift region, and forming a poly gate on the semiconductor substrate between the first and second conductivity type drift regions. And forming first and second LDD regions on the surfaces of the first and second conductivity type drift regions on both sides of the poly gate, forming sidewall spacers on both sides of the poly gate, and sidewall spacers. And forming source and drain regions in the first and second conductivity type drift regions on both sides of the poly gate, respectively.

A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention have the following effects.

If impurities are implanted to form the drift region in the well process before the poly gate is formed, the use of the impurity implantation energy is increased due to the mask pattern, thereby securing a large margin for securing the drift region.

In addition, it is possible to improve the vertical and lateral pressures without changing design rules.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

2 is a cross-sectional view showing an LDMOS transistor according to the present invention.

Referring to FIG. 2, a deep P well region 110, which is an active region, is formed in the semiconductor substrate 100, and an isolation layer 102 is formed to separate the active region. The active region 120 of the peripheral device may be formed of P type, which is the same well type, or N type, which is another well type.

Each of the low concentration P-type drift region 140 and the low concentration N-type drift region 130 and the low concentration P-type drift region 140 and the low concentration N-type drift region 130 formed in the deep P well region 110 are spaced apart from each other. The poly gate formed on the semiconductor substrate 100 between the formed high concentration P-type drift region 142 and the high concentration N-type drift region 132, and the low concentration P-type drift region 140 and the low concentration N-type drift region 130. 160).

For example, in the case of an NMOS transistor, the active region is a P type well, and in the case of a PMOS transistor, the active region is an N type well. The active region becomes a portion of the MOS transistor that forms a channel between the source and the drain. The active region 120 of the peripheral devices may be formed in the P type which is the same well type or may be formed in the N type which is another well type.

Lightly doped drain (LDD) regions through low concentration impurity ion implantation into substrates on both sides of the poly gate 160, that is, into the low concentration P-type drift region 140 and the low concentration N-type drift region 130, respectively. After forming 144 and 146, sidewall spacers 158 are formed on both sidewalls of the poly gate 160. High concentration impurity ions are injected into the low concentration P-type drift region 140 by using the sidewall spacer 158 and a mask in the low concentration P-type drift region 140 and the low concentration N-type drift region 130 on both sides of the sidewall spacer 158. The source region 166 is formed, and the drain region 168 is formed in the low concentration N-type drift region 130 through the implantation of high concentration impurity ions.

Here, the concentrations of the P-type drift regions 140 and 142 as well as the N-type drift regions 130 and 132 formed in the deep P well region 110 are changed as compared with FIG. 1, that is, the high concentration N-type and the high concentration P-type. The drift regions 132 and 142 are further formed to compensate for the source-drain breakdown voltage.

3A to 3D are cross-sectional views illustrating a method of manufacturing an LDMOS transistor according to the present invention.

Referring to FIG. 3A, a deep P well region 110 is formed by implanting P-type impurity ions to define an active region of a MOS transistor on the semiconductor substrate 100. In the active region, the deep P well region 110 is formed, but in the case of a PMOS transistor, the active region becomes an N well region. The active region becomes the portion of the MOS transistor that forms the channel between the source and the drain.

In addition, a device isolation film (STI) 102 is formed to separate the active region.

Subsequently, low concentration N-type impurity ions are implanted into the active deep P well region 110 using the first photoresist pattern 150 exposing a portion of the semiconductor substrate 100 to form a breakdown voltage of the LDNMOS transistor. The low concentration N-type drift region 130 is formed, and the high concentration N-type drift region 130 is implanted into the low concentration N-type drift region 130 to form the high concentration N-type drift region 132.

Subsequently, the first photoresist pattern 150 is removed.

Referring to FIG. 3B, the second photoresist pattern exposing the semiconductor substrate 100 to be spaced apart from the N-type drift regions 130 and 132, that is, except for the region where the N-type drift regions 130 and 132 are formed. After forming 152, the P-type drift region 140. 142 is formed using the second photoresist pattern 152 as a mask.

Specifically, the low concentration P-type is spaced apart from the N-type drift regions 130 and 132 in the deep P-well region 110 by using the second photoresist pattern 152 as a mask to compensate for P-well region characteristics of the LDNMOS transistor. Impurity ions are implanted to form a low concentration P-type drift region 140, and high concentration P-type impurity ions are implanted into the low concentration P-type drift region 140 to form a high concentration P-type drift region 142.

As such, by changing the concentrations of the P-type drift regions 140 and 142 as well as the N-type drift regions 130 and 132 formed in the deep P well region 110, that is, the low-concentration N-type and low-concentration P-type drift regions ( High concentration N-type and high concentration P-type drift regions 132 and 142 are formed in the 130 and 140, respectively, to compensate for the source-drain breakdown voltage.

In addition, a general method of manufacturing an LDMOS transistor forms a drift region after poly gate formation, in which case the thickness of the poly gate is limited. That is, in high energy injection, the ion implantation energy is limited because it penetrates through the thickness of the poly gate (for example, 2000 mW) and goes below the channel. Therefore, when impurities are implanted to form the drift region in the well process before the poly gate is formed, as shown in FIGS. 3A and 3B, the use of the impurity implantation energy is increased due to the mask pattern, thereby securing a large margin for securing the drift region. Has an effect. When the ion implantation energy increases, the breakdown voltage BV may increase because the ion implantation energy may be deeply brought into the vertical regions of the N-type drift regions 130 and 132. In addition, since the mask position can be arbitrarily adjusted during the well process, the penetration position of impurities can also be adjusted when forming the N-type drift regions 130 and 132, so that the length can be adjusted to the side length, and the breakdown is controlled by the length control. Voltage regulation is also possible.

However, since the N-type drift regions 130 and 132 are performed before the poly gate formation, it is difficult to form the N-type drift regions 130 and 132 at the correct position when forming the mask. In other words, when the N-type impurities in the N-type drift regions 130 and 132 enter the source direction to be formed later than the desired reference, the P-type impurities under the poly gate are canceled out. Therefore, in order to prevent this, when the impurity ions are implanted using the P-type drift mask to form the P-type drift regions 140 and 142, the P-type impurities penetrate between the poly gate and the source region to form an N-type drift region ( 130, 132) serves to reinforce the P-type impurity concentration weakened by the penetration of the N-type impurity.

Accordingly, the threshold voltage (VT) of the device is lowered, and when the threshold voltage is lowered, an increase in off current and saturation current Idsat and a breakdown voltage BV are also caused. do. This makes it easier for electrons to move from source to drain through the channel, resulting in better operating characteristics.

Next, the second photoresist pattern 152 is removed.

Referring to FIG. 3C, a gate oxide film (not shown) and a polysilicon layer (not shown) are formed on the semiconductor substrate 100 on which the N-type drift regions 130 and 132 and the P-type drift regions 140 and 142 are formed. After deposition, the poly gate 160 is formed on the semiconductor substrate 100 between the N-type drift regions 130 and 132 and the P-type drift regions 140 and 142 by patterning through an etching process using a mask. .

Subsequently, the P-type drift regions 140 and 142 are exposed on the poly gate 160, and the N-type drift regions 130, so as to be spaced apart from a portion of the N-type drift regions 130 and 132, that is, the poly gate 160. A third photoresist pattern 154 is formed to expose a portion of the high concentration N-type drift region 132 of 132. N-type impurity ions are implanted using the poly gate 160 and the third photoresist pattern 154 as a mask to form a first lightly doped drain (LDD) region 144 on the surface of the P-type drift regions 140 and 142. Second lightly doped drain (LDD) regions 146 are formed on the surface of the high concentration N-type drift region 132 to be spaced apart from the poly gate 160.

In general, doping of semiconductors is closely related to resistance, and the higher the amount of impurities, the better the conductivity, and the lower the resistance, and the lower the amount of impurities, the higher the resistance. Therefore, when an LDD region having a relatively high impurity amount is formed near the poly gate, a voltage applied to the drain is transferred to the vicinity of the poly gate, and a drain voltage is applied between the poly gate and the LDD region, thereby breaking down even at a low voltage. Since the voltage (BV) is generated, the poly gate 160 and the second LDD region 146 should be formed to be spaced apart at appropriate intervals.

In addition, the second LDD region 146 is formed in the high concentration N-type drift region 132 to further increase the impurity concentration, thereby lowering the resistance.

Next, the third photoresist pattern 154 is removed.

Referring to FIG. 3D, sidewall spacers 158 which are sidewall spacers are formed on both sidewalls of the poly gate 160 on the semiconductor substrate 100 on which the first and second LDD regions 144 and 146 are formed. . The sidewall spacers 158 are formed to prevent punch through from occurring because the channels are too close in the future as the source and drain implants become larger.

Subsequently, the second LDD region 146 of the region where the source and drain regions 166 and 168 are to be formed on the semiconductor substrate 100, that is, the P-type drift regions 140 and 142 and the high concentration N-type drift region 146. The fourth photoresist pattern 156 is formed to expose a portion of the. The source region 166 is implanted into the P-type drift regions 140 and 142 by implanting N-type impurity ions using the poly gate 160 including the fourth photoresist pattern 156 and the sidewall spacer 158 as a mask. Drain regions 168 are formed in the N-type drift regions 130 and 132.

As such, when the impurity is implanted to form the drift region in the well process before the poly gate is formed, the use of the impurity implantation energy is increased due to the mask pattern, thereby securing a large margin for securing the drift region. In addition, it is possible to improve the vertical and lateral pressures without changing design rules.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view showing the structure of a general LDMOS transistor.

2 is a cross-sectional view showing an LDMOS transistor according to the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing an LDMOS transistor according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100 semiconductor substrate 102 device isolation film

110: deep P well region 130: low concentration N-type drift region

132: high concentration N-type drift region 140: low concentration P-type drift region

142: high concentration P-type drift region 144, 146: LDD region

166, 168: source and drain region 160: poly gate

Claims (6)

A semiconductor substrate having a first conductivity type well formed therein; A low concentration first conductivity type drift region and a low concentration second conductivity type drift region formed spaced apart from each other in the first conductivity type well; A high concentration first conductivity type drift region formed in the low concentration first conductivity type drift region; A high concentration second conductivity type drift region formed in the low concentration second conductivity type drift region; A poly gate comprising sidewall spacers formed on the semiconductor substrate between the low concentration first conductivity type drift region and the low concentration second conductivity type drift region; Source and drain regions formed in each of the high concentration first conductivity type drift region and the high concentration second conductivity type drift region on both sides of the poly gate including the sidewall spacers; And first and second LDD regions formed on surfaces of each of the high concentration first conductivity type drift region and the high concentration second conductivity type drift region. The method of claim 1, One of the first and second LDD regions is formed to be spaced apart from the poly gate. Forming a first conductivity type well on a semiconductor substrate, Forming a first conductivity type drift region in the first conductivity type well, Forming a second conductive drift region in the first conductive well to be spaced apart from the first conductive drift region; Forming a poly gate on the semiconductor substrate between the first and second conductivity type drift regions; Forming first and second LDD regions on surfaces of the first and second conductivity type drift regions on both sides of the poly gate; Forming sidewall spacers on both sides of the poly gate; And forming source and drain regions in first and second conductivity type drift regions on both sides of the poly gate including the sidewall spacers, respectively. The method of claim 3, wherein Any one of the first and second LDD regions is formed to be spaced apart from the poly gate. The method of claim 3, wherein Forming the first drift region, Forming a low concentration first conductivity type drift region by implanting low concentration first conductivity type impurity ions into one side of the first conductivity type well; And implanting a high concentration of the first conductivity type drift region into the low concentration first conductivity type drift region to form a high concentration first conductivity type drift region. The method of claim 3, wherein Forming the second drift region, Implanting low concentration second conductivity type impurity ions into the other side of the first conductivity type well to form a low concentration second conductivity type drift region; And implanting a high concentration of a second conductivity type drift region into the low concentration second conductivity type drift region to form a high concentration second conductivity type drift region.

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