CN110534427B - Etching method - Google Patents
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- CN110534427B CN110534427B CN201910842922.XA CN201910842922A CN110534427B CN 110534427 B CN110534427 B CN 110534427B CN 201910842922 A CN201910842922 A CN 201910842922A CN 110534427 B CN110534427 B CN 110534427B
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- 238000005530 etching Methods 0.000 title claims abstract description 328
- 238000000034 method Methods 0.000 title claims abstract description 142
- 238000002955 isolation Methods 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 230000007613 environmental effect Effects 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- 239000000758 substrate Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
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Abstract
The invention provides an etching method, which comprises the following steps: the first step is as follows: initializing; the second step is as follows: loading a corresponding process program according to an etching process, and confirming the required etching rate of the etching process; the third step: acquiring the real-time etching rate of an etching machine; the fourth step: comparing the required etching rate with the real-time etching rate; the fifth step: if the required etching rate is greater than the real-time etching rate, calling a first warm-up process program and returning to execute the third step; if the required etching rate is less than the real-time etching rate, calling a second warm-up process program and returning to execute the third step; and if the required etching rate is equal to the real-time etching rate, calling the etching process program. By comparing the required etching rate with the real-time etching rate, the etching machine correspondingly executes different procedures, so that the active intervention and dynamic adjustment of the real-time etching rate of the etching machine are realized.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an etching method.
Background
The etching machine is a semiconductor research and development and production device necessary for an etching process, wherein the etching rate of the etching machine is one of important parameters of the etching process, and factors such as the temperature in an etching chamber, the deposition amount of a polymer on the inner wall of the etching chamber, the density of plasma in the etching chamber, the gas pressure in the etching chamber and the like are factors influencing the etching rate of the etching machine.
In the etching process, when the real-time etching rate of the etching machine table has a large deviation from the etching rate required by the etching process, the etching machine table is usually difficult to actively intervene and adjust the real-time etching rate in time, and if the real-time etching rate of the etching machine table is too fast or too slow, the etching thickness of a corresponding layer or structure is too large or too small, so that the product defect is caused, and the generation rate of defective products is increased.
Therefore, there is a need for an etching method capable of actively intervening and dynamically adjusting the real-time etching rate of an etching machine during the etching process so as to meet the requirement of the etching rate required by the etching process.
Disclosure of Invention
The invention aims to provide an etching method to solve the problem that the real-time etching rate of an etching machine cannot be automatically intervened and dynamically adjusted in the etching process.
In order to solve the above technical problem, the present invention provides an etching method, including:
the first step is as follows: initializing etching parameters of an etching machine;
the second step is as follows: loading a corresponding process program according to an etching process and confirming the required etching rate of the etching process, wherein the process program comprises the following steps: an etching process, a first warm-up process and a second warm-up process;
the third step: acquiring the real-time etching rate of an etching machine;
the fourth step: comparing the required etching rate with the real-time etching rate;
the fifth step: if the required etching rate is greater than the real-time etching rate, calling a first warm-up process program to execute a first warm-up process, and returning to execute the third step; if the required etching rate is less than the real-time etching rate, calling a second warm-up process program to execute a second warm-up process, and returning to execute the third step; and if the required etching rate is equal to the real-time etching rate, calling the etching process program to execute the etching process.
Optionally, in the etching method, in the second warm-up process, silicon on the surface of the control wafer is etched to change an environmental parameter and a wafer contact bias voltage in the etching chamber, so as to reduce the real-time etching rate, where the environmental parameter in the etching chamber includes: chamber gas pressure and sidewall deposition composition.
Optionally, in the etching method, in the first warm-up process, the silicon nitride on the surface of the control wafer is etched, so that the generated polymer is deposited on the inner wall surface of the etching chamber to change the plasma density in the etching chamber, thereby increasing the real-time etching rate.
Optionally, in the etching method, the etching process includes an etching process of an isolation structure of a flash memory device sharing a source line and an etching process of a sidewall structure of a flash memory device sharing a word line.
Optionally, in the etching method, in the isolation structure etching process of the flash memory device sharing the source line, silicon nitride located between the word line and the bit line is etched to form the isolation structure of the flash memory device sharing the source line.
Optionally, in the etching method, in the etching process of the isolation structure of the flash memory device sharing the source line, the required etching rate is
Optionally, in the etching method, a critical dimension of the isolation structure of the flash memory device sharing the source line in the width direction is 0.12 um.
Optionally, in the etching method, in the etching process of the sidewall structure of the flash memory device sharing the word line, the silicon oxide located between the control gate and the word line is etched to form the sidewall structure of the flash memory device sharing the word line.
Optionally, in the etching method, in the etching process of the sidewall structure of the flash memory device sharing the word line, the required etching rate is
Optionally, in the etching method, the critical dimension of the sidewall structure of the flash memory device sharing the word line in the width direction is 90 nm.
In summary, the present invention provides an etching method, including: the first step is as follows: initializing; the second step is as follows: loading a corresponding process program according to an etching process and confirming the required etching rate of the etching process, wherein the process program comprises the following steps: an etching process, a first warm-up process and a second warm-up process; the third step: acquiring the real-time etching rate of an etching machine; the fourth step: comparing the required etching rate with the real-time etching rate; the fifth step: if the required etching rate is greater than the real-time etching rate, calling a second warm-up process program and returning to execute the third step; if the required etching rate is less than the real-time etching rate, calling a first warm-up process program and returning to execute the third step; and if the required etching rate is equal to the real-time etching rate, calling the etching process program. By comparing the required etching rate with the real-time etching rate and correspondingly executing different procedures, the active intervention and dynamic adjustment of the real-time etching rate of the etching machine are realized, so that the real-time etching rate of the etching machine meets the etching rate requirement of the etching process, the condition that the etching machine is mistakenly etched or insufficiently etched is avoided, the accuracy of the etching rate of the etching machine is improved, and the product yield is improved.
Drawings
FIG. 1 is a flowchart of an etching method according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a semiconductor structure of a flash memory device sharing a source line according to a first embodiment of the present invention;
FIG. 3 is a semiconductor structure diagram of a prior art word line sharing flash memory device according to a second embodiment of the present invention;
wherein the reference numbers indicate:
100-a substrate, 110-a gate oxide layer, 120-a floating gate polysilicon layer, 130-an oxide-nitride-oxide (ONO) film layer, 140-a control gate polysilicon layer, 150-a first side wall, 160-a second side wall, 170-a source line, 180-a third side wall, 190-a word line, 200-an isolation structure, 210-a tunneling oxide layer and 300-a bit line forming region;
400-substrate, 410-gate oxide layer, 420-floating gate polysilicon layer, 430-ONO film layer, 440-control gate polysilicon layer, 450-floating gate silicon nitride structure, 460-side wall structure, 471-silicon oxide layer, 472-silicon nitride layer, 480-tunneling oxide layer and 500-word line.
Detailed Description
The etching method proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific examples. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
Example one
The invention provides an etching method, and referring to fig. 1 and fig. 2, fig. 1 is a flowchart of an etching method according to a first embodiment of the invention, and fig. 2 is a schematic view of a semiconductor structure of a flash memory device sharing a source line according to a first embodiment of the invention.
As shown in fig. 2, the flash memory device sharing a source line generally includes: a substrate 100, a source line 170 located on the substrate 100, a gate oxide layer 110, a floating gate polysilicon layer 120, an ONO film layer 130 and a control gate polysilicon layer 140 located on the substrate 100 at two sides of the source line 170 in sequence, a second sidewall 160 separating the source line 170 from the control gate polysilicon layer 140, a first sidewall 150 located on the control gate polysilicon layer 140 and far from the source line 170 side, a third sidewall 180 located on the floating gate polysilicon layer 120 and located at the first sidewall 150 side, a tunnel oxide layer 210 located on the substrate 100 and located at the third sidewall 180 side, a word line 190 located on the tunnel oxide layer 210, and an isolation structure 200 located at the word line 190 side, in addition, a bit line forming region 300 is further formed on the substrate 100 at a side of the isolation structure 200 away from the word line 190, and a bit line is formed on a surface of the bit line forming region 300 in a subsequent process. In the process of manufacturing the flash memory device sharing the source line, the isolation structure 200 is usually made of silicon nitride, and before the isolation structure 200 between the bit line and the word line 190 is formed, since the isolation structure 200 is formed by a self-aligned process, a certain height difference exists between the word line 190 and the third sidewall 180 between the control gate polysilicon layer 120. When the etching process of the isolation structure 200 of the flash memory device sharing the source line is performed, on one hand, if the etching rate of the etching machine is too fast, the substrate 100 at the position of the bit line forming region 300 is over-etched, so that a pit problem occurs; on the other hand, if the real-time etching rate of the machine is too low, silicon nitride residue generated during the process of forming the isolation structure 200 on the top of the word line 190 still remains, thereby affecting the subsequent metallization process.
The etching method in the etching process of the isolation structure 200 of the flash memory device that shares the source line is specifically described next.
First step S10: initializing etching parameters of an etching machine, specifically initializing specific etching parameters in all irrelevant etching process programs loaded before power failure, wherein the etching parameters of the etching machine can include but are not limited to etching rate, etching deviation, selection ratio, uniformity, etching profile and other parameters.
Second step S20: loading a corresponding process program according to an etching process and confirming the required etching rate of the etching process, wherein the process program comprises the following steps: an etching process, a first warm-up process, and a second warm-up process. Specifically, the etching process includes an etching process of an isolation structure of a flash memory device sharing a source line and an etching process of a sidewall structure of a flash memory device sharing a word line, in this embodiment, an etching process of an isolation structure 200 of a flash memory device sharing a source line is performed, and in this embodiment, a critical dimension of the isolation structure 200 of the flash memory device sharing a source line in a width direction is 0.12 um. And loading an isolation structure etching process program of the flash memory device sharing the source line according to the isolation structure 200 etching process of the flash memory device sharing the source line, confirming the required etching rate of the etching isolation structure, and inputting the required etching rate into the etching machine. Wherein the required etching rate corresponding to the etching process of the isolation structure 200 of the flash memory device sharing the source line is
Third step S30: and acquiring the real-time etching rate of the etching machine.
Fourth step S40: and comparing the required etching rate with the real-time etching rate.
Fifth step S50: if the required etching rate is greater than the real-time etching rate, calling a first warm-up process program to execute a first warm-up process, and returning to execute the third step; if the required etching rate is less than the real-time etching rate, calling a second warm-up process program to execute a second warm-up process, and returning to execute the third step; and if the required etching rate is equal to the real-time etching rate, calling the etching process program to execute the etching process. Specifically, when the required etching rate is greater than the real-time etching rate, in the second warm-up process, etching silicon on the surface of the control wafer to change environmental parameters in the etching chamber and wafer contact bias voltage to reduce the real-time etching rate, wherein the environmental parameters in the etching chamber include but are not limited to chamber gas pressure and sidewall deposition composition; when the required etching rate is less than the real-time etching rate, in the first warm-up process, the silicon nitride on the surface of the etching control wafer enables the generated polymer to be deposited on the surface of the inner wall of the etching chamber so as to change the plasma density in the etching chamber to increase the real-time etching rate. When the required etching rate is equal to the real-time etching rate, as shown in fig. 2, in the isolation structure etching process of the flash memory device sharing the source line, the silicon nitride between the word line 190 and the bit line is etched to form an isolation structure 200 of the flash memory device sharing the source line.
By comparing the required etching rate with the real-time etching rate and executing a second warm-up process to reduce the real-time etching rate or executing a first warm-up process to increase the real-time etching rate, active intervention and dynamic adjustment of the real-time etching rate of the etching machine are realized, so that the real-time etching rate of the etching machine meets the etching rate requirement of the etching process, the condition that the substrate of the bit line forming area 300 is etched by mistake or the silicon nitride residue is not etched sufficiently is avoided, the accuracy of the etching rate of the etching machine is improved, and the product yield is improved.
Example two
Referring to fig. 3, fig. 3 is a schematic diagram of a semiconductor structure of a word line sharing flash memory device according to a second embodiment of the present invention, where the word line sharing flash memory device generally includes: the structure comprises a substrate 400, a gate oxide layer 410 positioned on the substrate 400, a word line 500 positioned on the gate oxide layer 410, a floating gate polysilicon layer 420, an ONO film layer 430 and a control gate polysilicon layer 440 which are sequentially positioned on the gate oxide layer 410 at two sides of the word line 500, a silicon oxide layer 471 for isolating the word line 500 from the control gate polysilicon layer 440, a silicon nitride layer 472 and a tunneling oxide layer 480, a floating gate silicon nitride structure 450 positioned on the control gate polysilicon layer 440, and a side wall structure 460 positioned between the floating gate silicon nitride structure 450 and the silicon oxide layer 471. In the manufacturing process of the flash memory device sharing the word line, the sidewall structure 460 is formed by a self-aligned process, and since a wet process needs to be performed subsequently to remove and form the floating gate silicon nitride structure 450, but the sidewall structure 460 cannot be damaged, the sidewall structure 460 between the control gate polysilicon layer 440 and the word line 500 needs to be completely covered by the word line 500 to be protected, when the etching process of the sidewall structure 460 of the flash memory device sharing the source line is performed, the sidewall structure 460 needs a certain amount of over-etching so that the height of the sidewall structure 460 is slightly smaller than the height of the floating gate silicon nitride structure 450, but if the etching rate of an etching machine is too fast when the sidewall structure 460 is etched, the problem that the tunnel oxide layer 480 is over-etched to cause a pit defect when the word line 500 is not formed is caused.
In the second embodiment, the etching method in the etching process of the sidewall structure 460 of the flash memory device that shares the word line is specifically described next.
First step S10: initializing the etching parameters of the etching machine, specifically initializing the specific etching parameters in the etching process program loaded before power failure.
Second step S20: loading a corresponding process program according to an etching process and confirming the required etching rate of the etching process, wherein the process program comprises the following steps: an etching process, a first warm-up process, and a second warm-up process. Specifically, in this embodiment, the etching process of the sidewall structure 460 of the flash memory device sharing the word line is performed, and in this embodiment, the critical dimension of the sidewall structure 460 of the flash memory device sharing the word line in the width direction is 90 nm. Loading the side wall structure 460 etching process program of the flash memory device sharing the word line according to the side wall structure 460 etching process of the flash memory device sharing the word line, and confirming the etching requirement of the etching isolation structureAnd inputting the required etching rate into the etching machine. The required etching rate corresponding to the side wall structure 460 etching process of the flash memory device sharing the word line is
Third step S30: and acquiring the real-time etching rate of the etching machine.
Fourth step S40: and comparing the required etching rate with the real-time etching rate.
Fifth step S50: if the required etching rate is greater than the real-time etching rate, calling a first warm-up process program to execute a first warm-up process, and returning to execute the third step; if the required etching rate is less than the real-time etching rate, calling a second warm-up process program to execute a second warm-up process, and returning to execute the third step; and if the required etching rate is equal to the real-time etching rate, calling the etching process program to execute the etching process. Specifically, in the second warm-up process, the silicon on the surface of the control wafer is etched to change the environmental parameters in the etching chamber and the wafer contact bias voltage to reduce the real-time etching rate, wherein the environmental parameters in the etching chamber include but are not limited to the chamber gas pressure and the sidewall deposition composition; in the first warm-up process, the silicon nitride on the surface of the etching control wafer enables the generated polymer to be deposited on the inner wall surface of the etching chamber so as to change the plasma density in the etching chamber to increase the real-time etching rate. In this embodiment, since the sidewall structure 460 requires a certain amount of over-etching so that the height of the sidewall structure 460 is slightly less than the height of the floating gate silicon nitride structure 450, the required etching rate is easily greater than the real-time etching rate, and at this time, a second warm-up process is called to perform a second warm-up process, so as to etch the silicon on the surface of the control wafer to change the environmental parameters (such as the chamber pressure and the environmental parameters of the sidewall deposition composition) and the wafer contact bias voltage in the etching chamber to reduce the real-time etching rate. As shown in fig. 3, in the sidewall structure 460 etching process of the flash memory device sharing word lines, the silicon oxide between the control gate polysilicon layer 440 and the word lines 500 is etched to form the sidewall structure 460 of the flash memory device sharing word lines.
By comparing the required etching rate with the real-time etching rate and executing a second warming-up process to reduce the real-time etching rate, active intervention and dynamic adjustment of the real-time etching rate of the etching machine are realized, so that the real-time etching rate of the etching machine meets the etching rate requirement of the etching process, the condition that the tunneling oxide layer 480 is mistakenly etched is avoided, the accuracy of the etching rate of the etching machine is improved, and the product yield is improved.
In summary, the present invention provides an etching method, including: the first step is as follows: initializing; the second step is as follows: loading a corresponding process program according to an etching process and confirming the required etching rate of the etching process, wherein the process program comprises the following steps: an etching process, a first warm-up process and a second warm-up process; the third step: acquiring the real-time etching rate of an etching machine; the fourth step: comparing the required etching rate with the real-time etching rate; the fifth step: if the required etching rate is greater than the real-time etching rate, calling a second warm-up process program and returning to execute the third step; if the required etching rate is less than the real-time etching rate, calling a first warm-up process program and returning to execute the third step; and if the required etching rate is equal to the real-time etching rate, calling the etching process program. By comparing the required etching rate with the real-time etching rate and correspondingly executing different procedures, the active intervention and dynamic adjustment of the real-time etching rate of the etching machine are realized, so that the real-time etching rate of the etching machine meets the etching rate requirement of the etching process, the condition that the etching machine is mistakenly etched or insufficiently etched is avoided, the accuracy of the etching rate of the etching machine is improved, and the product yield is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. An etching method, comprising:
the first step is as follows: initializing etching parameters of an etching machine;
the second step is as follows: loading a corresponding process program according to an etching process and confirming the required etching rate of the etching process, wherein the process program comprises the following steps: an etching process, a first warm-up process and a second warm-up process;
the third step: acquiring the real-time etching rate of an etching machine;
the fourth step: comparing the required etching rate with the real-time etching rate;
the fifth step: if the required etching rate is greater than the real-time etching rate, calling a first warm-up process program to execute a first warm-up process, and returning to execute the third step; if the required etching rate is less than the real-time etching rate, calling a second warm-up process program to execute a second warm-up process, and returning to execute the third step; and if the required etching rate is equal to the real-time etching rate, calling the etching process program to execute the etching process.
2. The etching method according to claim 1, wherein in the second warm-up process, silicon on the surface of the control wafer is etched to change an environmental parameter and a wafer contact bias voltage in the etching chamber so as to reduce the real-time etching rate, wherein the environmental parameter in the etching chamber comprises: chamber gas pressure and sidewall deposition composition.
3. The etching method according to claim 1, wherein in the first warm-up process, the silicon nitride on the surface of the etching control wafer is etched so that the generated polymer is deposited on the inner wall surface of the etching chamber to change the plasma density in the etching chamber, thereby increasing the real-time etching rate.
4. The etching method according to claim 1, wherein the etching process comprises an isolation structure etching process of a flash memory device sharing a source line and a side wall structure etching process of a flash memory device sharing a word line.
5. The etching method according to claim 4, wherein in the process of etching the isolation structure of the flash memory device sharing the source line, the silicon nitride positioned between the word line and the bit line is etched to form the isolation structure of the flash memory device sharing the source line.
6. The etching method according to claim 5, wherein in the etching process of the isolation structure of the flash memory device sharing the source line, the required etching rate is
7. The etching method according to claim 5, wherein the critical dimension of the isolation structure of the flash memory device sharing the source line in width is 0.12 um.
8. The etching method according to claim 4, wherein in the etching process of the sidewall structure of the flash memory device sharing the word line, the silicon oxide between the control gate and the word line is etched to form the sidewall structure of the flash memory device sharing the word line.
9. The etching method according to claim 8, wherein in the etching process of the sidewall structure of the flash memory device sharing the word line, the required etching rate is
10. The etching method according to claim 8, wherein the critical dimension of the sidewall structure of the flash memory device sharing the word line in width is 90 nm.
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| CN116288275B (en) * | 2023-03-20 | 2024-09-10 | 上海华力集成电路制造有限公司 | Process chamber warming method of titanium aluminum deposition machine |
| CN116884884B (en) * | 2023-09-06 | 2023-11-24 | 粤芯半导体技术股份有限公司 | Warming-up sheet for grid side wall ICP etching, preparation method thereof and warming-up method |
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| US20150126036A1 (en) * | 2013-11-05 | 2015-05-07 | Tokyo Electron Limited | Controlling etch rate drift and particles during plasma processing |
| KR20160124992A (en) * | 2015-04-20 | 2016-10-31 | 삼성전자주식회사 | apparatus for manufacturing a substrate and ceramic film coating method of the same |
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| CN101055841A (en) * | 2006-04-12 | 2007-10-17 | 中芯国际集成电路制造(上海)有限公司 | Making method of semiconductor memory part |
| CN101894737A (en) * | 2009-05-19 | 2010-11-24 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Control method of cavity environment |
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