CN101055841A - Making method of semiconductor memory part - Google Patents
Making method of semiconductor memory part Download PDFInfo
- Publication number
- CN101055841A CN101055841A CN 200610025651 CN200610025651A CN101055841A CN 101055841 A CN101055841 A CN 101055841A CN 200610025651 CN200610025651 CN 200610025651 CN 200610025651 A CN200610025651 A CN 200610025651A CN 101055841 A CN101055841 A CN 101055841A
- Authority
- CN
- China
- Prior art keywords
- wafer
- etching
- reative cell
- side wall
- etch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Drying Of Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor device, after periodically maintaining a reaction chamber, the method comprises: peforming adaptability adjustment on the reaction chamber by a test wafer; solely executing an etching process in the reaction chamber by the test wafer; detecting an etching speed; adjusting an etching process time for formally producting wafers according to the etching speed. The method of the invention is capable of controlling a lateral wall interlayer in a desired width, the error is controlled in a range of +/-1, and an adaptability adjustment time desired after periodically maintaining the reaction chamber is reduced, production efficiency and nondefective rate are increased, production cost is reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method that in SONOS (silicon-oxide-nitirde-oxide-silicon silicon-oxide-nitride--oxide-silicon) memory device, has the wall (offset spacer) of buffer action.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, and semiconductor wafer develops towards higher component density, high integration direction.In the semiconductor storage unit of for example DRAM, SONOS (silicon-oxide-nitirde-oxide-silicon silicon-oxide-nitride--oxide-silicon) memory device is widely used with its good scaled characteristic as low-voltage high density non-volatility semiconductor flush memory device of new generation.Core texture is oxide layer-nitride layer-oxide layer (oxide-nitirde-oxide ONO) the laminated dielectric layer structure that forms between polysilicon gate and surface of silicon in the SONOS device, each layer thickness of ONO has only about 10nm, and it is shorter that length becomes, and charge carrier is stored in the nitration case.Adopt the ONO layer of thinner thickness, can strengthen the coupling of gate electrode and channel carrier, make the arithmetic speed of device faster.
Application number is that 01123714.7 Chinese patent application has been introduced the method that a kind of CMOS of utilization technology is made ONO dielectric layer in the SONOS memory device grid structure.Fig. 1 is a SONOS memory device ONO dielectric layer structure profile.Here, for convenience of explanation, be example with the memory cell of NMOS type, for PMOS, forming process is similar on the principle.As shown in Figure 1, at first utilize photoetching and etching technics to define active region, utilize ion implantation again in active area, n type impurity is injected into forms source region 12 and drain region 10 in the p type substrate 10 at substrate surface.Between source region 12 and drain region 14, limit channel region 16.Subsequently, deposit tunnel oxidation layer 18a and silicon nitride layer (Si successively on the channel region 16 of substrate 10
3N
4) 18b, deposit one deck barrier oxide layer 18c again on silicon nitride layer 18b, thus form the ono dielectric laminated construction of forming by silica-silicon-nitride and silicon oxide (oxide-nitirde-oxide) 18.Tunnel oxidation layer 18a contacts with drain region 14 with source region 12.Silicon nitride layer 18b is the trap bit with predetermined density.
Then, deposit spathic silicon (Polysilicon) layer 116 covers barrier oxide layer 18c, deposit metal silicide (Silicide) layer 118 again and cover polysilicon layer 116, utilize photoetching and etch process definition polysilicon layer 116 and metal silicide layer 118 equally, and form grid 120, and expose the tunnel oxidation layer 18a of ONO structure.Subsequently, at grid 120 both sides sidewalls the grow oxide layer of about 25 of a layer thickness, for example silicon dioxide (SiO
2) 121.Utilize then as method (Chemical Vapor Deposition with chemical vapor deposition; CVD) deposit layer of material layer covers ONO structure 18, oxide layer 121 and grid 120, and this material layer can be four oxygen ethyl silicate (Tetra-Ethyl-Ortho-Silicate; TEOS) or silicon nitride (Si
3N
4) etc., form sidewall spacers layer (offset spacer) 122 thereby remove the material layer on grid 120 surfaces then and return the material layer of carving oxide layer 121 surfaces.Then, the structure of being formed with clearance layer 122 and grid 120 is a mask, carrying out ion injects, for example, with phosphorus (P) or to the higher arsenic (As) of the solid solubility of silicon (Si) is ion source (Ion Source), high concentration and the darker heavy doping (Heavy Doping) of the degree of depth are carried out in source region 12 and drain region 16 to substrate 10, and low concentration and more shallow low-doped (LowDoping) of the degree of depth are carried out in zone 13 and 15, prevent the LDD (low doped drain region) of short-channel effect with formation.Anneal then and form source electrode and drain electrode to activate the foreign ion that injects.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of semiconductor storage unit, this method is when forming side wall spacers, control the width of side wall spacers by reative cell being carried out accommodation (season) and strict control etch period, to solve the unmanageable problem of side wall spacers width that exists in the prior art.
For achieving the above object, the manufacture method of a kind of semiconductor device provided by the invention, after reative cell carried out periodic maintenance, described method comprised:
A utilizes test piece that reative cell is carried out accommodation;
B utilizes the processing step of the testing wafer isolated operation etching side wall spacers with grid structure in reative cell;
C determines the etch rate of side wall spacers;
The etch period of side wall spacers when d formally produces wafer according to described etch rate adjustment.
Increase if detect etch rate, then when the side wall spacers of the formal wafer of etching, shorten etch period.Reduce if detect etch rate, then when the etching of formal wafer, prolong etch period.
The test piece quantity of described step a is the 5-10 sheet.
The testing wafer quantity of described step b is the 1-2 sheet.
Described accommodation identical processing step when comprising with formal wafer manufacture.
Described etching technics is a reactive ion etching process.
Have the manufacture method of the another kind of semiconductor device of identical or relevant art feature with preceding method of the present invention, after reative cell carried out periodic maintenance, described method comprised:
A utilizes test piece that reative cell is carried out accommodation;
B utilizes testing wafer isolated operation etching technics in reative cell;
C detection etch speed;
D formally produces the etch period of wafer according to described etch rate adjustment.
Increase if detect etch rate, then when the etching of formal wafer, shorten etch period.Reduce if detect etch rate, then when the etching of formal wafer, prolong etch period.
The test piece quantity of described step a is the 5-10 sheet.
The testing wafer quantity of described step b is the 1-2 sheet.
Described accommodation identical processing step when comprising with formal wafer manufacture.
Compared with prior art, the present invention has the following advantages:
The width of side wall spacers influences the characteristic of light doping section (LDD) in NMOS and the PMOS device active region to a great extent, and thereby LDD can suppress the drain saturation current of short channel effect controlling filed effect transistor, and therefore the width of control side wall spacers is very important in the process of making field-effect transistor.The purpose of the manufacture method of semiconductor storage unit of the present invention mainly is the width of control side wall spacers, and it is remained in the specific scope.After reative cell carries out periodic maintenance, method of the present invention is promptly controlled washer by reasonable input test piece, just the quantity of exposed wafer (BareSilicon Wafer) is carried out the test piece operation of accommodation to reative cell, to eliminate the destabilizing factor of reative cell, on the one hand by the etch period of mensuration testing wafer side wall spacers and the relation of width, adjust the etch period of formal wafer side wall spacers, this is the application of the high model FEEDBACK CONTROL of standard.Guarantee the side wall spacers etching technics of the wafer of one batch of isolated operation in the reative cell on the other hand, and not with other batch or other operation mixed running, reach the purpose of control side wall spacers width.Method of the present invention can be controlled at side wall spacers required width, its error is controlled in ± scope of 1 in, and shortened because necessary institute accommodation time after the periodic maintenance of reative cell has guaranteed manufacturing schedule, improve yields, reduced production cost.
Description of drawings
Fig. 1 is a SONOS memory device ONO dielectric layer structure profile;
Fig. 2 is the flow chart of the manufacture method of semiconductor storage unit of the present invention;
Fig. 3 is the flow chart of semiconductor making method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The present invention has disclosed a kind of manufacture method of semiconductor gate electrode structure, and the width of 90nm and following SONOS device side wall wall is had very high control precision.
CMOS technology has entered the following process node of 90nm, and width and its variation of control side wall spacers become more and more important.The change of side wall spacers width and/or big variation will cause the marked change of NMOS and PMOS device drain saturation current, thereby influence device performance.In the process node below 90nm, the width of side wall spacers is controlled in about 85 .The present invention adopt high dielectric constant material for example silicon nitride (Si3N4) as side wall spacers, to suppress leakage current and to improve drive current.So thin side wall spacers is quite responsive to the environmental condition of reative cell, particularly after reative cell just finishes periodic maintenance.And, because the restriction of reative cell resource, the etching of ONO side wall spacers and other operation (for example the etching of ONO lamination etc.) are usually moved in same reative cell, this in reative cell the mixed running of operation have a strong impact on the etch rate of side wall spacers, cause the extremely unstable of side wall spacers width.
Method of the present invention makes full use of the resource of existing reative cell under the prerequisite that guarantees the raising yields, adopt test piece promptly to control washer, the just exposed mode that wafer (BareSilicon Wafer) carries out accommodation to reative cell and isolated operation testing wafer side wall spacers etching technics combines in reative cell overcomes the uncertain factor of reaction chamber environment condition, reaches the purpose of the etching precision of control side wall spacers.Describe in detail below.
The basis of semiconductor manufacturing industry is to carry out polytechnic equipment, and for example lithographic equipment and etching apparatus etc. because equipment itself is the system of a complexity, needed equipment is carried out periodic maintenance after operation a period of time.With the plasma etching equipment is example, be provided with the conductivity partition wall in the vacuum tank of reative cell, the conductivity partition wall is two spaces with the vacuum tank internal insulation, it is that film forming is handled the space that an interior volume forms the plasma span, another space of having disposed high-frequency electrode, internal configurations has the chip retaining cushion of bearing wafer, this reative cell with labyrinth is carried out periodic maintenance be very important.
Method, semi-conductor device manufacturing method of the present invention carries out accommodation to reative cell after reative cell carries out periodic maintenance.So-called accommodation, it is exactly the test piece of in reative cell, throwing in the 5-10 sheet, this test piece is the control washer, promptly exposed wafer (BareSilicon Wafer), adopt 5 in the present embodiment, the operation and the formal identical technology of manufacturing of wafer (comprising the SONOS device) are comprising the etching technics of side wall spacers.Accommodation in this way reduces the influence by the change oppose side wall wall etching width of the environmental condition of bringing after the periodic maintenance effectively.In addition, when the formal wafer of actual production, adopt the mode of non-mixed running, just at the etching technics of the inner isolated operation side wall spacers of reative cell.Non-mixed running when before formal etched wafer reative cell being carried out accommodation and formal production can be controlled at the etching precision of side wall spacers ± scope of 1 in.Fig. 2 is the graph of relation of wafer manufacture batch and side wall spacers width error, as shown in Figure 2, abscissa is represented different wafer batch, ordinate is represented width error, three points in the circle are illustrated in through three wafers carrying out non-hybrid technique operation in the reative cell of accommodation batch, as can be seen from Figure, the width error of the side wall spacers of three batch wafers representing of three points in the circle all is controlled in the 1 scope.
After the periodic maintenance of reative cell, a lot of parameters have variation to a certain degree, and practice shows that these variations will cause the remarkable increase of etching rate.Therefore be etched thinlyyer at same time madial wall wall.And the change of this temporary transient process conditions to rely on test piece accommodation and non-mixed running be insurmountable.Therefore, method, semi-conductor device manufacturing method of the present invention can reduce even eliminate overetch owing to the change oppose side wall wall of process conditions after the reative cell periodic maintenance by the method that reduces etch period, and overall dimension that can the oppose side wall wall causes any negative effect.Method of the present invention drops into 1-2 built-in testing wafer after the reative cell periodic maintenance, this testing wafer is the wafer identical with formal wafer, in reative cell, try out, whether the etch technological condition with ONO side wall spacers on the detection reaction back-to-back test examination wafer exists change, and just whether etch rate increases.Etch rate is determined by the width of measurement side wall spacers and the relation of etch period.If etch rate increases, then when the side wall spacers of the formal wafer of etching, reduce etch period.Reduce if detect etch rate, then when the etching of formal wafer, prolong etch period.By the method for this FEEDBACK CONTROL, improved the reliability of reative cell, with the needs of accommodate wafer volume production.
Fig. 3 is the flow chart of semiconductor making method of the present invention.The manufacture method of semiconductor device of the present invention after reative cell carries out periodic maintenance, is at first promptly controlled the just exposed wafer of catch with test piece reative cell is carried out accommodation; In reative cell, utilize the processing step of testing wafer isolated operation etching side wall spacers then with grid structure; Next the width of measuring side wall spacers detects the etch rate of side wall spacers; The etch period of side wall spacers when formally producing wafer according to described etch rate adjustment.Detecting etch rate increases, and then shortens etch period when the side wall spacers of the formal wafer of etching.Reduce if detect etch rate, then when the etching of formal wafer, prolong etch period.Wherein test piece quantity is the 5-10 sheet, and testing wafer quantity is the 1-2 sheet.Accommodation identical processing step when comprising with formal wafer manufacture, etching technics wherein is a reactive ion etching process.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art; without departing from the spirit and scope of the present invention; all can do various changes and modification; after reative cell carries out periodic maintenance; the etching at other position of wafer, comprise except etching technics; other technology is the operation of depositing technics for example, all can adopt of the present invention reative cell is carried out accommodation and technological parameter is carried out the thought of FEEDBACK CONTROL, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1, a kind of manufacture method of semiconductor device, after reative cell carried out periodic maintenance, described method comprised:
A utilizes test piece that reative cell is carried out accommodation;
B utilizes testing wafer isolated operation etching technics in reative cell;
C detection etch speed;
D formally produces the etch period of wafer according to described etch rate adjustment.
2, the method for claim 1 is characterized in that: increase if detect etch rate, then shorten etch period when the etching of formal wafer, reduce if detect etch rate, then prolong etch period when the etching of formal wafer.
3, the method for claim 1 is characterized in that: the test piece quantity of described step a is the 5-10 sheet.
4, the method for claim 1 is characterized in that: the testing wafer quantity of described step b is the 1-2 sheet.
5, the method for claim 1 is characterized in that: described accommodation identical processing step when comprising with formal wafer manufacture.
6, the method for claim 1 is characterized in that: described etching technics is a reactive ion etching process.
7, a kind of manufacture method of semiconductor device, after reative cell carried out periodic maintenance, described method comprised:
A utilizes test piece that reative cell is carried out accommodation;
B utilizes the processing step of the testing wafer isolated operation etching side wall spacers with grid structure in reative cell;
C determines the etch rate of side wall spacers;
The etch period of side wall spacers when d formally produces wafer according to described etch rate adjustment.
8, method as claimed in claim 7 is characterized in that: increase if detect etch rate, then shorten etch period when the side wall spacers of the formal wafer of etching, reduce if detect etch rate, then prolong etch period when the etching of formal wafer.
9, method as claimed in claim 7 is characterized in that: the test piece quantity of described step a is the 5-10 sheet.
10, method as claimed in claim 7 is characterized in that: the testing wafer quantity of described step b is the 1-2 sheet.
11, method as claimed in claim 7 is characterized in that: described accommodation identical processing step when comprising with formal wafer manufacture.
12, method as claimed in claim 7 is characterized in that: described etching technics is a reactive ion etching process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100256511A CN100468650C (en) | 2006-04-12 | 2006-04-12 | Making method of semiconductor memory part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100256511A CN100468650C (en) | 2006-04-12 | 2006-04-12 | Making method of semiconductor memory part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101055841A true CN101055841A (en) | 2007-10-17 |
| CN100468650C CN100468650C (en) | 2009-03-11 |
Family
ID=38795585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100256511A Active CN100468650C (en) | 2006-04-12 | 2006-04-12 | Making method of semiconductor memory part |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100468650C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044482A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming groove |
| CN102315112A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Etching method for stacked metal gate |
| CN102412293A (en) * | 2010-09-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof |
| CN101673682B (en) * | 2009-09-25 | 2012-07-04 | 上海宏力半导体制造有限公司 | Method for etching wafer |
| CN106155005A (en) * | 2015-04-22 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The managing and control system of a kind of board process parameter skew and method |
| CN110534427A (en) * | 2019-09-06 | 2019-12-03 | 上海华虹宏力半导体制造有限公司 | Lithographic method |
-
2006
- 2006-04-12 CN CNB2006100256511A patent/CN100468650C/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673682B (en) * | 2009-09-25 | 2012-07-04 | 上海宏力半导体制造有限公司 | Method for etching wafer |
| CN102044482A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming groove |
| CN102044482B (en) * | 2009-10-20 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Method for forming groove |
| CN102412293A (en) * | 2010-09-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof |
| CN102315112A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Etching method for stacked metal gate |
| CN102315112B (en) * | 2011-09-28 | 2016-03-09 | 上海华虹宏力半导体制造有限公司 | The lithographic method of stacked metal gate |
| CN106155005A (en) * | 2015-04-22 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The managing and control system of a kind of board process parameter skew and method |
| CN106155005B (en) * | 2015-04-22 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of managing and control system and method for the offset of board process parameter |
| CN110534427A (en) * | 2019-09-06 | 2019-12-03 | 上海华虹宏力半导体制造有限公司 | Lithographic method |
| CN110534427B (en) * | 2019-09-06 | 2021-11-12 | 上海华虹宏力半导体制造有限公司 | Etching method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100468650C (en) | 2009-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20160125870A (en) | Semiconductor structure and manufacturing method thereof | |
| CN100468650C (en) | Making method of semiconductor memory part | |
| CN100375269C (en) | Semiconductor device and method for manufacturing thereof | |
| CN1713395A (en) | Semiconductor device capable of threshold voltage adjustment by applying an external voltage and its manufacture | |
| CN105448726A (en) | Method for forming fin field effect transistor | |
| KR100607346B1 (en) | Method of manufacturing a flash memory device | |
| US20210336014A1 (en) | Semiconductor device and method for manufacturing same | |
| US20030139025A1 (en) | Method of forming a MOS transistor with improved threshold voltage stability | |
| KR20220016788A (en) | Conformal oxidation for gate all around nanosheet i/o device | |
| US9112012B2 (en) | Transistor device and fabrication method | |
| US6429052B1 (en) | Method of making high performance transistor with a reduced width gate electrode and device comprising same | |
| CN110767658A (en) | Forming method of flash memory device | |
| CN102543744B (en) | Transistor and manufacturing method thereof | |
| US7282420B2 (en) | Method of manufacturing a flash memory device | |
| CN104347507B (en) | The forming method of semiconductor devices | |
| CN1627503A (en) | Memory device and method of manufacturing the same | |
| CN111613584A (en) | Semiconductor device and manufacturing method thereof | |
| CN107706153B (en) | Method for forming semiconductor device | |
| US7893508B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN101989548B (en) | Semiconductor device and manufacturing method thereof | |
| CN111769043B (en) | Forming method of gate dielectric layer, semiconductor structure and forming method thereof | |
| US20180082999A1 (en) | Integrated circuits with high voltage devices and methods for producing the same | |
| CN111599759B (en) | Semiconductor device and manufacturing method thereof | |
| CN103579077B (en) | A kind of semiconductor structure and forming method thereof | |
| CN102543704B (en) | Forming method of grid oxide layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |