CN110534427A - Lithographic method - Google Patents
Lithographic method Download PDFInfo
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- CN110534427A CN110534427A CN201910842922.XA CN201910842922A CN110534427A CN 110534427 A CN110534427 A CN 110534427A CN 201910842922 A CN201910842922 A CN 201910842922A CN 110534427 A CN110534427 A CN 110534427A
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- etch rate
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The present invention provides a kind of lithographic methods, comprising: first step: initialization；Second step: corresponding technique formula is loaded according to etching technics, and confirms the demand etch rate of the etching technics；Third step: the real time etch rate of etching machine bench is obtained；Four steps: the size of the demand etch rate and the real time etch rate；5th step: it if the demand etch rate is greater than the real time etch rate, calls the first warming-up technique formula and returns to execution third step；If the demand etch rate is less than the real time etch rate, calls the second warming-up technique formula and return to execution third step；If the demand etch rate is equal to the real time etch rate, the etching technics formula is called.By comparing the size of the demand etch rate and the real time etch rate, etching machine bench is corresponding to execute different processes, and the pro-active intervention and dynamic for realizing the real time etch rate of etching machine bench adjust.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of lithographic method.
Background technique
Etching machine bench is the semiconductor research and development and production equipment of etching technics indispensability, wherein the etch rate of etching machine bench
One of the important parameter of etching technics, the indoor temperature of etch chamber, etching cavity inner wall polymer deposit amount, etch chamber
The factors such as the indoor gas pressure of density and etch chamber of indoor plasma are all the etch rates for influencing etching machine bench
Factor.
In etching process, the etch rate needed for the real time etch rate and etching technics of etching machine bench has larger
When deviation, etching machine bench is generally difficult to timely pro-active intervention and adjusts the size of real time etch rate, if etching machine bench is real-time
Etch rate is too fast perhaps excessively slow, and the etch thicknesses that will lead to equivalent layer or structure are excessive or too small, to cause product
Defect increases the generation rate of defective products.
Therefore, it is necessary to a kind of lithographic methods pro-active intervention simultaneously dynamically to adjust etching machine bench in etching process
The requirement of etch rate needed for real time etch rate makes it meet etching technics.
Summary of the invention
The purpose of the present invention is to provide a kind of lithographic methods, to solve not intervening automatically simultaneously in etching process
The problem of real time etch rate of dynamic adjustment etching machine bench.
In order to solve the above technical problems, the present invention provides a kind of lithographic method, comprising:
First step: the etching parameters of etching machine bench are initialized；
Second step: loading corresponding technique formula according to etching technics, and confirms that the demand of the etching technics is carved
Lose rate, wherein the technique formula includes: etching technics formula, the first warming-up technique formula and the second warming-up technique formula；
Third step: the real time etch rate of etching machine bench is obtained；
Four steps: the size of the demand etch rate and the real time etch rate；
5th step: if the demand etch rate is greater than the real time etch rate, the first warming-up technique formula is called
To execute the first warming-up technique, and return to execution third step；If the demand etch rate is less than the real time etch rate,
It calls the second warming-up technique formula to execute the second warming-up technique, and returns to execution third step；If the demand etch rate
Equal to the real time etch rate, call the etching technics formula to execute etching technics.
Optionally, it in the lithographic method, in the first warming-up technique, etches the silicon on control wafer surface and is carved with changing
The indoor environmental parameter of chamber and wafer contacts bias are lost, to reduce the real time etch rate, wherein the indoor institute of etch chamber
Stating environmental parameter includes: cavity air pressure and side wall deposit ingredient.
Optionally, in the lithographic method, in the second warming-up technique, the silicon nitride on etching control wafer surface makes
The polymer deposits of generation in the inner wall surface of etching cavity to change the plasma density in etching cavity, to increase institute
State real time etch rate.
Optionally, in the lithographic method, the etching technics includes the isolation structure of the flush memory device of shared source line
The sidewall structure etching technics of etching technics and the flush memory device of shared word line.
Optionally, in the lithographic method, in the isolation structure etching technics of the flush memory device of the shared source line,
The silicon nitride between wordline and bit line is etched to form the isolation structure of the flush memory device of shared source line.
Optionally, in the lithographic method, in the isolation structure etching technics of the flush memory device of the shared source line,
The demand etch rate is
Optionally, in the lithographic method, the pass of the isolation structure of the flush memory device of the shared source line on the width
Key is having a size of 0.12um.
Optionally, in the lithographic method, in the sidewall structure etching technics of the flush memory device of the shared word line,
The silica between control gate and wordline is etched to form the sidewall structure of the flush memory device of shared word line.
Optionally, in the lithographic method, in the sidewall structure etching technics of the flush memory device of the shared word line,
The demand etch rate is
Optionally, in the lithographic method, the sidewall structure of the flush memory device of the shared word line is on the width
Critical size is 90nm.
To sum up, the present invention provides a kind of lithographic method, comprising: first step: initialization；Second step: according to etching work
Skill loads corresponding technique formula, and confirms the demand etch rate of the etching technics, wherein the technique formula packet
It includes: etching technics formula, the first warming-up technique formula and the second warming-up technique formula；Third step: the reality of etching machine bench is obtained
When etch rate；Four steps: the size of the demand etch rate and the real time etch rate；5th step: if
The demand etch rate is greater than the real time etch rate, calls the first warming-up technique formula and returns to execution third step；
If the demand etch rate is less than the real time etch rate, calls the second warming-up technique formula and return to execution third step
Suddenly；If the demand etch rate is equal to the real time etch rate, the etching technics formula is called.By comparing the need
The size of etch rate Yu the real time etch rate, and the process that corresponding execution is different are asked, the real-time of etching machine bench is realized
The pro-active intervention and dynamic of etch rate adjust, so that the real time etch rate of etching machine bench meets the etch rate of etching technics
Demand avoids etching machine bench and accidentally etches or etch insufficient situation, improves the accurate of the etch rate of etching machine bench
Property, improve product yield.
Detailed description of the invention
Fig. 1 is the lithographic method flow chart of the embodiment of the present invention one；
Fig. 2 is the semiconductor structure schematic diagram of the flush memory device of the shared source line of the prior art of the embodiment of the present invention one；
Fig. 3 is the semiconductor structure schematic diagram of the flush memory device of the shared word line of the prior art of the embodiment of the present invention two；
Wherein, description of symbols:
100- substrate, 110- gate oxide, 120- floating gate polysilicon layer, 130-ONO film layer, 140- control gate polysilicon
Layer, the first side wall of 150-, the second side wall of 160-, the source 170- line, 180- third side wall, 190- wordline, 200- isolation structure, 210-
Tunnel oxide, 300- bit line form area；
400- substrate, 410- gate oxide, 420- floating gate polysilicon layer, 430-ONO film layer, 440- control gate polysilicon
Layer, 450- floating gate silicon nitride structure, 460- sidewall structure, 471- silicon oxide layer, 472- silicon nitride layer, 480- tunnel oxide,
500- wordline.
Specific embodiment
Lithographic method proposed by the present invention is described in further detail below in conjunction with the drawings and specific embodiments.Under
Face explanation and claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplification
Form and use non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.In addition, attached
Scheme a part that shown structure is often practical structures.Particularly, the emphasis that each attached drawing needs to show is different, sometimes
Using different ratios.
Embodiment one
The present invention provides a kind of lithographic method, is the lithographic method process of the embodiment of the present invention one with reference to Fig. 1 and Fig. 2, Fig. 1
Figure, Fig. 2 is the semiconductor structure schematic diagram of the flush memory device of the shared source line of the prior art of the embodiment of the present invention one.
As shown in Fig. 2, the flush memory device of the shared source line generally includes: substrate 100, on the substrate 100
Source line 170, the gate oxide 110 being sequentially located on the substrate 100 of 170 two sides of source line, floating gate polysilicon layer 120, ONO film
Layer 130 and control gate polysilicon layer 140, the isolation source line 170 and the control gate polysilicon layer 140 the second side wall 160,
Positioned at it is described control gate polysilicon layer 140 on and far from 170 side of source line the first side wall 150, be located at the floating gate polycrystalline
On silicon layer 120 and it is located at the third side wall 180 of 150 side of the first side wall, is located on the substrate 100 and is located at the third
The tunnel oxide 210 of 180 side of side wall, the wordline 190 on the tunnel oxide 210 and be located at 190 side of wordline
Isolation structure 200, in addition, be located at the isolation structure 200 far from 190 side of wordline on the substrate 100 also shape
At there is bit line to form area 300, the surface that the bit line forms area 300 will form bit line in the subsequent process.In shared source line
In the process for making of flush memory device, the material of the isolation structure 200 is usually silicon nitride, is forming bit line and wordline
Before isolation structure 200 between 190, due to forming the isolation structure 200 using self-registered technology, so the word
There are certain differences in height for third side wall 180 between line 190 and control gate polysilicon layer 120.Execute the flash memory of shared source line
When 200 etching technics of isolation structure of device, on the one hand, if the etch rate of etching machine bench is too fast, will lead to the bit line
There is the problem of pit by over etching in the substrate 100 of formation 300 position of area；On the other hand, if the reality of board
When etch rate it is too low, then will lead to the wordline 190 top still to form the isolation structure 200 during generate
Silicon nitride residue, to influence subsequent metallization process.
Next the specific institute introduced in the etching technics for executing the isolation structure 200 of flush memory device of the shared source line
State lithographic method.
First step S10: initializing the etching parameters of etching machine bench, specifically, what is loaded before initialization power down is all
Specific etching parameters in incoherent etching technics formula, wherein the etching parameters of etching machine bench may include but unlimited
It is main in etch rate, etching deviation, selection ratio, uniformity and Etching profile etc. parameter, lithographic method of the present invention
For etch rate, this etching parameters does specific improvement.
Second step S20: corresponding technique formula is loaded according to etching technics, and confirms the demand of the etching technics
Etch rate, wherein the technique formula includes: etching technics formula, the first warming-up technique formula and the second warming-up technique journey
Formula.Specifically, the etching technics includes the etching technics and shared word line of the isolation structure of the flush memory device of shared source line
The sidewall structure etching technics of flush memory device, what the present embodiment executed is the isolation structure of the flush memory device of the shared source line
200 etching technics, in the present embodiment, the crucial ruler of the isolation structure 200 of the flush memory device of the shared source line on the width
Very little is 0.12um.The shared source line is loaded according to 200 etching technics of isolation structure of the flush memory device of the shared source line
The isolation structure etching technics formula of flush memory device, and confirm the demand etch rate of etching isolation structure, in the etching machine
The demand etch rate is inputted in platform.Wherein, 200 etching technics of isolation structure of the flush memory device of the shared source line is corresponding
The demand etch rate be
Third step S30: the real time etch rate of etching machine bench is obtained.
Four steps S40: the size of the demand etch rate and the real time etch rate.
5th step S50: if the demand etch rate is greater than the real time etch rate, the first warming-up technique journey is called
Formula returns to execution third step to execute the first warming-up technique；If the demand etch rate is less than the real-time etching speed
Rate calls the second warming-up technique formula to execute the second warming-up technique, and returns to execution third step；If the demand etching speed
Rate is equal to the real time etch rate, calls the etching technics formula to execute etching technics.Specifically, when the demand is carved
When losing rate greater than the real time etch rate, in the first warming-up technique, the silicon on control wafer surface is etched to change etching
The indoor environmental parameter of chamber and wafer contacts bias reduce the real time etch rate, wherein the indoor ring of etch chamber
Border parameter includes but is not limited to cavity air pressure and side wall deposit ingredient；When the demand etch rate is less than the real-time etching
When rate, in the second warming-up technique, the silicon nitride on etching control wafer surface makes the polymer deposits generated in etch chamber
The inner wall surface of room increases the real time etch rate to change the plasma density in etching cavity.When the demand is carved
When losing rate equal to the real time etch rate, as shown in Fig. 2, the isolation structure etching of the flush memory device in the shared source line
In technique, the silicon nitride between wordline 190 and bit line is etched to form the isolation structure of the flush memory device of shared source line
200。
By comparing the demand etch rate and the real time etch rate size, and execution the first warming-up technique with
Reduce the real time etch rate or execute the second warming-up technique to increase the real time etch rate, realizes etching machine bench
Real time etch rate pro-active intervention and dynamic adjust so that the real time etch rate of etching machine bench meets the quarter of etching technics
Rate requirement is lost, the substrate for avoiding bit line formation area 300 is accidentally etched or silicon nitride residue etches insufficient situation, mentions
The high accuracy of the etch rate of etching machine bench, improves product yield.
Embodiment two
Referring to FIG. 3, Fig. 3 is the semiconductor junction of the flush memory device of the shared word line of the prior art of the embodiment of the present invention two
The flush memory device of structure schematic diagram, the shared word line generally includes: substrate 400, the gate oxide on the substrate 400
410, the wordline 500 on the gate oxide 410, be sequentially located at it is floating on the gate oxide 410 of 500 two sides of wordline
Gate polysilicon layer 420, ONO film layer 430 and control gate polysilicon layer 440, the isolation wordline 500 and the control gate polysilicon
Silicon oxide layer 471, silicon nitride layer 472 and the tunnel oxide 480 of layer 440, floating on the control gate polysilicon layer 440
Grid silicon nitride structure 450 and the sidewall structure between the floating gate silicon nitride structure 450 and the silicon oxide layer 471
460.In the process for making of the flush memory device of shared word line, sidewall structure 460 is formed by self-registered technology, due to rear
It is continuous to need to be implemented wet processing to form floating gate silicon nitride structure 450 to remove, but the sidewall structure 460 cannot be damaged again
It is bad, so the needs of the sidewall structure 460 between control gate polysilicon layer 440 and wordline 500 are covered completely by the wordline 500
When covering to protect, therefore executing 460 etching technics of sidewall structure of flush memory device of shared source line, the sidewall structure
460 height for needing a certain amount of over etching that the height of the sidewall structure 460 is made to be slightly less than the floating gate silicon nitride structure 450
Degree, if but when etching the sidewall structure 460, the etch rate of etching machine bench is too fast, then will lead to not formed described
When wordline 500, there is the problem of pit defect by over etching in tunnel oxide 480.
In example 2, next specific to introduce 460 quarter of sidewall structure for executing the flush memory device of the shared word line
The lithographic method in etching technique.
First step S10: initializing the etching parameters of etching machine bench, specifically, the etching loaded before initialization power down
Specific etching parameters in technique formula.
Second step S20: corresponding technique formula is loaded according to etching technics, and confirms the demand of the etching technics
Etch rate, wherein the technique formula includes: etching technics formula, the first warming-up technique formula and the second warming-up technique journey
Formula.Specifically, the present embodiment execute be the shared word line flush memory device 460 etching technics of sidewall structure, in this reality
It applies in example, the critical size of the sidewall structure 460 of the flush memory device of the shared word line on the width is 90nm.According to described total
The sidewall structure 460 for enjoying the flush memory device of 460 etching technics of the sidewall structure load shared word line of the flush memory device of wordline etches
Technique formula, and confirm the demand etch rate of etching isolation structure, the demand etching speed is inputted in the etching machine bench
Rate.Wherein, the corresponding demand etch rate of 460 etching technics of sidewall structure of the flush memory device of the shared word line is
Third step S30: the real time etch rate of etching machine bench is obtained.
Four steps S40: the size of the demand etch rate and the real time etch rate.
5th step S50: if the demand etch rate is greater than the real time etch rate, the first warming-up technique journey is called
Formula returns to execution third step to execute the first warming-up technique；If the demand etch rate is less than the real-time etching speed
Rate calls the second warming-up technique formula to execute the second warming-up technique, and returns to execution third step；If the demand etching speed
Rate is equal to the real time etch rate, calls the etching technics formula to execute etching technics.Specifically, warm described first
In machine technique, the silicon on etching control wafer surface reduces the reality to change the indoor environmental parameter of etch chamber and wafer contacts bias
When etch rate, wherein the indoor environmental parameter of etch chamber includes but is not limited to cavity air pressure and side wall deposit ingredient；
In the second warming-up technique, the silicon nitride on etching control wafer surface makes the polymer deposits generated in the inner wall of etching cavity
Surface increases the real time etch rate to change the plasma density in etching cavity.In the present embodiment, because of institute
Stating sidewall structure 460 needs a certain amount of over etching that the height of the sidewall structure 460 is made to be slightly less than the floating gate silicon nitride
The height of structure 450 calls the first warming-up work so the demand etch rate is easy to be greater than the real time etch rate at this time
Skill formula etches the silicon on control wafer surface to execute the first warming-up technique to change the indoor environmental parameter of etch chamber (such as cavity
Air pressure and side wall deposit ingredient etc. environmental parameter) and wafer contacts bias reduce the real time etch rate.Such as Fig. 3 institute
Show, in 460 etching technics of sidewall structure of the flush memory device of shared word line, etching is located at control gate polysilicon layer 440 and word
Silica between line 500 is to form the sidewall structure 460 of the flush memory device of shared word line.
By comparing the demand etch rate and the real time etch rate size, and execution the first warming-up technique with
Reduce the real time etch rate, the pro-active intervention and dynamic for realizing the real time etch rate of etching machine bench adjust, so that carving
The real time etch rate of erosion board meets the etch rate demand of etching technics, avoids what tunnel oxide 480 was accidentally etched
Situation improves the accuracy of the etch rate of etching machine bench, improves product yield.
To sum up, the present invention provides a kind of lithographic method, comprising: first step: initialization；Second step: according to etching work
Skill loads corresponding technique formula, and confirms the demand etch rate of the etching technics, wherein the technique formula packet
It includes: etching technics formula, the first warming-up technique formula and the second warming-up technique formula；Third step: the reality of etching machine bench is obtained
When etch rate；Four steps: the size of the demand etch rate and the real time etch rate；5th step: if
The demand etch rate is greater than the real time etch rate, calls the first warming-up technique formula and returns to execution third step；
If the demand etch rate is less than the real time etch rate, calls the second warming-up technique formula and return to execution third step
Suddenly；If the demand etch rate is equal to the real time etch rate, the etching technics formula is called.By comparing the need
The size of etch rate Yu the real time etch rate, and the process that corresponding execution is different are asked, the real-time of etching machine bench is realized
The pro-active intervention and dynamic of etch rate adjust, so that the real time etch rate of etching machine bench meets the etch rate of etching technics
Demand avoids etching machine bench and accidentally etches or etch insufficient situation, improves the accurate of the etch rate of etching machine bench
Property, improve product yield.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of lithographic method characterized by comprising
First step: the etching parameters of etching machine bench are initialized；
Second step: loading corresponding technique formula according to etching technics, and confirms the demand etching speed of the etching technics
Rate, wherein the technique formula includes: etching technics formula, the first warming-up technique formula and the second warming-up technique formula；
Third step: the real time etch rate of etching machine bench is obtained；
Four steps: the size of the demand etch rate and the real time etch rate；
5th step: if the demand etch rate is greater than the real time etch rate, call the first warming-up technique formula to hold
Row the first warming-up technique, and return to execution third step；If the demand etch rate is less than the real time etch rate, call
Second warming-up technique formula returns to execution third step to execute the second warming-up technique；If the demand etch rate is equal to
The real time etch rate calls the etching technics formula to execute etching technics.
2. lithographic method according to claim 1, which is characterized in that in the first warming-up technique, etch control wafer table
The silicon in face is to change the indoor environmental parameter of etch chamber and wafer contacts bias, to reduce the real time etch rate, wherein
The indoor environmental parameter of etch chamber includes: cavity air pressure and side wall deposit ingredient.
3. lithographic method according to claim 1, which is characterized in that in the second warming-up technique, etch control wafer table
The silicon nitride in face makes the polymer deposits generated in the inner wall surface of etching cavity to change the plasma in etching cavity
Density, to increase the real time etch rate.
4. lithographic method according to claim 1, which is characterized in that the etching technics includes the flash memories of shared source line
The sidewall structure etching technics of the flush memory device of the isolation structure etching technics and shared word line of part.
5. lithographic method according to claim 4, which is characterized in that in the isolation junction of the flush memory device of the shared source line
In structure etching technics, the silicon nitride between wordline and bit line is etched to form the isolation junction of the flush memory device of shared source line
Structure.
6. lithographic method according to claim 5, which is characterized in that in the isolation junction of the flush memory device of the shared source line
In structure etching technics, the demand etch rate is
7. lithographic method according to claim 5, which is characterized in that the isolation structure of the flush memory device of the shared source line
Critical size on the width is 0.12um.
8. lithographic method according to claim 4, which is characterized in that in the side wall knot of the flush memory device of the shared word line
In structure etching technics, the silica between control gate and wordline is etched to form the side wall knot of the flush memory device of shared word line
Structure.
9. lithographic method according to claim 8, which is characterized in that in the side wall knot of the flush memory device of the shared word line
In structure etching technics, the demand etch rate is
10. lithographic method according to claim 8, which is characterized in that the side wall knot of the flush memory device of the shared word line
The critical size of structure on the width is 90nm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113658888A (en) * | 2021-08-16 | 2021-11-16 | 长鑫存储技术有限公司 | Hybrid process control method, device, apparatus and medium |
| CN116884884A (en) * | 2023-09-06 | 2023-10-13 | 粤芯半导体技术股份有限公司 | Warming-up sheet for grid side wall ICP etching, preparation method thereof and warming-up method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101055841A (en) * | 2006-04-12 | 2007-10-17 | 中芯国际集成电路制造(上海)有限公司 | Making method of semiconductor memory part |
| CN101894737A (en) * | 2009-05-19 | 2010-11-24 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Control method of cavity environment |
| US20150126036A1 (en) * | 2013-11-05 | 2015-05-07 | Tokyo Electron Limited | Controlling etch rate drift and particles during plasma processing |
| US20160307740A1 (en) * | 2015-04-20 | 2016-10-20 | Samsung Electronics Co., Ltd. | Substrate Processing System and Ceramic Coating Method Therefor |
| CN107275248A (en) * | 2016-04-07 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | Board control method and machine control system |
-
2019
- 2019-09-06 CN CN201910842922.XA patent/CN110534427B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101055841A (en) * | 2006-04-12 | 2007-10-17 | 中芯国际集成电路制造(上海)有限公司 | Making method of semiconductor memory part |
| CN101894737A (en) * | 2009-05-19 | 2010-11-24 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Control method of cavity environment |
| US20150126036A1 (en) * | 2013-11-05 | 2015-05-07 | Tokyo Electron Limited | Controlling etch rate drift and particles during plasma processing |
| US20160307740A1 (en) * | 2015-04-20 | 2016-10-20 | Samsung Electronics Co., Ltd. | Substrate Processing System and Ceramic Coating Method Therefor |
| CN107275248A (en) * | 2016-04-07 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | Board control method and machine control system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113658888A (en) * | 2021-08-16 | 2021-11-16 | 长鑫存储技术有限公司 | Hybrid process control method, device, apparatus and medium |
| CN113658888B (en) * | 2021-08-16 | 2023-07-14 | 长鑫存储技术有限公司 | Hybrid process control method, apparatus, device and medium |
| CN116884884A (en) * | 2023-09-06 | 2023-10-13 | 粤芯半导体技术股份有限公司 | Warming-up sheet for grid side wall ICP etching, preparation method thereof and warming-up method |
| CN116884884B (en) * | 2023-09-06 | 2023-11-24 | 粤芯半导体技术股份有限公司 | Warming-up sheet for grid side wall ICP etching, preparation method thereof and warming-up method |
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