CN110993605B - Method for forming flash memory device - Google Patents
Method for forming flash memory device Download PDFInfo
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- CN110993605B CN110993605B CN201911204016.3A CN201911204016A CN110993605B CN 110993605 B CN110993605 B CN 110993605B CN 201911204016 A CN201911204016 A CN 201911204016A CN 110993605 B CN110993605 B CN 110993605B
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- semiconductor substrate
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- dielectric layer
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000010410 layer Substances 0.000 claims abstract description 115
- 239000004065 semiconductor Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 230000015654 memory Effects 0.000 claims abstract description 36
- 239000011241 protective layer Substances 0.000 claims abstract description 30
- 230000008569 process Effects 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000007921 spray Substances 0.000 claims description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- -1 boron ions Chemical class 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
In the method for forming the flash memory device, the protective layer covering the semiconductor substrate of the flash memory region is formed, so that damage to the dielectric layer of the flash memory region is avoided when the dielectric layer of the logic region is removed later. Further, since the semiconductor substrate is covered with the dielectric layer, damage to the semiconductor substrate can be avoided in the process of subsequently removing the protective layer and the remaining dielectric layer.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method for forming a flash memory device.
Background
With the continuous popularization of flash memory applications, flash memory devices are becoming more and more important, and flash memory has the advantages of large capacity, low power consumption, low cost, high read-write speed and the like, so that the flash memory is one of the most widely applied nonvolatile memories at present. Of the Flash memories, NOR Flash (NOR Flash) and NAND Flash (NAND Flash) are two of the most dominant products. Compared with NAND flash memory, NOR flash memory is more reliable, processes small data volume faster, has the capability of executing in a chip, and has wide application in the fields of occasions with smaller data volume and program memories. Today, NOR flash memory has entered a large scale mass production phase of 65nm, and according to moore's law, the development and mass production of 55&50nm node NOR flash memory is a necessity for the development of memory chip manufacturing. The more advanced technology nodes mean smaller flash cell sizes, i.e., smaller active area widths and gap widths, which can present greater process challenges for the fabrication of flash memory chips.
The gate structure of the flash memory device is positioned on the surface of the semiconductor substrate, a side wall is formed around the gate structure, an integral etching mode is adopted in the side wall process flow, the semiconductor substrate is also etched when the side wall is etched, the protective layer on the semiconductor surface is removed by multiple times of etching, and etching gas or liquid is easily contacted with the semiconductor substrate, so that the semiconductor substrate is damaged by etching.
Disclosure of Invention
The application aims to provide a method for forming a flash memory device, which is used for solving the problem of etching damage to a semiconductor substrate in the prior art.
In order to solve the above technical problems, the present application provides a method for forming a flash memory device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a flash memory area and a logic area, and a grid structure is formed on the semiconductor substrate of the flash memory area;
forming a dielectric layer, wherein the dielectric layer covers the gate structure and the surface of the semiconductor substrate;
forming a protective layer, wherein the protective layer covers the semiconductor substrate of the flash memory region;
removing the dielectric layer of the logic region to expose the semiconductor substrate of the logic region;
performing an ion implantation process on the semiconductor substrate of the logic region;
removing the protective layer and the rest of the dielectric layer;
optionally, in the method for forming a flash memory device, a side wall layer is formed on a side surface of the gate structure, and when the dielectric layer is formed, the dielectric layer covers the top surface of the gate structure and the side wall layer.
Optionally, in the method for forming a flash memory device, the method for forming a sidewall layer includes:
forming a side wall material layer, wherein the side wall material layer covers the top surface and the side surface of the grid structure and the surface of the semiconductor substrate;
and removing the side wall material layers on the top surface of the grid electrode structure and the surface of the semiconductor substrate to form the side wall layer.
Optionally, in the method for forming a flash memory device, the top surface of the gate structure and the sidewall material layer on the surface of the semiconductor substrate are removed by dry etching.
Optionally, in the method for forming a flash memory device, the sidewall material layer is a stacked silicon oxide layer and silicon nitride layer.
Optionally, in the method for forming a flash memory device, the material of the dielectric layer is silicon nitride.
Optionally, in the method for forming a flash memory device, the protective layer is a photoresist layer.
Optionally, in the method for forming a flash memory device, the dielectric layer of the logic region is removed by dry etching.
Optionally, in the method for forming a flash memory device, the remaining dielectric layer is removed by wet etching.
Optionally, in the method for forming a flash memory device, the solution used in the wet etching is phosphoric acid.
In the method for forming the flash memory device, the protective layer covering the semiconductor substrate of the flash memory region is formed, so that damage to the dielectric layer of the flash memory region is avoided when the dielectric layer of the logic region is removed later. Furthermore, the semiconductor substrate is covered with the dielectric layer, and damage to the semiconductor substrate can be avoided in the process of removing the protective layer and the remaining dielectric layer later.
Drawings
Fig. 1 is a flowchart illustrating a method for forming a flash memory device according to an embodiment of the present application;
fig. 2 to 5 are schematic structural diagrams of a flash memory device according to an embodiment of the present application;
wherein reference numerals are as follows:
100-a semiconductor substrate; 101-a dielectric layer; 102-an oxide layer; 110-a flash memory area; a 111-gate structure; 120-logic area; 130-a side wall layer; 140 a protective layer.
Detailed Description
The method for forming the flash memory device according to the present application is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the application. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
The core idea of the application is to provide a method for forming a flash memory device, which is to form a protective layer covering the semiconductor substrate of the flash memory region, so as to avoid damage to the dielectric layer of the flash memory region when the dielectric layer of the logic region is removed later. Furthermore, the semiconductor substrate is covered with the dielectric layer, and damage to the semiconductor substrate can be avoided in the process of removing the protective layer and the remaining dielectric layer later. .
The application will be further described with reference to specific examples.
Fig. 1 is a flowchart illustrating a method for forming a flash memory device according to an embodiment of the application. As shown in fig. 1, the present application provides a method for forming a flash memory device, which includes the following steps:
step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a flash memory area and a logic area, and a grid structure is formed on the semiconductor substrate of the flash memory area;
step S2: forming a dielectric layer, wherein the dielectric layer covers the gate structure and the surface of the semiconductor substrate;
step S3: forming a protective layer, wherein the protective layer covers the semiconductor substrate of the flash memory region;
step S4: removing the dielectric layer of the logic region to expose the semiconductor substrate of the logic region;
step S5: performing an ion implantation process on the semiconductor substrate of the logic region;
step S6: and removing the protective layer and the rest of the dielectric layer.
Next, please refer to fig. 2, which is a schematic diagram illustrating a structure formed in a method for forming a flash memory device according to an embodiment of the present application. As shown in fig. 2, in step S1, a semiconductor substrate 100 is provided, and an oxide layer is formed on the surface of the semiconductor substrate 100, where the oxide layer can protect the semiconductor substrate 100 from damage caused by the semiconductor substrate 100 in a subsequent process. Preferably, the oxide layer 102 may be a silicon oxide layer. A gate structure 111 is formed on the semiconductor substrate 100. The semiconductor substrate 100 includes a flash memory region 110 and a logic region 120, and a gate structure 111 is formed on the semiconductor substrate 100 of the flash memory region 110; the gate structure 111 is located on the oxide layer 101. Specifically, the gate structure 111 includes a gate dielectric layer and a gate electrode located on the gate dielectric layer, where a material of the gate dielectric layer may be silicon oxide; the gate electrode may be made of polysilicon, but is not limited to polysilicon, and may be made of other materials known to those skilled in the art, such as metal, etc.
A sidewall layer 130 is formed on a side surface of the gate structure 111, and the method for forming the sidewall layer 130 includes: forming a side wall material layer, wherein the side wall material layer covers the top surface and the side surface of the gate structure 111 and the surface of the semiconductor substrate 100; and removing the side wall material layer on the top surface of the gate structure 111 and the surface of the semiconductor substrate 100 to form the side wall layer 130. The sidewall material layers on the top surface of the gate structure 111 and the surface of the semiconductor substrate 100 may be removed by a dry etching method. Preferably, the sidewall layer 130 includes a first silicon oxide layer covering the side surface of the gate structure 111, a silicon nitride layer covering the first silicon oxide layer, and a second silicon oxide layer covering the silicon nitride layer. The sidewall layer 130 can prevent source-drain punch-through during high-dose source-drain (S/D) implantation.
Referring to fig. 2, in step S2, a dielectric layer 101 is formed, and the dielectric layer 101 covers the gate structure 111 and the surface of the semiconductor substrate 100; the dielectric layer 101 covers the top surface of the gate structure 111 and the sidewall layer 130. The dielectric layer 101 may be formed by a deposition method. Further, the method for forming the dielectric layer 101 includes depositing a dielectric material on the gate structure 111 and the semiconductor substrate 100 to form the dielectric layer 101. The dielectric layer 101 covers the oxide layer. Preferably, the material of the dielectric layer 101 is silicon nitride.
Fig. 3 is a schematic structural diagram of a flash memory device formed by the method according to the embodiment of the application. In step S3, a protective layer 140 is formed, the protective layer 140 covering the semiconductor substrate 100 of the flash memory region 110. Preferably, the protective layer 140 is a photoresist layer, and the method for forming the protective layer 140 includes placing the semiconductor substrate 100 on a spreading machine, calculating the thickness of the photoresist layer to be formed on the semiconductor substrate 100, and calculating the total photoresist spray amount required for forming the photoresist layer, where the total photoresist spray amount can be decomposed into photoresist spray amounts of more than two times, so that the photoresist has better fluidity in the process of coating the photoresist. Thereby forming a relatively flat photoresist layer. After the photoresist is applied, the semiconductor substrate 100 is baked to form the photoresist layer, i.e., the protective layer 140. The protection layer 140 is formed to protect the dielectric layer 101 of the flash memory region 110 from damage caused by a subsequent etching process to the dielectric layer 101 of the flash memory region 110. Further, since the dielectric layer 101 covers the semiconductor substrate 100, damage to the semiconductor substrate 100 in the subsequent etching process can be avoided.
In step S4, the dielectric layer 101 of the logic region 120 is removed, the semiconductor substrate 100 of the logic region 120 is exposed, and the dielectric layer 101 of the logic region 120 may be removed by dry etching. Preferably, the gas used for the dry etching may be one or more of carbon tetrafluoride, argon, hydrogen bromide and boron trichloride. Since the dielectric layer 101 of the flash memory region 110 is covered with the protective layer 140. Therefore, only the dielectric layer 101 of the logic region 120 can be removed by the dry etching, thereby avoiding damage to the dielectric layer 101 of the flash memory region 110.
In step S5, an ion implantation process is performed on the semiconductor substrate 100 of the logic region 120, where ions implanted in the ion implantation process may be one or more of boron ions, arsenic ions, or phosphorus ions.
Fig. 5 is a schematic structural diagram of a flash memory device formed by the method according to the embodiment of the application. In step S6, the protective layer 140 and the remaining dielectric layer 101 are removed. The protective layer 140 and the remaining dielectric layer 101 may be removed by wet etching. Preferably, the solution used in the wet etching is phosphoric acid. The phosphoric acid is used for removing the protective layer 140 and the remaining dielectric layer 101, so that a higher etching ratio can be formed during etching, and only the protective layer 140 and the remaining dielectric layer 101 can be removed during etching, thereby avoiding damage to the semiconductor substrate 100 due to over-etching.
In the method for etching the flash memory device, the protective layer covering the semiconductor substrate of the flash memory region is formed, so that damage to the dielectric layer of the flash memory region is avoided when the dielectric layer of the logic region is removed later. Further, since the semiconductor substrate is covered with the dielectric layer, damage to the semiconductor substrate can be avoided in the process of subsequently removing the protective layer and the remaining dielectric layer.
The above description is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the present application, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (7)
1. A method of forming a flash memory device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a flash memory area and a logic area, and a grid structure is formed on the semiconductor substrate of the flash memory area;
forming a dielectric layer, wherein the dielectric layer covers the gate structure and the surface of the semiconductor substrate;
placing the semiconductor substrate on a gumming machine table, and calculating the thickness of a photoresist layer to be formed on the semiconductor substrate and the total spraying amount of the photoresist required for forming the photoresist layer;
decomposing the total photoresist spray amount into photoresist spray amounts of more than two times, and coating photoresist on the semiconductor substrate;
baking the semiconductor coated with the photoresist to form a protective layer, wherein the protective layer covers the semiconductor substrate of the flash memory region;
removing the dielectric layer of the logic region to expose the semiconductor substrate of the logic region;
performing an ion implantation process on the semiconductor substrate of the logic region;
and removing the protective layer and the rest dielectric layer by wet etching, wherein the solution adopted by the wet etching is phosphoric acid.
2. The method for forming a flash memory device of claim 1, wherein a sidewall layer is formed on a side surface of the gate structure, and the dielectric layer covers a top surface of the gate structure and the sidewall layer when the dielectric layer is formed.
3. The method for forming a flash memory device as claimed in claim 2, wherein the method for forming the sidewall layer comprises:
forming a side wall material layer, wherein the side wall material layer covers the top surface and the side surface of the grid structure and the surface of the semiconductor substrate;
and removing the side wall material layers on the top surface of the grid electrode structure and the surface of the semiconductor substrate to form the side wall layer.
4. The method of forming a flash memory device of claim 3, wherein the sidewall material layer on the top surface of the gate structure and the surface of the semiconductor substrate is removed by dry etching.
5. The method of claim 3, wherein the sidewall material layer is a stacked silicon oxide layer and silicon nitride layer.
6. The method of forming a flash memory device of claim 1, wherein the dielectric layer is silicon nitride.
7. The method of forming a flash memory device of claim 1, wherein the dielectric layer of the logic region is removed by dry etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911204016.3A CN110993605B (en) | 2019-11-29 | 2019-11-29 | Method for forming flash memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911204016.3A CN110993605B (en) | 2019-11-29 | 2019-11-29 | Method for forming flash memory device |
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| Publication Number | Publication Date |
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| CN110993605A CN110993605A (en) | 2020-04-10 |
| CN110993605B true CN110993605B (en) | 2023-10-24 |
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| CN114284285B (en) * | 2021-06-02 | 2024-04-16 | 青岛昇瑞光电科技有限公司 | NOR type semiconductor memory device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465525A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Forming method for embedded flash memory |
| CN106409833A (en) * | 2016-10-19 | 2017-02-15 | 武汉新芯集成电路制造有限公司 | Isolation method and preparation method of embedded flash memory |
| CN108074933A (en) * | 2016-11-16 | 2018-05-25 | 无锡华润上华科技有限公司 | Memory and preparation method thereof |
| CN108490739A (en) * | 2018-03-29 | 2018-09-04 | 上海华力集成电路制造有限公司 | Photoetching glue coating method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100812237B1 (en) * | 2006-08-25 | 2008-03-10 | 삼성전자주식회사 | Method of fabricating embedded flash memory device |
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- 2019-11-29 CN CN201911204016.3A patent/CN110993605B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465525A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Forming method for embedded flash memory |
| CN106409833A (en) * | 2016-10-19 | 2017-02-15 | 武汉新芯集成电路制造有限公司 | Isolation method and preparation method of embedded flash memory |
| CN108074933A (en) * | 2016-11-16 | 2018-05-25 | 无锡华润上华科技有限公司 | Memory and preparation method thereof |
| CN108490739A (en) * | 2018-03-29 | 2018-09-04 | 上海华力集成电路制造有限公司 | Photoetching glue coating method |
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