CN102194675A - Method for producing grid of semiconductor device - Google Patents
Method for producing grid of semiconductor device Download PDFInfo
- Publication number
- CN102194675A CN102194675A CN2010101246087A CN201010124608A CN102194675A CN 102194675 A CN102194675 A CN 102194675A CN 2010101246087 A CN2010101246087 A CN 2010101246087A CN 201010124608 A CN201010124608 A CN 201010124608A CN 102194675 A CN102194675 A CN 102194675A
- Authority
- CN
- China
- Prior art keywords
- etching
- layer
- gas
- oxygen
- flow velocity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a method for producing a grid of a semiconductor device, comprising the steps of: sequentially forming a grid oxide layer, a grid material layer, a finishing layer, an anti-reflecting coating layer and a photoresist layer with patterns on a front end device layer; etching the anti-reflecting coating layer by using the photoresist layer with the patterns as a mask to expose the upper surface of the finishing layer; primarily etching the finishing layer by using first etching gas containing oxygen to form an opening with a depth as 10-70% of thickness of the finishing layer; slightly adjusting the size of the opening by using second etching gas containing oxygen, and etching the remainder finishing layer to form a finishing layer with patterns, wherein the slight adjustment is performed by controlling the flow speed of the oxygen in the second etching gas; and sequentially etching the grid material layer and the grid oxide layer by using the finishing layer with the patterns as a mask to form a grid. By using the method disclosed by the invention, the mask finishing technique can be performed in a larger technique window; and the same key size uniformity can be obtained.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of method of making grating of semiconductor element.
Background technology
At present, development along with very lagre scale integrated circuit (VLSIC), the circuit design size is more and more littler, particularly technology node has arrived in the technology below the 45nm, critical size (the CD of circuit, CriticalDimension) variation is also increasing for the influence of device performance, and for example the critical size variation of circuit can directly cause the variation of the device speed of service.
Owing to be exposed the influence of the resolution limit of board (optical exposure too1), circuit pattern on the mask is being carried out exposure technology with design transfer to photoresist the time, just be easy to produce optical proximity effect (OPE, Optical Proximity Effect).Optical approach effect comes from when the very close circuit pattern of pitch on the mask is transferred on the photoresist of Semiconductor substrate in little shadow mode, because optical diffraction and interference between adjacent patterns, and cause the pattern distortions distortion of transferring at last on the photoresist, produce the change fixed according to pattern form.In the deep-submicron device, because the circuit pattern very dense, optical approach effect is more serious to the influence of the pattern on the mask.Therefore, cause design transfer distortion on the mask for fear of above-mentioned optical approach effect, and can't correctly be transferred to circuit diagram on the wafer, existing semiconductor technology all is to utilize computer system to come that this circuit pattern is carried out optics earlier to close on correction (OPC, Optical Proximity Correction), with the elimination optical approach effect, and then the corrected circuit pattern of foundation is made mask.Therefore, the basic principle that optics closes on correction is exactly to carry out in advance modification for circuit pattern, the defective that the amount of make revising just in time can the compensate for optical approach effect causes, thereby the design transfer of closing on the mask that revise to form through optics to the wafer after, just can reach the requirement of exposure technology.
Yet because the difference of circuit, corresponding circuit pattern compact district (dense) and non-dense set district (ISO) can occur because spacing (pitch) is different, and the compact district is the higher zone of device density, and the non-dense set district is that device is more sparse, the zone that density is lower.Therefore, close on correction though passed through optics, after carrying out exposure technology, the formed photoresist pattern of same circuits pattern that lays respectively at compact district and non-dense set district is also can be owing to the spacing in compact district and non-dense set district different tangible size difference to occur, for example, may be for the compact district, the size of the photoresist pattern that forms after the exposure technology is greater than the size of the photoresist pattern in non-dense set district.Therefore, after etching, also can utilize critical dimension ESEM (CD-SEM), many live widths on the wafer and device architecture side are analyzed, with critical size (CD) information, etching CD deviation (Etch CD Bias), etching CD deviation range (range) and the 3-sigma value of obtaining device on the wafer.Etching CD deviation can be carried out quality control to the variation difference of zones of different.Etching CD deviation is calculated by following formula:
Etching CD deviation=AEI CD-ADI CD
Wherein, AEI CD is the critical size of checking after the etching, the critical size of the material that is etched after promptly photoresist removes; ADI CD is the critical size of checking after developing, i.e. the critical size of photoresist before the etching.Etching CD deviation range is the poor of the maximum of etching CD deviation and minimum value.The 3-sigma value is on the wafer after the each point etching three of the variance of device CD times, be used for characterizing after the etching key size evenness of device on the wafer (CD uniformity, CDU).Under a lot of situations, close on the difference of the circuit pattern meeting of correction through optics, and make that the etching CD deviation range of the device of formation does not satisfy technological requirement after etching technics is finished, thereby influence the precision of overall optical carving technology because of the pattern distribution situation.
As everyone knows, the etching technics of grid is the committed step in the CMOS manufacture process.Along with CMOS is reduced to below the 45nm technology node, utilize mask finishing (trim) technology in the traditional handicraft usually, come the AEI CD of grid is adjusted, to obtain accurate AEI CD.Usually, the mask dressing technique of traditional handicraft is to control the AEI CD of grid by changing the finishing time, and specifically, when the finishing time was longer, the grid AEI CD of acquisition was less, when the finishing time more in short-term, the grid AEI CD of acquisition is bigger.
Yet, have more following problems by the mask dressing technique of control finishing time.Fig. 1 is the change curve of 3-sigma value under the different finishing times in the prior art.As shown in Figure 1, the 3-sigma value of different finishing time correspondences changes greatly, and therefore the different finishing time makes and has different CDU between the different wafers.
Fig. 2 be in the prior art under the different finishing times etching CD deviation with the change curve of spacing.As shown in Figure 2, along with the increase of spacing, the etching CD deviation of different finishing time correspondences all reduces gradually.Table 1 is maximum, minimum value and the etching CD deviation range by the etching CD deviation under the difference finishing time of Fig. 2 acquisition.
Table 1
Can be clearer from table 1 finds out, the etching CD deviation range difference that the different finishing time is obtained down, the finishing time effects etching CD deviation range in the full spacing range.When the finishing time was 8s, 9s and 10s, etching CD deviation range is correspondence 5.1,5.3 and 5.3 respectively.But when the finishing time increased to 11s and 12s, etching CD deviation range had increased to 6.5 and 7.1 respectively.For the manufacturing process of grid, the etching CD deviation range that the finishing time is respectively 11s and 12s correspondence can not satisfy technological requirement.Therefore, can only repair mask in the 8-10s scope, feasible mask dressing technique by the control time has very small process window, and this has very big constraint for actual production.
There is above-mentioned defective owing to repair the traditional handicraft of mask by the control finishing time, therefore, need a kind of improved process, can solve effectively that the etching CD deviation range in the full spacing range does not satisfy the problem of technological requirement on the different and wafer of the key size evenness that causes owing to control finishing asynchronism(-nization), so that in bigger process window, carry out the mask trim process and the identical key size evenness of acquisition between different chips.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention proposes a kind of method of making grating of semiconductor element, described method comprises: a) form gate oxide layers, gate material layers, trim layer, antireflecting coating successively and have the photoresist layer of pattern on the front end device layer; B) be that mask carries out etching to described antireflecting coating with described photoresist layer, to expose the upper surface of described trim layer with pattern; C) use first etching gas comprise oxygen that described trim layer is carried out preliminary etching, to form the opening of 10%-70% that the degree of depth is the thickness of described trim layer; D) use second etching gas that comprises oxygen that the size of described opening is finely tuned, and the remaining trim layer of etching, have the trim layer of pattern with formation, wherein, carry out described fine setting by the oxygen gas flow rate of controlling in described second etching gas; And e) is mask described gate material layers of etching and described gate oxide layers successively with described trim layer, forms grid with pattern.
According to an aspect of the present invention, the thickness of wherein said trim layer is the 500-1000 dust.
According to an aspect of the present invention, the material of wherein said trim layer is at least a material that is selected from amorphous carbon, silica or the silicon nitride.
According to an aspect of the present invention, wherein between described trim layer and described antireflecting coating, also comprise dark antireflecting coating.
According to an aspect of the present invention, wherein said first etching gas also comprises hydrogen halide and fluorohydrocarbon gas.
According to an aspect of the present invention, the carbon of wherein said fluorohydrocarbon gas/fluorine ratio is smaller or equal to 0.5.
According to an aspect of the present invention, the flow velocity of wherein said hydrogen halide is 20-400sccm, and the flow velocity of described fluorohydrocarbon gas is 5-200sccm.
According to an aspect of the present invention, the flow velocity of oxygen is 6-14sccm in wherein said first etching gas.
According to an aspect of the present invention, wherein said second etching gas also comprises chlorine.
According to an aspect of the present invention, the flow velocity of wherein said chlorine is 10-100sccm.
According to an aspect of the present invention, wherein said second etching gas also comprises inert gas.
According to an aspect of the present invention, the flow velocity of wherein said inert gas is smaller or equal to 500sccm greater than 0sccm.
According to an aspect of the present invention, the flow velocity of oxygen is controlled according to the difference between described opening size and the target size in wherein said second etching gas, and the trim rate of wherein said oxygen is 1nm/sccm.
According to an aspect of the present invention, the flow velocity of oxygen is 6-14sccm in wherein said second etching gas.
According to an aspect of the present invention, the etch period of wherein said c step is 10-20s, and the etch period of described d step is 5-15s.
The method according to this invention can be carried out the mask trim process and obtain identical key size evenness between different chips in bigger process window.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the change curve of 3-sigma value under the different finishing times in the prior art;
Fig. 2 be in the prior art under the different finishing times etching CD deviation with the change curve of spacing;
Fig. 3 A to Fig. 3 E is the cutaway view according to each step in the technological process of one embodiment of the invention formation grid;
Fig. 4 is the change curve according to 3-sigma value under the different oxygen gas flow rates of the present invention;
Fig. 5 is with the change curve of spacing according to etching CD deviation under the different oxygen gas flow rates of the present invention;
Fig. 6 is the process chart that forms grid according to one embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention makes grid so that solve a key size evenness difference and the less difficult problem of process window between the different chips.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution mode.
In order to make grid on the different chips obtain identical key size evenness and to have the process window of broad, the present invention proposes a kind of grid making method that combines improved mask dressing technique.Manufacture method with polysilicon gate is that example illustrates principle of the present invention below.Fig. 3 A to Fig. 3 E is the cutaway view of each step in the technological process of grid formed according to the present invention.
At first, as shown in Figure 3A, on substrate, define device active region and finish shallow trench isolation from back formation front end device layer 300.Described substrate includes but not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Form the gate oxide layers 301 that thickness is about the 20-50 dust on front end device layer 300, this gate oxide layers 301 can be by the oxidation technology silicon dioxide that temperature forms under 800～1000 degrees centigrade in the oxygen steam ambient.Utilize methods such as chemical vapor deposition (CVD) on gate oxide layers 301, deposition wants etching to form the gate material layers 302 of grid subsequently.The material of gate material layers 302 can be but be not limited to polysilicon.Mix at once after the deposition with the resistance value of effective reduction grid, improve device performance.Form trim layer 303 on gate material layers 302, the thickness of this trim layer 303 is about the 500-1000 dust.The material of trim layer is at least a material that is selected from amorphous carbon, silica or the silicon nitride, preferably comprises amorphous carbon, more preferably is made up of amorphous carbon.Before the coating photoresist, want process deposition of antiglare layer, to reduce in the exposure process light in the reflection on photoresist surface, most of energy of exposure is absorbed by photoresist, adopt which kind of anti-reflecting layer to depend primarily on the optimization selection of the material and the conditions of exposure of photoresist.The present invention at first forms the dark antireflecting coating 304 that thickness is about the 50-500 dust on trim layer 303 surfaces, the material of this dark antireflecting coating 304 can be silicon oxynitride (SiON), silicon nitride (Si
3N
4) or silicon nitride and hopcalite, then again on the surface of dark antireflecting coating 304 deposit thickness be about the antireflecting coating 305 of 500-1000 dust.At last, on antireflecting coating 305, form photoresist layer 306 with pattern.
Then, shown in Fig. 3 B, be mask with photoresist layer 306 with pattern, antagonistic reflex coating 305 and dark antireflecting coating 304 are carried out etching, up to the upper surface that exposes trim layer, to obtain to have the antireflecting coating 305 and 304 of opening.
Then, shown in Fig. 3 C, using first etching gas that comprises oxygen that trim layer 303 is carried out etching, is the opening of the 10%-70% of trim layer 303 thickness to form the degree of depth.The etch period of this step is 10-20s, and purpose is the size that tentatively limits opening.First etching gas also comprises hydrogen halide and fluorohydrocarbon gas.Wherein, the flow velocity of oxygen is about 6-14sccm, and concrete flow velocity for example is 6sccm, 8sccm, 10sccm, 12sccm, 14sccm etc., and wherein, sccm is under the standard state, just 1 atmospheric pressure, 1 cubic centimetre of (1cm of 25 degrees centigrade of following per minutes
3/ min) flow.Hydrogen halide can be selected bromize hydrogen gas or hydrogen chloride gas, and flow velocity is about 20-400sccm, is preferably 50-100sccm.Fluorohydrocarbon gas can be selected CH
2F
2, CHF
3, CF
4Or C
2F
6, so that the polymer that produces does not seldom even produce polymer, promote lateral etching, thereby finish the qualification of trim layer size than smaller or equal to 0.5 gas in carbon/fluorine.The flow velocity of fluorohydrocarbon gas is about 5-200sccm, is preferably 10-50sccm.According to one embodiment of present invention, aerating oxygen, bromize hydrogen gas (HBr) and CH
2F
2Gas, etch period are 15s.Wherein, the flow velocity of oxygen is about 10sccm, and the flow velocity of bromize hydrogen gas is about 50-100sccm, CH
2F
2The flow velocity of gas is about 10-50sccm.
Then, shown in Fig. 3 D, use second etching gas that comprises oxygen that the size of described opening is finely tuned, and the remaining trim layer of etching, the trim layer of pattern had with formation.At first, measure the size of the opening of above-mentioned preliminary etching formation, and compare, to determine the flow velocity of oxygen in second etching gas with target size.Above-mentioned steps can realize by technological means well known in the art, for example, and preceding FEEDBACK CONTROL technology.The flow velocity of oxygen can be selected 6-14sccm in second etching gas, and concrete flow velocity for example is 6sccm, 8sccm, 10sccm, 12sccm, 14sccm etc.The concrete flow velocity of oxygen can be selected according to the trim amount of opening size, and wherein, the trim rate of oxygen is 1nm/sccm, i.e. the every increase of the flow velocity of oxygen (dwindling) 1sccm, and the size of opening then increases (dwindling) about 1nm.Specifically, when opening size during than target size little (greatly) 1nm, oxygen gas flow rate increases (reducing) 1sccm, by that analogy.Then, size to the opening that forms through preliminary etching on trim layer 303 is repaired, and the remainder of trim layer 303 carried out etching, overcoming the inaccurate problem of CD that causes inadequately owing to the mask aligner precision, thereby obtain to satisfy the grid structure of technological requirement by etching subsequently.Second etching gas also comprises chlorine, and wherein, the flow velocity of chlorine is about 10-100sccm, is preferably 20-50sccm.In addition, second etching gas can also comprise inert gas as required, and inert gas can be selected gases such as helium or argon gas, so that keep the pressure in the reaction chamber, and can play the effect of dilution, the flow velocity of inert gas is about greater than 0sccm smaller or equal to 500sccm.The etch period of this step is 5-15s.In an embodiment of the present invention, because opening size and target size that above-mentioned qualification step forms are basic identical, therefore, the flow velocity of oxygen still is 10sccm.In addition, select the flow velocity of chlorine to be about 20-50sccm, select the flow velocity of helium to be about 20-50sccm.Behind the etching 10s, the upper surface of gate material layers exposes.
At last, shown in Fig. 3 E, be mask etching gate material layers 302 and gate oxide layers 301 successively with trim layer 303 with accurate pattern, remove trim layer 303 through technology such as peeling off then, form grid.
Fig. 4 is the change curve according to 3-sigma value under the different oxygen gas flow rates of the present invention.As shown in Figure 4, it is less that the 3-sigma value of different oxygen gas flow rate correspondences changes, and shows after the etching that the CDU of grid is basic identical between the different chips.
Fig. 5 is with the change curve of spacing according to etching CD deviation under the different oxygen gas flow rates of the present invention.As shown in Figure 5, along with the increase of spacing, compare with the situation (Fig. 2) of control finishing time, the trend that the etching CD deviation of different oxygen gas flow rate correspondences reduces slows down.Therefore, etching CD deviation range diminishes.Table 2 is maximum, minimum value and the etching CD deviation ranges by the etching CD deviation under the different oxygen gas flow rates of Fig. 5 acquisition.
Table 2
From table 2, can clearerly find out that when the oxygen gas flow rate of feeding was 6-14sccm, the etching CD deviation range that is obtained substantially all remained in the 5.1-5.8nm scope, satisfies technological requirement.Therefore, compare with the mask dressing technique in control time and have bigger process window by the mask dressing technique of control oxygen gas flow rate.
Fig. 6 is the process chart that forms grid according to one embodiment of present invention.
Execution in step 601 forms gate oxide layers 301, deposition of gate material layer on gate oxide layers on the front end device layer.Mix at once after the deposition with the resistance value of effective reduction grid, improve device performance.Form trim layer on gate material layers, the material of trim layer is at least a material that is selected from amorphous carbon, silica or the silicon nitride, preferably comprises amorphous carbon, more preferably is made up of amorphous carbon.On trim layer, form antireflecting coating and photoresist layer successively with pattern.Wherein antireflecting coating can be embodied as one deck structure that only comprises bottom antireflective coating according to the optimization selection of the material and the conditions of exposure of photoresist, perhaps for comprising that lower floor is that dark antireflecting coating, upper strata are the bottom antireflective coating double-layer structure, or the like.
Execution in step 602 is that mask adopts dry etching or wet etching antagonistic reflex coating to carry out etching with the photoresist layer with pattern, up to the upper surface that exposes trim layer, to form opening on antireflecting coating.
Execution in step 603 uses first etching gas that comprises oxygen that trim layer is carried out etching, is the opening of the 10%-70% of trim layer thickness to form the degree of depth.The purpose of this step is the size that tentatively limits opening.First etching gas also comprises hydrogen halide and fluorohydrocarbon gas, and etch period is 10-20s.Wherein, the flow velocity of oxygen is about 6-14sccm, and concrete flow velocity for example is 6sccm, 8sccm, 10sccm, 12sccm, 14sccm etc.Hydrogen halide can be selected bromize hydrogen gas or hydrogen chloride gas, and flow velocity is about 20-400sccm, is preferably 50-100sccm.Fluorohydrocarbon gas can be selected CH
2F
2, CHF
3, CF
4Or C
2F
6, so that the polymer that produces does not seldom even produce polymer, promote lateral etching, thereby finish the qualification of trim layer size than smaller or equal to 0.5 gas in carbon/fluorine.The flow velocity of fluorohydrocarbon gas is about 5-200sccm, is preferably 10-50sccm.
Execution in step 604 uses second etching gas that comprises oxygen that the size of described opening is finely tuned, and the remaining trim layer of etching, has the trim layer of pattern with formation.At first, measure the size of the opening that forms according to the preliminary etching of step 603, and compare, to determine the flow velocity of oxygen in second etching gas with target size.Above-mentioned steps can realize by technological means well known in the art, for example, and preceding FEEDBACK CONTROL technology.The flow velocity of oxygen is about 6-14sccm in second etching gas, and concrete flow velocity for example is 6sccm, 8sccm, 10sccm, 12sccm, 14sccm etc.The concrete flow velocity of oxygen can be selected according to the trim amount of opening size, and wherein, the trim rate of oxygen is 1nm/sccm, i.e. the every increase of the flow velocity of oxygen or dwindle 1sccm, and the size of opening then increases or dwindles about 1nm.Then, size to the opening that forms through preliminary etching on trim layer is repaired, and the remainder of trim layer carried out etching, overcoming the inaccurate problem of CD that causes inadequately owing to the mask aligner precision, thereby obtain to satisfy the grid structure of technological requirement by etching subsequently.Second etching gas also comprises chlorine, and wherein, the flow velocity of chlorine is about 10-100sccm, is preferably 20-50sccm.In addition, second etching gas can also comprise inert gas as required, and inert gas can be selected gases such as helium or argon gas, so that keep the pressure in the reaction chamber, and can play the effect of dilution, the flow velocity of inert gas is about greater than 0sccm smaller or equal to 500sccm.The etch period of this step is 5-15s.
Last execution in step 605 is mask etching gate material layers and a gate oxide layers successively with the trim layer with accurate CD pattern.Carry out technologies such as peeling off of trim layer then, form grid.
Said method of the present invention can be applied to formation to the various structures that the CDU of etching CD deviation range and different chips has relatively high expectations, and comprises through hole, contact hole or groove etc.
Have according to the semiconductor device of the grid of embodiment manufacturing as mentioned above and can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcie arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (17)
1. method of making grating of semiconductor element, described method comprises:
A) on the front end device layer, form gate oxide layers, gate material layers, trim layer, antireflecting coating and have the photoresist layer of pattern successively;
B) be that mask carries out etching to described antireflecting coating with described photoresist layer, to expose the upper surface of described trim layer with pattern;
C) use first etching gas comprise oxygen that described trim layer is carried out preliminary etching, to form the opening of 10%-70% that the degree of depth is the thickness of described trim layer;
D) use second etching gas that comprises oxygen that the size of described opening is finely tuned, and the remaining trim layer of etching, have the trim layer of pattern with formation, wherein, carry out described fine setting by the oxygen gas flow rate of controlling in described second etching gas; And
E) be mask described gate material layers of etching and described gate oxide layers successively with described trim layer, form grid with pattern.
2. method according to claim 1, the thickness of wherein said trim layer are the 500-1000 dust.
3. method according to claim 1, the material of wherein said trim layer are at least a material that is selected from amorphous carbon, silica or the silicon nitride.
4. method according to claim 1 wherein also comprises dark antireflecting coating between described trim layer and described antireflecting coating.
5. method according to claim 1, wherein said first etching gas also comprises hydrogen halide and fluorohydrocarbon gas.
6. method according to claim 5, the carbon of wherein said fluorohydrocarbon gas/fluorine ratio is smaller or equal to 0.5.
7. method according to claim 5, the flow velocity of wherein said hydrogen halide are 20-400sccm, and the flow velocity of described fluorohydrocarbon gas is 5-200sccm.
8. method according to claim 1, the flow velocity of oxygen is 6-14sccm in wherein said first etching gas.
9. method according to claim 1, wherein said second etching gas also comprises chlorine.
10. method according to claim 9, the flow velocity of wherein said chlorine are 10-100sccm.
11. method according to claim 9, wherein said second etching gas also comprises inert gas.
12. method according to claim 11, the flow velocity of wherein said inert gas are smaller or equal to 500sccm greater than 0sccm.
13. method according to claim 1, the flow velocity of oxygen is controlled according to the difference between described opening size and the target size in wherein said second etching gas, and the trim rate of wherein said oxygen is 1nm/sccm.
14. method according to claim 13, the flow velocity of oxygen is 6-14sccm in wherein said second etching gas.
15. method according to claim 1, the etch period of wherein said c step are 10-20s, the etch period of described d step is 5-15s.
16. an integrated circuit that comprises the grating of semiconductor element of making by the method for claim 1, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
17. an electronic equipment that comprises the grating of semiconductor element of making by the method for claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010124608 CN102194675B (en) | 2010-03-11 | 2010-03-11 | Method for producing grid of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010124608 CN102194675B (en) | 2010-03-11 | 2010-03-11 | Method for producing grid of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102194675A true CN102194675A (en) | 2011-09-21 |
| CN102194675B CN102194675B (en) | 2013-06-12 |
Family
ID=44602527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010124608 Active CN102194675B (en) | 2010-03-11 | 2010-03-11 | Method for producing grid of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102194675B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108490733A (en) * | 2018-03-21 | 2018-09-04 | 上海华力集成电路制造有限公司 | OPC modification methods |
| CN108885977A (en) * | 2016-03-04 | 2018-11-23 | 东京毅力科创株式会社 | Patterned dressing method is carried out during each stage of Integrated Solution |
| CN111902910A (en) * | 2018-05-09 | 2020-11-06 | 应用材料公司 | Method for patterning a layer of material having a desired dimension |
| CN113140505A (en) * | 2021-03-18 | 2021-07-20 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
| CN114114825A (en) * | 2022-01-27 | 2022-03-01 | 广东省大湾区集成电路与系统应用研究院 | Mask optimization method and transistor grid manufacturing process method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030017711A1 (en) * | 2001-07-12 | 2003-01-23 | International Business Machines Corporation | Lateral-only photoresist trimming for sub-80 nm gate stack |
| US20040018739A1 (en) * | 2002-07-26 | 2004-01-29 | Applied Materials, Inc. | Methods for etching using building blocks |
| US20040043590A1 (en) * | 2002-07-31 | 2004-03-04 | Advanced Micro Devices, Inc. | Method for semiconductor gate line dimension reduction |
| CN1938841A (en) * | 2004-03-31 | 2007-03-28 | 东京毅力科创株式会社 | Method of controlling trimming of a gate electrode structure |
-
2010
- 2010-03-11 CN CN 201010124608 patent/CN102194675B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030017711A1 (en) * | 2001-07-12 | 2003-01-23 | International Business Machines Corporation | Lateral-only photoresist trimming for sub-80 nm gate stack |
| US20040018739A1 (en) * | 2002-07-26 | 2004-01-29 | Applied Materials, Inc. | Methods for etching using building blocks |
| US20040043590A1 (en) * | 2002-07-31 | 2004-03-04 | Advanced Micro Devices, Inc. | Method for semiconductor gate line dimension reduction |
| CN1938841A (en) * | 2004-03-31 | 2007-03-28 | 东京毅力科创株式会社 | Method of controlling trimming of a gate electrode structure |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108885977A (en) * | 2016-03-04 | 2018-11-23 | 东京毅力科创株式会社 | Patterned dressing method is carried out during each stage of Integrated Solution |
| CN108885977B (en) * | 2016-03-04 | 2023-08-08 | 东京毅力科创株式会社 | Trimming method for patterning during various stages of an integration scheme |
| CN108490733A (en) * | 2018-03-21 | 2018-09-04 | 上海华力集成电路制造有限公司 | OPC modification methods |
| CN111902910A (en) * | 2018-05-09 | 2020-11-06 | 应用材料公司 | Method for patterning a layer of material having a desired dimension |
| CN113140505A (en) * | 2021-03-18 | 2021-07-20 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
| CN113140505B (en) * | 2021-03-18 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
| CN114114825A (en) * | 2022-01-27 | 2022-03-01 | 广东省大湾区集成电路与系统应用研究院 | Mask optimization method and transistor grid manufacturing process method |
| CN114114825B (en) * | 2022-01-27 | 2022-04-15 | 广东省大湾区集成电路与系统应用研究院 | Mask optimization method and transistor grid manufacturing process method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102194675B (en) | 2013-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7563721B2 (en) | Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region | |
| US7141460B2 (en) | Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers | |
| CN102194675B (en) | Method for producing grid of semiconductor device | |
| JP2007294905A (en) | Method of manufacturing semiconductor and etching system | |
| KR20040014112A (en) | Method of manufacturing a semiconductor integrated circuit device | |
| CN102184852A (en) | Method for etching double-doped polysilicon | |
| TW200828407A (en) | Method for fabricating a semiconductor device | |
| CN102194676B (en) | Method for manufacturing semiconductor device grid | |
| TW200525324A (en) | Critical dimension control in a semiconductor fabrication process | |
| CN102194738A (en) | Method for making contact hole | |
| CN100517577C (en) | Manufacturing method for grid of semiconductor device | |
| CN108010835B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN102263017B (en) | Method for manufacturing grid electrode of semiconductor device | |
| Panneerchelvam et al. | Evolution of lithography-to-etch bias in multi-patterning processes | |
| CN101777485B (en) | Etching method | |
| CN109712872B (en) | Method for enhancing ion implantation photoetching process window of semiconductor device | |
| CN101431045B (en) | Method for controlling relative aperture deviation ratio of openings with different aperture | |
| CN109065465B (en) | Method for measuring height stability of shallow trench isolation step | |
| KR100571629B1 (en) | Method for manufacturing in semiconductor device | |
| KR20080002061A (en) | Method of manufacturing flash memory device | |
| US20230411168A1 (en) | Fin structures | |
| CN100517575C (en) | Manufacturing method of semiconductor device grids | |
| US7268086B2 (en) | Method for reducing critical dimension and semiconductor etching method | |
| CN101192524A (en) | Semiconductor device grids preparation method | |
| KR100840660B1 (en) | Method for Manufacturing Semiconductor Devices by Using KrF Light Source |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORAT Effective date: 20130104 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130104 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |