CN102263017B - Method for manufacturing grid electrode of semiconductor device - Google Patents
Method for manufacturing grid electrode of semiconductor device Download PDFInfo
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- CN102263017B CN102263017B CN 201010182714 CN201010182714A CN102263017B CN 102263017 B CN102263017 B CN 102263017B CN 201010182714 CN201010182714 CN 201010182714 CN 201010182714 A CN201010182714 A CN 201010182714A CN 102263017 B CN102263017 B CN 102263017B
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Abstract
The invention discloses a method for manufacturing a grid electrode of a semiconductor device. The method comprises the following steps: a) forming a first grid oxide layer, a grid electrode material layer, a second grid oxide layer, a first hard mask layer, a second hard mask layer, an anti-reflection coating layer and a photo-etching glue layer having a pattern on a front-end device layer in turn; b) etching the anti-reflection coating layer; c) etching the second hard mask layer; d) etching the first hard mask layer; and e) etching the second grid oxide layer, the grid electrode material layer and the first grid oxide layer in turn by taking the first hard mask layer as a mask, and then removing the first hard mask layer, thereby forming the grid electrode, wherein the method also comprises a step of introducing an etching gas for finishing a to-be-finished layer. The method provided by the invention can be used for promoting the property, reliability and yield of a device.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of method of making grating of semiconductor element.
Background technology
Along with very lagre scale integrated circuit (VLSIC) high integration and high performance demand are increased gradually, semiconductor technology is towards 45nm even the more technology node development of small-feature-size.Correspondingly, also more and more higher to the requirement that the precision of semiconductor device manufacturing is controlled, satisfy requirement and the raising yields of design to guarantee product.
The formation of grid is a step crucial in the semiconductor manufacture flow path in the transistor, reason is that grid is the structure of physical size minimum in the whole integrated circuit fabrication process, so grid critical size (Critical Dimension, CD) often need to carry out accurate control, a large amount of technological improvements is devoted to improve the accuracy of grid critical size.
At present, usually adopt the mode that increases the hard mask of one deck to form grid, so that photoetching agent pattern is transferred to grid exactly.Figure 1A and Figure 1B are the cutaway view that prior art is made the device that each step obtains in the technological process of grid structure.
At first, shown in Figure 1A, define device active region and finish shallow trench isolation from rear formation front end device layer 100 at substrate.Form gate oxide layers 101 at front end device layer 100.Utilize the methods such as chemical vapour deposition (CVD) (CVD) at gate oxide layers 101, deposition wants etching to form the gate material layers 102 of grid subsequently.Form second grid oxide skin(coating) 103 in gate material layers 102.Form hard mask layer 104 at second grid oxide skin(coating) 103, the material of this layer can be amorphous carbon etc.Then, form antireflecting coating 105 at hard mask layer 104.At last, form the figuratum photoresist layer 106 of tool in antireflecting coating 105.
Then, as shown in Figure 1B, take photoresist layer 106 as mask, antagonistic reflex coating 105 and hard mask layer 104 carry out etching, with design transfer to hard mask layer 104.Then successively second grid oxide skin(coating) 103, gate material layers 102 and first grid oxide skin(coating) 101 are carried out etching take the figuratum hard mask layer 104 of tool as mask, then remove the residue photoresist through techniques such as ashing, and form grid.
Yet along with constantly reducing of grid size, owing to the reasons such as restriction of the photo-etching machine exposal limit, the grid CD that obtains can not reach the size of technological requirement.And along with the minimum feature size of integrated circuit continues to dwindle, the density of transistor and metal wire is increasing, and another problem having occurred is that line end shortens (LES).Fig. 2 is the top view of grating of semiconductor element.As shown in Figure 2,201 is grid, and 202 is active area.LES embodies is the etching deviation of in the vertical direction grid critical size in the grid forming process and the ratio between the etching deviation of grid critical size in the horizontal direction, wherein, etching deviation be after the etching critical size with develop after critical size poor.
In semiconductor technology, LES is the smaller the better.If LES is excessive, show that the etching deviation of grid critical size on the vertical direction is larger, namely the grid in the vertical direction shortens serious after the etching.Grid can not be overlapped with active area, cause the reduction of device performance and reliability, yields to descend, and the leakage in the device, the problems such as restriction of critical size occur.Thereby, still be necessary the formation method of grid is improved.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention proposes a kind of method of making grating of semiconductor element, comprise step: a) on the front end device layer, form successively first grid oxide skin(coating), gate material layers, second gate oxide skin(coating), the first hard mask layer, the second hard mask layer, antireflecting coating and the figuratum photoresist layer of tool; B) described antireflecting coating is carried out etching; C) described the second hard mask layer is carried out etching; D) described the first hard mask layer is carried out etching; And e) described second gate oxide skin(coating), described gate material layers and described first grid oxide skin(coating) take described the first hard mask layer as mask successively etching, remove described the first hard mask layer, form grid, wherein, further comprising the steps of: as between step a and step b, to pass into the first etching gas the figuratum photoresist layer of described tool is repaired; Perhaps between step c and steps d, pass into the second etching gas described the second hard mask layer, described antireflecting coating and the figuratum photoresist layer of described tool are repaired.This scheme can make grid have less critical size, and can accurately control the critical size of grid.
According to a further aspect in the invention, described finishing comprises: in the situation that other parameter is constant, only the finishing time changes, and measures respectively different corresponding etching deviations of finishing time; Measured data point is carried out match, obtain the relation curve of described etching deviation and described finishing time; With based on described relation curve, determine the actual required finishing time according to needed etching deviation.This scheme can be controlled the critical size of grid more accurately.
According to a further aspect in the invention, the material of described the second hard mask layer is silicon oxynitride, silicon nitride or silicon nitride and hopcalite.This scheme can further improve the electric property of formed grid.
According to a further aspect in the invention, the thickness of described the second hard mask layer is the 100-600 dust.
According to a further aspect in the invention, the etching in the described b step is dry etching, and etching gas comprises CF
4, CHF
3, CH
2F
2, C
3F
8, C
4F
8In one or more.
According to a further aspect in the invention, the etching in the described b step is dry etching, and etching gas comprises halogen gas and/or halogen-containing etching chemical compound gas.
According to a further aspect in the invention, described etching gas also comprises inert gas.
According to a further aspect in the invention, the etching in the described c step comprises main etching and over etching.This scheme can be removed etch residue, makes open region have higher selection ratio.
According to a further aspect in the invention, described main etching and described over etching are dry etching, and etching gas comprises CF
4, CHF
3, CH
2F
2, SF
6And NF
3In one or more.
According to a further aspect in the invention, described etching gas also comprises inert gas.
According to a further aspect in the invention, described the first etching gas comprises chlorine and oxygen.
According to a further aspect in the invention, the flow velocity of described chlorine is 10-200sccm, and the flow velocity of described oxygen is 10-200sccm.
According to a further aspect in the invention, the flow velocity of described chlorine is 20-100sccm, and the flow velocity of described oxygen is 20-100sccm.
According to a further aspect in the invention, described the first etching gas also comprises inert gas.
According to a further aspect in the invention, described the second etching gas comprises CF
4, CHF
3And CH
2F
2In one or more.This scheme can reduce etch rate, thereby controls more accurately the CD of grid.
According to a further aspect in the invention, described the second etching gas comprises CF
4This scheme can be improved LES well.
According to a further aspect in the invention, described CF
4Flow velocity be 10-500sccm.
According to a further aspect in the invention, described the second etching gas also comprises oxygen and/or inert gas.
The above-mentioned manufacture method of semiconductor device according to the invention grid can significantly be improved LES, thereby improves device performance, reliability and yields, and improves the leakage in the device, the problems such as restriction of critical size.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A and Figure 1B are the cutaway view that prior art is made the device that each step obtains in the technological process of grid structure;
Fig. 2 is the top view of grating of semiconductor element;
The cutaway view of the device that Fig. 3 A to Fig. 3 G obtains for each step in the technological process of making grid structure according to one embodiment of the present invention;
Fig. 4 is according to the etching deviation of a preferred embodiment of the invention and the relation curve of finishing time;
Fig. 5 is the process chart according to the described making grid of a preferred embodiment of the present invention;
Fig. 6 A to Fig. 6 G for according to the present invention another preferred implementation make the cutaway view of the device that each step obtains in the technological process of grid structure;
Fig. 7 is the etching deviation of another preferred implementation according to the present invention and the relation curve of finishing time;
Fig. 8 is the process chart of the described making grid of another preferred implementation according to the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explanation the present invention makes grid in order to solve grid size and the larger difficult problem of LES in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution mode.
The below take the manufacture method of polysilicon gate as example illustrates principle of the present invention.With reference to Fig. 3 A to Fig. 3 G, the cutaway view of the device that obtains according to each step in the technological process of a preferred embodiment of the invention making grid structure is shown.
At first, as shown in Figure 3A, define device active region and finish shallow trench isolation from rear formation front end device layer 300 at substrate.Described substrate can be the silicon materials that comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Form the first grid oxide skin(coating) 301 that thickness are about the 20-50 dust at front end device layer 300, first grid oxide skin(coating) 301 can be the silicon dioxide layer that approximately forms under 800～1000 degrees centigrade the temperature in the oxygen steam ambient by oxidation technology.Utilize the methods such as chemical vapour deposition (CVD) (CVD) at first grid oxide skin(coating) 301, deposition wants etching to form the gate material layers 302 of grid subsequently.The material of gate material layers 302 can be but be not limited to polysilicon.Can mix at once with the resistance value of effective reduction polysilicon gate after the deposition, improve device performance.Form second gate oxide skin(coating) 303 in gate material layers 302.Second gate oxide skin(coating) 303 is the oxides by furnace oxidation, and the purpose of carrying out this oxidation technology is to repair the lattice of polysilicon gate.At the surface of second gate oxide skin(coating) 303 deposition the first hard mask layer 304.The material of this layer can be amorphous carbon etc.The material that is about the second hard mask layer 305, the second hard mask layers 305 of 100-600 dust at the first hard mask layer 304 surfaces formation thickness can be silicon oxynitride (SiON), silicon nitride (Si
3N
4) or silicon nitride and hopcalite.Form the antireflecting coating 306 that thickness is about the 500-1000 dust at the second hard mask layer 305, to reduce in the exposure process light in the reflection on photoresist surface, most of energy of exposure is absorbed by photoresist, adopt which kind of anti-reflecting layer to depend primarily on the optimization selection of material and the conditions of exposure of photoresist.At last, apply photoresist in antireflecting coating 306, form the photoresist layer 307 with pattern (open region 308) through techniques such as exposure, developments.
Shown in Fig. 3 B, pass into the first etching gas that comprises chlorine, oxygen etc. the figuratum photoresist layer of tool (layer to be trimmed) is repaired, with the width in enlarged openings district 308, thereby make grid obtain the critical size that meets the demands.The flow velocity of chlorine is 10-200sccm, is preferably 20-100sccm; The flow velocity of oxygen is 10-200sccm, is preferably 20-100sccm, and wherein, sccm is under the standard state, namely 1 atmospheric pressure, 1 cubic centimetre of (1cm of 25 degrees centigrade of lower per minutes
3/ min) flow.In addition, can also comprise inert gas in the first etching gas, to play the effects such as protection and dilution.And, in the trim process process, do not apply any bias voltage.
In one embodiment of the present invention, pre-shaping step comprises: in the situation that other parameter is constant, only the finishing time changes, measure respectively different corresponding etching deviations of finishing time, wherein etching deviation is the poor of critical size (AEI) after the rear critical size (ADI) of development and the etching; Measured data point is carried out match, obtain the relation curve of etching deviation and finishing time; Measure the rear critical size that develops to calculate etching deviation, according to described relation curve, the etching deviation that passes through to calculate is determined the actual finishing time.This step can realize by technological means well known in the art, for example, and front FEEDBACK CONTROL technique.
Fig. 4 is according to the etching deviation of a preferred embodiment of the invention and the relation curve of finishing time.Etching deviation (B) with the pass of finishing time (T) is: B=1.1173T-0.5.Wherein, trim rate (B/T) is 1.1173nm/s, namely repairs every increase of time/dwindle 1s, and the size of photoresist open region then increases/dwindle approximately 1.1173nm.Then, based on this relation curve, determine the actual finishing time according to the size of needed etching deviation, adjust the size of photoresist layer open region, overcoming the restriction of the photo-etching machine exposal limit, thereby obtain to satisfy the grid structure of technological requirement by etching subsequently.
Shown in Fig. 3 C, carry out etching take photoresist layer 307 as mask antagonistic reflex coating 306.Lithographic method for example is dry etching, and etching gas preferably comprises CF
4, CHF
3, CH
2F
2, C
3F
8, C
4F
8Deng in the fluorohydrocarbon gas one or more, or halogen gas and/or halogen-containing etching chemical compound gas.Halogen gas is such as being chlorine etc., halogen-containing etching with chemical compound gas such as being hydrogen chloride, hydrogen bromide and boron chloride etc.Etching gas can also comprise inert gases such as argon gas and helium.Preferred etching gas comprises CF
4, CF
4Flow velocity be 10-500sccm.
Shown in Fig. 3 D, the second hard mask layer 305 is carried out main etching, the main etching speed stops after etching into the second hard mask layer 305 interior certain depths, to obtain the second hard mask layer 305 with open region 308.
Shown in Fig. 3 E, the second hard mask layer 305 is carried out over etching, remove open region 308 interior remaining the second hard mask layers 305, to the upper surface that exposes the first hard mask layer 304.The main etching of the second hard mask layer 305 and over etching can be selected dry etching.Etching gas preferably comprises CF
4, CHF
3, CH
2F
2, SF
6And NF
3Deng in the gas one or more, can also comprise inert gases such as argon gas and helium.Preferred etching gas comprises CF
4, CF
4Flow velocity be 10-500sccm.
Shown in Fig. 3 F, take photoresist layer 307 and the second hard mask layer 305 as mask etching the first hard mask layer 304.Lithographic method for example is dry etching, and wherein, the lithographic method of hard mask is well known by persons skilled in the art, and can select different etching technics by corresponding different hard mask material, does not repeat them here.In the process to the second hard mask layer 305 and the first hard mask layer 304 etchings, photoresist layer 307 is consumed substantially.
At last, shown in Fig. 3 G, take the second hard mask layer 305 and the first hard mask layer 304 as mask successively etching second gate oxide skin(coating) 303, gate material layers 302 and first grid oxide skin(coating) 301, then remove the second hard mask layer 305 and the first hard mask layer 304 through the technique such as peeling off, form grid.
The grid that above-mentioned preferred implementation according to the present invention is made has less critical size.Utilize ESEM that the grid of making according to a preferred embodiment of the invention is detected.Testing result shows: LES is 2.4.
The flow chart of Fig. 5 shows the technological process of making grid according to above-mentioned preferred implementation.In step 501, form first grid oxide skin(coating) at the front end device layer, want subsequently etching to form the gate material layers of grid in first grid oxide skin(coating) deposition, form the second gate oxide skin(coating) in gate material layers, at the surface of second gate oxide skin(coating) deposition the first hard mask layer, form the second hard mask layer on the first hard mask layer surface, form antireflecting coating at the second hard mask layer, form the figuratum photoresist layer of tool in antireflecting coating.In step 502, pass into the first etching gas the figuratum photoresist layer of tool is repaired.In step 503, carry out etching take photoresist layer as mask antagonistic reflex coating.In step 504, the second hard mask layer is carried out main etching, etch in the second hard mask layer and stop behind the certain depth.In step 505, the second hard mask layer is carried out over etching, remove remaining the second hard mask layer in the open region, expose the upper surface of the first hard mask layer.In step 506, take photoresist layer and the second hard mask layer as mask etching the first hard mask layer.In step 507, take the second hard mask layer and the first hard mask layer as mask successively etching second gate oxide skin(coating), gate material layers and first grid oxide skin(coating), then remove the second hard mask layer and the first hard mask layer through the technique such as peeling off, form grid.
Above-mentioned technique realizes the adjustment to grid CD by the finishing photoresist layer.Yet, because the loss of photoresist is larger in this technique, can cause when shifting pattern that therefore the spacing between two end points of neighboring gates increases, namely LES is larger.
Describe the manufacture method of the grid of another preferred implementation according to the present invention in detail below with reference to Fig. 6 A to Fig. 6 G.
At first, the front-end architecture of this grid making method as shown in Figure 6A, its structure is described identical with Fig. 3 A, here repeats no more.
Shown in Fig. 6 B, carry out etching take photoresist layer 607 as mask antagonistic reflex coating 606.Lithographic method for example is dry etching, and etching gas preferably comprises CF
4, CHF
3, CH
2F
2, C
3F
8, C
4F
8Deng in the fluorohydrocarbon gas one or more, or halogen gas and/or halogen-containing etching chemical compound gas.Halogen gas is such as being chlorine etc., halogen-containing etching with chemical compound gas such as being hydrogen chloride, hydrogen bromide and boron chloride etc.Etching gas can also comprise inert gases such as argon gas and helium.Preferred etching gas comprises CF
4, CF
4Flow velocity be 10-500sccm.
Shown in Fig. 6 C, the second hard mask layer 605 is carried out main etching, the main etching speed stops after etching into the second hard mask layer 605 interior certain depths, to obtain the second hard mask layer 605 with open region 608.
Shown in Fig. 6 D, the second hard mask layer 605 is carried out over etching, remove the second hard mask layer 605 of open region 608 interior remainders, expose the upper surface of the first hard mask layer 604.
The main etching of the second hard mask layer 605 and over etching can be selected dry etching.Etching gas includes but not limited to comprise CF
4, CHF
3, CH
2F
2, SF
6And NF
3Deng in the gas one or more, can also comprise inert gases such as argon gas and helium.Preferred etching gas is CF
4, CF
4Flow velocity be 10-500sccm.
Shown in Fig. 6 E, passing into the second etching gas repairs the figuratum photoresist layer of the second hard mask layer, antireflecting coating and tool (layer to be trimmed is the figuratum photoresist layer of the second hard mask layer, antireflecting coating and tool) herein, width with enlarged openings district 608, overcome the restriction of the photo-etching machine exposal limit, obtain the grid CD that meets the demands.The second etching gas comprises CF
4, CHF
3, CH
2F
2In one or more.The second etching gas can also comprise oxygen and/or inert gas etc.Preferred the second etching gas comprises CF
4, CF wherein
4Flow velocity be 10-500sccm, be preferably 100-300sccm.And, in the trim process process, do not apply any bias voltage.Please refer to the description of front about concrete technology step of dressing technique etc.
Fig. 7 be according to the preferred embodiment of the present invention etching deviation with the finishing time relation curve.Etching deviation (B) with the pass of finishing time (T) is: B=0.3348T+0.7908.Wherein, trim rate (B/T) is 0.3348nm/s, namely repairs every increase of time/dwindle 1s, and the size of photoresist open region then increases/dwindle approximately 0.3348nm.According to this preferred implementation of the present invention, trim rate only is 0.3348nm/s, therefore more easily controls etching deviation.
Shown in Fig. 6 F, take photoresist layer 607 and the second hard mask layer 605 as mask etching the first hard mask layer 604.Lithographic method for example is dry etching, and wherein, the lithographic method of hard mask is well known to a person skilled in the art, and can select different etching technics by corresponding different hard mask material, does not repeat them here.In the process to the second hard mask layer 605 and the first hard mask layer 604 etchings, photoresist layer 607 is consumed substantially.
At last, shown in Fig. 6 G, take the second hard mask layer 605 and the first hard mask layer 604 as mask successively etching second gate oxide skin(coating) 603, gate material layers 602 and first grid oxide skin(coating) 601, then remove the second hard mask layer 605 and the first hard mask layer 604 through the technique such as peeling off, form grid.
The above-mentioned preferred implementation according to the present invention (Fig. 6 A-6G) can make grid have less critical size, with respect to technological process shown in Figure 5, can control more accurately the critical size of grid.The grid that utilizes ESEM that above-mentioned preferred implementation according to the present invention (Fig. 6 A-6G) is made detects.Testing result shows: LES is 1.1.With respect to execution mode shown in Figure 5, further improved LES, improve performance of devices and reliability, improved the leakage problem in the device.
The flow chart of Fig. 8 shows the technological process according to the described making grid of above-mentioned preferred implementation of the present invention (Fig. 6 A-6G).In step 801, form first grid oxide skin(coating) at the front end device layer, want subsequently etching to form the gate material layers of grid in first grid oxide skin(coating) deposition, form the second gate oxide skin(coating) in gate material layers, at the surface of second gate oxide skin(coating) deposition the first hard mask layer, form the second hard mask layer on the first hard mask layer surface, form antireflecting coating at the second hard mask layer, form the figuratum photoresist layer of tool in antireflecting coating.In step 802, carry out etching take photoresist layer as mask antagonistic reflex coating.In step 803, the second hard mask layer is carried out main etching, etch in the second hard mask layer and stop behind the certain depth.In step 804, the second hard mask layer is carried out over etching, remove the second hard mask layer of remainder in the open region, expose the upper surface of the first hard mask layer.In step 805, pass into the second etching gas the figuratum photoresist layer of the second hard mask layer, antireflecting coating and tool is repaired.In step 806, take photoresist layer and the second hard mask layer as mask etching the first hard mask layer.In step 807, take the second hard mask layer and the first hard mask layer as mask successively etching second gate oxide skin(coating), gate material layers and first grid oxide skin(coating), then remove the second hard mask layer and the first hard mask layer through the technique such as peeling off, form grid.
Have according to the semiconductor device of the grid of embodiment manufacturing as mentioned above and can be applicable in the multiple integrated circuit (IC).For example be memory circuitry according to IC of the present invention, such as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, such as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or any other circuit devcie.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (19)
1. method of making grating of semiconductor element comprises step:
A) on the front end device layer, form successively first grid oxide skin(coating), gate material layers, second gate oxide skin(coating), the first hard mask layer, the second hard mask layer, antireflecting coating and the figuratum photoresist layer of tool;
B) described antireflecting coating is carried out etching;
C) described the second hard mask layer is carried out etching;
D) described the first hard mask layer is carried out etching; With
E) described second gate oxide skin(coating), described gate material layers and described first grid oxide skin(coating) take described the first hard mask layer as mask successively etching are removed described the first hard mask layer, form grid,
Wherein, further comprising the steps of: as between step a and step b, to pass into the first etching gas the figuratum photoresist layer of described tool is repaired; Perhaps between step c and steps d, pass into the second etching gas described the second hard mask layer, described antireflecting coating and the figuratum photoresist layer of described tool are repaired, described finishing comprises:
In the situation that other parameter is constant, only the finishing time changes, and measures respectively different corresponding etching deviations of finishing time;
Measured data point is carried out match, obtain the relation curve of described etching deviation and described finishing time; With
Based on described relation curve, determine the actual required finishing time according to needed etching deviation.
2. the method for claim 1 is characterized in that, the material of described the second hard mask layer is silicon oxynitride, silicon nitride or silicon nitride and hopcalite.
3. the method for claim 1 is characterized in that, the thickness of described the second hard mask layer is the 100-600 dust.
4. the method for claim 1 is characterized in that, the etching in the described b step is dry etching, and etching gas comprises CF
4, CHF
3, CH
2F
2, C
3F
8, C
4F
8In one or more.
5. the method for claim 1 is characterized in that, the etching in the described b step is dry etching, and etching gas comprises halogen gas and/or halogen-containing etching chemical compound gas.
6. such as claim 4 or 5 described methods, it is characterized in that, described etching gas also comprises inert gas.
7. the method for claim 1 is characterized in that, the etching in the described c step comprises main etching and over etching.
8. method as claimed in claim 7 is characterized in that, described main etching and described over etching are dry etching, and etching gas comprises CF
4, CHF
3, CH
2F
2, SF
6And NF
3In one or more.
9. method as claimed in claim 8 is characterized in that, described etching gas also comprises inert gas.
10. the method for claim 1 is characterized in that, described the first etching gas comprises chlorine and oxygen.
11. method as claimed in claim 10 is characterized in that, the flow velocity of described chlorine is 10-200sccm, and the flow velocity of described oxygen is 10-200sccm.
12. method as claimed in claim 10 is characterized in that, the flow velocity of described chlorine is 20-100sccm, and the flow velocity of described oxygen is 20-100sccm.
13. method as claimed in claim 10 is characterized in that, described the first etching gas also comprises inert gas.
14. the method for claim 1 is characterized in that, described the second etching gas comprises CF
4, CHF
3And CH
2F
2In one or more.
15. method as claimed in claim 14 is characterized in that, described the second etching gas comprises CF
4
16. method as claimed in claim 15 is characterized in that, described CF
4Flow velocity be 10-500sccm.
17. such as the described method of claims 14 or 15, it is characterized in that, described the second etching gas also comprises oxygen and/or inert gas.
18. an integrated circuit that comprises by the grating of semiconductor element of making such as each described method among the claim 1-17, wherein said integrated circuit is dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array or radio circuit.
19. an electronic equipment that comprises by the grating of semiconductor element of making such as each described method among the claim 1-17, wherein said electronic equipment is computer, game machine, cellular phone, personal digital assistant, video camera or digital camera.
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| CN103839811B (en) * | 2012-11-21 | 2017-05-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN108550520A (en) * | 2018-04-27 | 2018-09-18 | 武汉新芯集成电路制造有限公司 | A method of improving memory block shallow slot line flatness |
| CN111640665B (en) * | 2019-03-01 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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| CN101151716A (en) * | 2005-04-04 | 2008-03-26 | 先进微装置公司 | Etch process for CD reduction of ARC material |
| CN101211854A (en) * | 2006-12-27 | 2008-07-02 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN101303975A (en) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | Fin filled effect transistor and method of forming the same |
| CN101593685A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Grid formation method |
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