CN112582263B - Punctiform residue improvement method - Google Patents
Punctiform residue improvement method Download PDFInfo
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- CN112582263B CN112582263B CN201910940896.4A CN201910940896A CN112582263B CN 112582263 B CN112582263 B CN 112582263B CN 201910940896 A CN201910940896 A CN 201910940896A CN 112582263 B CN112582263 B CN 112582263B
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- gap
- etching
- wafer
- punctiform
- upper electrode
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 45
- 230000007547 defect Effects 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000002245 particle Substances 0.000 abstract description 2
- 230000001105 regulatory effect Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000012495 reaction gas Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32568—Relative arrangement or disposition of electrodes; moving means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
Abstract
A method for improving punctiform residue is provided. Relates to the technical field of discrete device manufacturing in semiconductor manufacturing technology, in particular to a dot residue improvement method. The wafer etching residual method is convenient to operate and can effectively avoid the influence of an oxide layer or particles. After the wafer is transferred in place, gap is regulated and stabilized to 0.9cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s through CF4 with 200sccm and 250W power, and a Wafer surface natural oxide layer is etched; on the premise of ensuring the BT Step etching rate, the BT Step Gap (the Gap between the silicon chip and the upper electrode in the through etching Step) is adjusted to be consistent with ME STEP GAP (the Gap between the silicon chip and the upper electrode in the main etching Step), so that defects are prevented from being introduced on the Wafer surface in the downward movement process of the upper electrode, and therefore, the Poly (polysilicon) punctiform residues are improved, and the product yield is improved.
Description
Technical Field
The invention relates to the technical field of discrete device manufacturing in semiconductor manufacturing technology, in particular to a punctiform residue improvement method.
Background
Gap is the distance between the upper electrode and the lower electrode of the machine, and Lam4420 is movable Gap for improving etching uniformity and facilitating conveying. The polysilicon etching process includes stabilizing the Gap of the machine and the reaction gas, introducing reaction gas (CF 4, HBr, cl 2) into the cavity, starting RF, ionizing the reaction gas, reacting the plasma with etching medium, controlling the cavity pressure via butterfly valve to change angle, performing physical bombardment and chemical reaction to the silicon chip, and selectively removing the area to be removed
The poly etch generally comprises three main etch steps, BT step, ME step, OE step. This allows the anisotropic etch and selectivity ratio to be optimized in different etch steps
(1) BT, pre-etching, namely removing a natural oxide layer on the surface of Poly by mainly using CF4 gas;
(2) The main etching step, mainly using mixed gas of HBr, cl2 and He to etch most polysilicon on wafer surface, wherein the etching step requires high selectivity, high speed and high uniformity, the combination of HBr and Cl2 has high selectivity and high speed, and the Gap is 0.9cm at the moment by optimizing the Gap of the machine;
(3) And OE is an over-etching step, which mainly uses HBr and Cl2 to remove etching residues caused by previous deposition and PL etching uniformity, ensure high selectivity to the gate oxide layer and obtain ideal anisotropic sidewall profile.
In the prior art, during different processing steps, the Gap needs to be adjusted for multiple times, the initial state is usually 1.2cm, after the BT step is finished, the Gap needs to be stabilized to 0.9cm to run ME and OE, and after the etching is finished, the Gap is restored to 5.5cm to transmit Wafer, so that the operation is completed. When the BT step is switched to the ME (main etching) step, the Gap movement has the risk of introducing defects or leaking impurity gas into the cavity, the introduced defects can form a barrier layer on the surface of the Poly, and the leaked impurity gas can lead the surface of the Poly to produce a natural oxide layer again, so that etching point residues are caused.
Disclosure of Invention
Aiming at the problems, the invention provides a wafer etching residual method which is convenient to operate and can effectively avoid the influence of an oxide layer or particles.
The technical scheme of the invention is as follows: the method comprises the following steps:
1) The wafer is transferred into the reaction cavity in the Gap initial state;
2) Pre-etching: after the wafer is transferred in place, gap adjustment is stabilized to 0.9cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s through CF4 with 200sccm and 250W power, and a Wafer surface natural oxide layer is etched;
3) After the pre-etching is finished, running main etching and over-etching to finish the etching of the polysilicon;
4) After the step 3) is completed, the Gap is restored to the initial state, and Wafer is transferred out to complete the operation.
The Gap initial state is 5.5cm.
After the wafer is transferred in place, gap is regulated and stabilized to 0.9cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s through CF4 with 200sccm and 250W power, and a Wafer surface natural oxide layer is etched; on the premise of ensuring the BT Step etching rate, the BT Step Gap (the Gap between the silicon chip and the upper electrode in the through etching Step) is adjusted to be consistent with ME STEP GAP (the Gap between the silicon chip and the upper electrode in the main etching Step), so that defects are prevented from being introduced on the Wafer surface in the downward movement process of the upper electrode, and therefore, the Poly (polysilicon) punctiform residues are improved, and the product yield is improved.
Drawings
Figure 1 is a schematic view of the structure of the initial state of the invention,
Figure 2 is a schematic diagram of the structure of BT, ME and OE states,
Figure 3 is a schematic view of the state structure after completion of the job,
Figure 4 is a schematic diagram of the structure before the etching,
Figure 5 is a schematic diagram of the structure after the etching,
Figure 6 is a schematic diagram of the structure before etching with the leak-in impurities,
FIG. 7 is a schematic diagram of the structure after etching with the leak-in impurity;
in the figure, 1 is an upper electrode, 2 is a lower electrode, 3 is a natural oxide layer, and 4 is a polysilicon layer.
Detailed Description
The invention is as shown in fig. 1-3, in which a is Gap in initial state, b is Gap in processing state, c is Gap after processing, a dot residue improving method comprises the following steps:
1) The wafer is transferred into the reaction cavity in the Gap initial state; between the upper electrode 1 and the lower electrode 2;
2) Pre-etching: after the wafer is transferred in place, gap adjustment is stabilized to 0.9cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s through CF4 with 200sccm and 250W power, and the Wafer surface natural oxide layer 3 is etched;
3) After the pre-etching is finished, the main etching and the over-etching are operated to finish the etching of the polysilicon layer 4; (the main etching and the over etching are respectively the same as the prior art, belonging to the prior art)
4) After the step 3) is completed, the Gap is restored to the initial state, and Wafer is transferred out to complete the operation.
The Gap initial state is 5.5cm.
After optimization, gap does not move when BT step is switched to ME (main etching) step, so that the risk of introducing defects or leaking impurity gas into a cavity is avoided, the phenomenon of figure 7 is avoided, in the figure, 5 is GOX layer (gate oxide layer), and 6 is impurities, so that the defects of etching are directly caused; the method increases the pressure and the power of the BT step in operation, and ensures that the etching rate of the BT step is not reduced.
For the purposes of this disclosure, the following points are also described:
(1) The drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;
(2) The embodiments disclosed herein and features of the embodiments may be combined with each other to arrive at new embodiments without conflict;
the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (2)
1. A method for improving punctiform residue, comprising the steps of:
1) The wafer is transferred into the reaction cavity in the Gap initial state; is positioned between the upper electrode and the lower electrode;
2) Pre-etching: after the wafer is transferred in place, gap adjustment is stabilized to 0.9cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s through the CF 4 with the power of 200sccm and the natural oxide layer on the Wafer surface is etched;
3) After the pre-etching is finished, running main etching and over-etching to finish the etching of the polysilicon;
4) After the step 3) is completed, the Gap is restored to an initial state, wafer is transmitted out, and the operation is completed;
When the BT step is switched to the ME step, gap does not move any more, so that the defect of etching caused by the risk of introducing defects or leaking impurity gas into the cavity is avoided.
2. The method for improving punctiform residue according to claim 1, wherein the Gap initial state is 5.5cm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910940896.4A CN112582263B (en) | 2019-09-30 | 2019-09-30 | Punctiform residue improvement method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910940896.4A CN112582263B (en) | 2019-09-30 | 2019-09-30 | Punctiform residue improvement method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112582263A CN112582263A (en) | 2021-03-30 |
| CN112582263B true CN112582263B (en) | 2024-04-26 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910940896.4A Active CN112582263B (en) | 2019-09-30 | 2019-09-30 | Punctiform residue improvement method |
Country Status (1)
| Country | Link |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854136A (en) * | 1996-03-25 | 1998-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-step nitride etching process for better critical dimension and better vertical sidewall profile |
| CN1700426A (en) * | 2004-05-21 | 2005-11-23 | 中国科学院微电子研究所 | Method for etching 15-50 nanowire wide polycrystalline silicon gate |
| CN1731286A (en) * | 2004-08-04 | 2006-02-08 | 上海华虹Nec电子有限公司 | Method of through hole etching for RF device products |
| CN1731565A (en) * | 2004-08-04 | 2006-02-08 | 上海华虹Nec电子有限公司 | Etching method for 0.18 micrometre contact hole |
| JP2006345001A (en) * | 2006-09-08 | 2006-12-21 | Tokyo Electron Ltd | Plasma etching method and plasma etching apparatus |
| CN101728254A (en) * | 2008-10-21 | 2010-06-09 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing gate on wafer |
| CN104425237A (en) * | 2013-08-20 | 2015-03-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Substrate etching method |
-
2019
- 2019-09-30 CN CN201910940896.4A patent/CN112582263B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854136A (en) * | 1996-03-25 | 1998-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-step nitride etching process for better critical dimension and better vertical sidewall profile |
| CN1700426A (en) * | 2004-05-21 | 2005-11-23 | 中国科学院微电子研究所 | Method for etching 15-50 nanowire wide polycrystalline silicon gate |
| CN1731286A (en) * | 2004-08-04 | 2006-02-08 | 上海华虹Nec电子有限公司 | Method of through hole etching for RF device products |
| CN1731565A (en) * | 2004-08-04 | 2006-02-08 | 上海华虹Nec电子有限公司 | Etching method for 0.18 micrometre contact hole |
| JP2006345001A (en) * | 2006-09-08 | 2006-12-21 | Tokyo Electron Ltd | Plasma etching method and plasma etching apparatus |
| CN101728254A (en) * | 2008-10-21 | 2010-06-09 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing gate on wafer |
| CN104425237A (en) * | 2013-08-20 | 2015-03-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Substrate etching method |
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| CN112582263A (en) | 2021-03-30 |
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