CN1700426A

CN1700426A - Method for etching 15-50 nanowire wide polycrystalline silicon gate

Info

Publication number: CN1700426A
Application number: CN 200410047533
Authority: CN
Inventors: 徐秋霞; 钱鹤; 赵玉印
Original assignee: Institute of Microelectronics of CAS
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Institute of Microelectronics of CAS
Priority date: 2004-05-21
Filing date: 2004-05-21
Publication date: 2005-11-23
Anticipated expiration: 2024-05-21
Also published as: CN100334693C

Abstract

This invention relates to nanometer wide multi-silicon grating etching method, which comprises the following steps: a, adopting electron beam etching or optical etching combination glue process and hard mask film repairing technique to get the hard mask pattern of Sao2; b, using Sao2 as hard mask and using CF4, Cl2, HBr, O2 gases; Adopting step four reaction ion etching process to get the steep grating etching section.

Description

The lithographic method of 15-50 nano-scale linewidth polysilicon gate

Technical field

The invention belongs to semiconductor device technology and implementation method, particularly a kind of reactive ion etching method of polysilicon gate of live width 15-50 nanometer adopts the method can provide steep etching section and polysilicon to SiO under it ₂Gate medium was much larger than 500: 1 high selectivity etching.

Background technology

The etching technics of polysilicon gate figure has determined the physical gate size and the section shape of device, is one of the strictest factor of decision device electric property.Particularly grid medium thickness is thinned to below 2.0 nanometers in inferior 50 nano-devices, so how to improve the etching selection ratio of polysilicon to the ultra-thin gate dielectric under it, obtaining high anisotropy section is that thirty is divided stern challenge with accurate polysilicon gate size Control.

Summary of the invention

The object of the present invention is to provide a kind of lithographic method of nano-scale linewidth polysilicon gate, this method can etch 15-50 nano-scale linewidth polysilicon gate.The present invention does not need to purchase expensive special equipment, and the old equipment of available 0.5 micron (500 nanometer) technology is finished the etching of the inferior 30 nm polysilicon grid figures of high level, and has the low and practical characteristics of cost.

So the present invention can overcome above-mentioned three big stern challenges, one of the main reasons is that three conventional step etchings have been made into four step etchings, promptly main etching was divided into for two steps, main etching-the 1st is in order to obtain fabulous anisotropy and accuracy, main etching-the 2nd is in order to obtain fabulous etching selection ratio, even make the ultra-thin gate dielectric to 1.3 nanometers under the polysilicon also not cause etching injury.Simultaneously, each step has all been selected etching parameters such as rational gas and component thereof, suitable power, pressure, and they complement each other, and have just reached desirable effect.

Specifically, lithographic method provided by the invention, its key step is as follows:

Step 1 is at the SiO of 1.2-5.0 nanometer thickness ₂Deposit the polysilicon film of 100-300 nanometer thickness on the gate medium, on polysilicon film, form the hard mask pattern of 15-50 nano-scale linewidth then, comprising:

(1) in the tetraethoxysilane thermal decomposition SiO of 720 ℃ of deposition 75 nanometer thickness on polysilicon film ₂(TEOS SiO ₂) film;

(2) electron beam lithography or optical lithography (248 nanometers or 193 nanometer excimer laser exposures etc.) obtain the glue pattern of 90-250 nano-scale linewidth.

(3) ashing treatment of glue: adopt oxygen plasma that glue is carried out isotropic etching, reach the purpose of dwindling live width.

(4) fluoridize and toast: use CF ₄Plasma is handled the glue surface, to improve the softening temperature of glue, baking then.

(5) to the TEOS SiO of no glue masking regional ₂Film at first carries out anisotropic etching, after removing photoresist, cleaning, to TEOS SiO ₂Figure carries out isotropic chemical corrosion, further dwindles live width, to meet the requirements of 15-50 nano-scale linewidth TEOS SiO ₂Hard mask pattern.

Step 2 etches away the natural oxide of the polysilicon surface of no glue masking regional: 300 watts of radio-frequency powers, reacting gas carbon tetrafluoride, Freon-14 CF ₄, flow 100sccm, diluent gas helium (He), flow 50sccm, operating pressure 750m τ, 35 ℃ of electrode temperatures.

Step 3 main etching-1, the polysilicon that control etches away accounts for the 80-90% of gross thickness, radio-frequency power 250-350 watt, reacting gas Cl ₂/ HBr=60-100sccm/30-50sccm, Cl ₂: HBr=2: 1, operating pressure 200-300m τ, 35 ℃ of electrode temperatures.This step can obtain fabulous anisotropic etching.

Step 4 main etching-2, this step is the polysilicon layer that etches away the 20-10% that main etching-1 stays, and exposes to gate medium, terminal point triggers and ends.This step is owing to have the adding of oxygen of proper ratio and the suitable increase of HBr ratio, makes polysilicon improve greatly to the etching selection ratio of ultra-thin gate dielectric that (＞500: 1), X-ray analysis of spectrum (XPS) shows, has in fact obtained class SiO ₂The clean deposition of film.Radio-frequency power 120-140 watt, reacting gas C1 ₂/ HBr/O ₂=60-90sccm/40-60sccm/2.5-3.5sccm, operating pressure 240-280m τ, 35 ℃ of electrode temperatures.

Step 5 over etching is the polysilicon that etching only may be remaining, and this step is because the adding of oxygen and the further increase of HBr ratio, make etching selection ratio further improve (＞＞500: 1), because of class SiO ₂The clean deposition of film further increases.Radio-frequency power 120-140 watt, reacting gas Cl ₂/ HBr/O ₂=40-80sccm/60-120sccm/2.5-3.5sccm, operating pressure 240-280m τ.

Description of drawings

Fig. 1 is TEOS SiO prepared in accordance with the present invention ₂ESEM (SEM) photo of hard mask gate figure, the grid line bar is wide to be 21.3 nanometers.

Fig. 2 is the SEM photo of the polysilicon gate etching section after Co/Ti silicide prepared in accordance with the present invention forms, and the polysilicon live width is 20.2 nanometers.

Fig. 3 grows transmission electron microscope (TEM) photo of 27 nanometer cmos device sections for the grid of succeeding in developing according to the present invention.

Embodiment

Embodiment:

Step 1 comprises:

(1) 800 ℃ of nitriding and oxidizing gate medium 1.3 nanometer of growing down;

(2) 620 ℃ of deposit 200 nano-multicrystal silicon thin films;

(3) 720 ℃ of following tetraethoxysilane thermal decomposed deposition TEOS SiO ₂Film 75 nanometers;

(4) electron beam lithography: SAL601 bears glue, forms 100-110 nano-scale linewidth glue pattern;

(5) ashing and baking: 60 watts of radio-frequency powers, reacting gas O ₂40sccm, diluent gas He60sccm, operating pressure 450m τ, 1.5 centimetres of electrode distances, 35 ℃ of electrode temperatures.The control ashing time obtains 50-60 nanometer adhesive tape live width figure.Toast 125 ℃ then, 40 minutes, slowly heating and cooling;

(6) reactive ion etching TEOS SiO ₂Film, 300 watts of radio-frequency powers, CHF ₃/ CF ₄/ Ar=50sccm/10sccm/250sccm, operating pressure 200m τ, terminal point trigger and end, and do not have quarter;

(7) cleaning of removing photoresist: 3 ^#Remove photoresist then 3 ^#Clean again 1 ^#Clean;

(8) wet-chemical etching: room temperature, HF/IPA/H ₂O=0.5%: 0.02%: 1, about 0.3 nm/sec of corrosion rate, the control etching time obtains about 20 nano-scale linewidth figures; Fig. 1 has provided the TEOS SiO that obtains after the step 1 ₂ESEM (SEM) photo of hard mask gate figure, mask gate figure lines are wide to be 21.3 nanometers.

Step 2 etching natural oxidizing layer, 300 watts of radio-frequency powers, reacting gas CF ₄, flow 100sccm, operating pressure 750m τ.

Step 3 main etching-1: etch away 85% of polysilicon gross thickness, reacting gas Cl ₂/ HBr=80sccm/40sccm=2: 1,280 watts of radio-frequency powers, operating pressure 250m τ.

Step 4 main etching-2: be etched to triggering, 130 watts of radio-frequency powers, reacting gas Cl ₂/ HBr=70sccm/50sccm=1.4: 1, O ₂=3sccm, operating pressure 260m τ.

Step 5 excessive erosion: radio-frequency power 130, reacting gas Cl ₂/ HBr=60sccm/95sccm, O ₂=3sccm, the excessive erosion time 40%.

Fig. 2 has provided the SEM photo of section behind the polysilicon gate etching after the Co/Ti silicide forms, and the polysilicon live width is 20.2 nanometers.As seen section is smooth, and is steep, is about an angle of 90 degrees.Height/wide ratio is greater than 7.Live width is lost about 5 nanometers.

Fig. 3 has provided transmission electron microscope (TEM) photo of the long 27 nanometer cmos device sections of succeeding in developing of grid, and the polysilicon section is steep, smooth.Device property is good.

Claims

1. the reactive ion etching method of a nano-scale linewidth polysilicon gate, the grid width of making is the 15-50 nanometer, its key step is:

Step 1: the SiO that on polysilicon film, forms the 15-50 nano-scale linewidth ₂Hard mask pattern

A) deposit polysilicon film on ultra-thin gate dielectric, deposit tetraethoxysilane thermal decomposition SiO then ₂Film;

B) with excimer laser or electron beam exposure, photoetching forms the glue gate figure;

C) ashing of glue is carried out isotropic etching with oxygen plasma to glue, and radio-frequency power 30-100 watt, operating pressure 200-800m τ, reacting gas oxygen, flow 20-80sccm, diluent gas helium, flow 30-120sccm, electrode spacing 1-2 centimetre, electrode temperature 30-40 ℃;

D) use CF ₄Gas is fluoridized and is toasted;

E) reactive ion etching tetraethoxysilane thermal decomposition SiO anisotropically ₂Film; The etching gas that adopts is carbon tetrafluoride Freon-14/fluoroform/argon gas, CF ₄Flow 6-30sccm, CHF ₃Flow 20-150sccm, Ar flow 150-360sccm, operating pressure 100-300m τ, radio-frequency power 200-400 watt, electrode spacing 1-2 centimetre, 0 ℃ of electrode temperature.

F) remove photoresist with wet chemistry and clean; In 120 ℃, be H with volume ratio ₂SO ₄: H ₂O ₂=4-6: 1 solution removes photoresist, 10 minutes time; Same solution cleans; Is NH in 60 ℃ with volume ratio ₄OH: H ₂O ₂: H ₂The solution of O=0.7-0.9: 1: 4-6 cleaned 5 minutes; Hot N ₂Dry in the atmosphere;

G) wet chemical etching technique under the room temperature, corrosive liquid are hydrofluoric acid/isopropyl alcohol/H of 40% ₂O=0.4-0.6%: 0.01-0.04%: 1, meet the requirements of 15-50 nano-scale linewidth TEOS SiO ₂Hard mask pattern ends;

Step 2: adopt CF ₄Etchant gas is removed the natural oxide of polysilicon surface, CF ₄Gas flow 50-150sccm, power 250-350 watt, operating pressure 650-850m τ, electrode spacing 0.7-1.0 centimetre, electrode temperature 30-40 ℃;

Step 3: main etching-1, adopt Cl ₂/ HBr mist etches away the 80-90% of polysilicon gross thickness; Cl wherein ₂/ HBr=60-100sccm/30-50sccm, radio-frequency power 250-350 watt, operating pressure 200-300m τ;

Step 4: main etching-2, adopt Cl ₂/ HBr/O ₂Mist is etched to terminal point and only triggers; Cl ₂/ HBr/O ₂=60-80sccm/45-65sccm/2.5-3.5sccm, radio-frequency power 120-140 watt, operating pressure 240-280m τ;

Step 5: over etching, adopt Cl ₂/ HBr/O ₂=40-80sccm/70-120sccm/2.5-3.5sccm mist, radio-frequency power 120-140 watt, operating pressure 240-280m τ.

2. lithographic method according to claim 1, the thick 1.2-5.0 nanometer of gate medium in the step 1 wherein, polysilicon bed thickness 100-300 nanometer.

3. lithographic method according to claim 1, wherein step 2 is the natural oxides that etch away the polysilicon surface of no masked areas.

4. lithographic method according to claim 1, wherein main etching in the step 4-the 2nd is etched to gate medium and only exposes.

5. lithographic method according to claim 1, wherein step 5 over etching is that etching only may remaining polysilicon.