CN112582263A - Improvement method for punctiform residues - Google Patents

Improvement method for punctiform residues Download PDF

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Publication number
CN112582263A
CN112582263A CN201910940896.4A CN201910940896A CN112582263A CN 112582263 A CN112582263 A CN 112582263A CN 201910940896 A CN201910940896 A CN 201910940896A CN 112582263 A CN112582263 A CN 112582263A
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gap
wafer
etching
upper electrode
oxide layer
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CN201910940896.4A
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CN112582263B (en
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樊亚男
朱光源
王毅
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Yangzhou Yangjie Electronic Co Ltd
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Yangzhou Yangjie Electronic Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32568—Relative arrangement or disposition of electrodes; moving means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching

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  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A method for improving punctate residue. Relates to the technical field of manufacturing of discrete devices in the semiconductor manufacturing technology, in particular to a point-like residue improving method. The wafer etching residual method is convenient to operate and can effectively avoid the influence of an oxide layer or particles. In the invention, after the wafer is conveyed in place, the Gap is adjusted and stabilized to 0.9 cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s by the power of 250W and CF4 of 200sccm, and a natural oxide layer on the surface of the Wafer is etched; on the premise of ensuring the BT Step etching rate, the BT Step Gap (the Gap between the silicon Wafer and the upper electrode in the penetrating etching Step) and the ME Step Gap (the Gap between the silicon Wafer and the upper electrode in the main etching Step) are adjusted to be consistent, so that the defect introduced on the surface of the Wafer (silicon Wafer) in the downward movement process of the upper electrode is avoided, the dot-shaped residue of Poly (polycrystalline silicon) is improved, and the product yield is improved.

Description

Improvement method for punctiform residues
Technical Field
The invention relates to the technical field of manufacturing of discrete devices in the semiconductor manufacturing technology, in particular to a point-like residue improving method.
Background
Gap is the distance between the upper electrode and the lower electrode of the machine, and Lam4420 is movable Gap for improving etching uniformity and facilitating transmission. The method mainly comprises the steps of stabilizing a machine table Gap and reaction gas, introducing the reaction gas (CF 4, HBr and Cl 2) into a cavity, starting RF, ionizing the reaction gas, reacting the plasma with an etching medium, controlling the pressure of the cavity through the angle change of a butterfly valve, carrying out physical bombardment and chemical reaction on a silicon wafer, and selectively removing the region needing to be removed
The poly-etching usually comprises three main etching steps of BT step, ME step and OE step. This allows the anisotropic etching and the selection ratio to be optimized in different etching steps
(1) BT, pre-etching, wherein CF4 gas is mainly used for removing a natural oxide layer on the surface of Poly;
(2) ME (main etching), namely a main etching step, wherein most of polycrystalline silicon on the surface of the wafer is etched by mainly using HBr, Cl2 and He mixed gas, the etching of the step requires high selectivity, high speed and high uniformity, the combination of HBr + Cl2 has the characteristics of high selectivity and high speed, good uniformity is achieved by optimizing the Gap of a machine table, and the Gap is 0.9 cm;
(3) and OE, an over-etching step, mainly using HBr and Cl2, for removing etching residues caused by front-end deposition and PL etching uniformity, ensuring high selectivity ratio of the gate oxide layer and obtaining ideal anisotropic side wall profile.
In the Wafer processing in the prior art, Gap needs to be adjusted for multiple times in different processing steps, the Gap is 1.2cm in an initial state generally, after BT (BT) step is finished, the Gap needs to be stabilized to 0.9cm to run ME (ME) and OE (OE-engine) and after etching is finished, the Gap returns to 5.5cm and is transmitted out of Wafer, and the operation is finished. When the BT step is switched to the ME (main etching) step, Gap movement has the risk of introducing defects or leaking impurity gas into a cavity, the introduced defects can form a barrier layer on the surface of the Poly, and the leaked impurity gas can enable the surface of the Poly to produce a natural oxide layer again, so that etching point-like residues are caused.
Disclosure of Invention
Aiming at the problems, the invention provides a wafer etching residue method which is convenient to operate and can effectively avoid the influence of an oxide layer or particles.
The technical scheme of the invention is as follows: the method comprises the following steps:
1) the wafer is transferred into the reaction cavity in the initial state of Gap;
2) and pre-etching: after the wafer is conveyed in place, adjusting Gap to be stable to 0.9 cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s by the power of 250W and CF4 of 200sccm, and a natural oxide layer on the surface of the Wafer is etched;
3) after the pre-etching is finished, operating main etching and over-etching to finish the etching of the polycrystalline silicon;
4) and 3) after the step 3) is finished, the Gap is restored to the initial state and transferred out of the Wafer, and the operation is finished.
The initial state of Gap is 5.5 cm.
In the invention, after the wafer is conveyed in place, the Gap is adjusted and stabilized to 0.9 cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s by the power of 250W and CF4 of 200sccm, and a natural oxide layer on the surface of the Wafer is etched; on the premise of ensuring the BT Step etching rate, the BT Step Gap (the Gap between the silicon Wafer and the upper electrode in the penetrating etching Step) and the ME Step Gap (the Gap between the silicon Wafer and the upper electrode in the main etching Step) are adjusted to be consistent, so that the defect introduced on the surface of the Wafer (silicon Wafer) in the downward movement process of the upper electrode is avoided, the dot-shaped residue of Poly (polycrystalline silicon) is improved, and the product yield is improved.
Drawings
Figure 1 is a schematic structural view of the initial state of the present invention,
FIG. 2 is a schematic of the structure of BT, ME and OE states,
figure 3 is a schematic diagram of the state structure after completion of the job,
FIG. 4 is a schematic diagram of the structure of the present application before etching,
FIG. 5 is a schematic diagram of the etched structure of the present invention,
figure 6 is a schematic diagram of the structure before the leak-in impurity etch,
FIG. 7 is a schematic diagram of the structure after the leak-in impurity etch;
in the figure, 1 is an upper electrode, 2 is a lower electrode, 3 is a native oxide layer, and 4 is a polysilicon layer.
Detailed Description
The present invention is shown in fig. 1-3, in which a is Gap in an initial state, b is Gap in a machining state, and c is Gap after machining is completed, and a method for improving dotted residues comprises the following steps:
1) the wafer is transferred into the reaction cavity in the initial state of Gap; between the upper electrode 1 and the lower electrode 2;
2) and pre-etching: after the wafer is conveyed in place, adjusting Gap to be stable to 0.9 cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s by the power of 250W and CF4 of 200sccm, and the natural oxide layer 3 on the surface of the Wafer is etched;
3) after the pre-etching is finished, operating main etching and over-etching to finish the etching of the polycrystalline silicon layer 4; (the main etching and the over-etching respectively adopt the same processes as the prior art and belong to the prior art)
4) And 3) after the step 3) is finished, the Gap is restored to the initial state and transferred out of the Wafer, and the operation is finished.
The initial state of Gap is 5.5 cm.
After optimization, when the BT step is switched to the ME (main etching) step, the Gap does not move any more, so that the risk of introducing defects or leaking impurity gas into a cavity is avoided, and the phenomenon of figure 7 is avoided, wherein 5 is a GOX layer (gate oxide layer) and 6 is impurity, so that the defect of etching is directly caused; the scheme increases the pressure and power of the BT step during operation, and ensures that the etching rate of the BT step cannot be reduced.
The disclosure of the present application also includes the following points:
(1) the drawings of the embodiments disclosed herein only relate to the structures related to the embodiments disclosed herein, and other structures can refer to general designs;
(2) in case of conflict, the embodiments and features of the embodiments disclosed in this application can be combined with each other to arrive at new embodiments;
the above embodiments are only embodiments disclosed in the present disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the scope of the claims.

Claims (2)

1. A method for improving punctiform residues is characterized by comprising the following steps:
1) the wafer is transferred into the reaction cavity in the initial state of Gap;
2) and pre-etching: after the wafer is conveyed in place, adjusting Gap to be stable to 0.9 cm; the pressure in the cavity is kept at 650mt, the BT step is operated for 35s by the power of 250W and CF4 of 200sccm, and a natural oxide layer on the surface of the Wafer is etched;
3) after the pre-etching is finished, operating main etching and over-etching to finish the etching of the polycrystalline silicon;
4) and 3) after the step 3) is finished, the Gap is restored to the initial state and transferred out of the Wafer, and the operation is finished.
2. The method for improving punctate residues according to claim 1, wherein the Gap initial state is 5.5 cm.
CN201910940896.4A 2019-09-30 2019-09-30 Punctiform residue improvement method Active CN112582263B (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854136A (en) * 1996-03-25 1998-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Three-step nitride etching process for better critical dimension and better vertical sidewall profile
CN1700426A (en) * 2004-05-21 2005-11-23 中国科学院微电子研究所 Method for etching 15-50 nanowire wide polycrystalline silicon gate
CN1731286A (en) * 2004-08-04 2006-02-08 上海华虹Nec电子有限公司 Method of through hole etching for RF device products
CN1731565A (en) * 2004-08-04 2006-02-08 上海华虹Nec电子有限公司 Etching method for 0.18 micrometre contact hole
JP2006345001A (en) * 2006-09-08 2006-12-21 Tokyo Electron Ltd Plasma etching method and plasma etching apparatus
CN101728254A (en) * 2008-10-21 2010-06-09 中芯国际集成电路制造(北京)有限公司 Method for manufacturing gate on wafer
CN104425237A (en) * 2013-08-20 2015-03-18 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854136A (en) * 1996-03-25 1998-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Three-step nitride etching process for better critical dimension and better vertical sidewall profile
CN1700426A (en) * 2004-05-21 2005-11-23 中国科学院微电子研究所 Method for etching 15-50 nanowire wide polycrystalline silicon gate
CN1731286A (en) * 2004-08-04 2006-02-08 上海华虹Nec电子有限公司 Method of through hole etching for RF device products
CN1731565A (en) * 2004-08-04 2006-02-08 上海华虹Nec电子有限公司 Etching method for 0.18 micrometre contact hole
JP2006345001A (en) * 2006-09-08 2006-12-21 Tokyo Electron Ltd Plasma etching method and plasma etching apparatus
CN101728254A (en) * 2008-10-21 2010-06-09 中芯国际集成电路制造(北京)有限公司 Method for manufacturing gate on wafer
CN104425237A (en) * 2013-08-20 2015-03-18 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method

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