CN100413034C

CN100413034C - Polysilicon etching technology capable of preventing device from plasma damage

Info

Publication number: CN100413034C
Application number: CNB2005101263698A
Authority: CN
Inventors: 赵强
Original assignee: Beijing North Microelectronics Co Ltd
Current assignee: Beijing North Microelectronics Co Ltd
Priority date: 2005-12-08
Filing date: 2005-12-08
Publication date: 2008-08-20
Anticipated expiration: 2025-12-08
Also published as: CN1851880A

Abstract

The present invention provides a polysilicon etching technology capable of preventing device from plasma damage, which comprises a through step, a main etching step, a staying step, an over etching step and a silicon chip unloading step. The method of the present invention reduces the charge accumulation on the surface of a silicon chip in the polysilicon etching process, and thereby, the plasma damage is reduced. Moreover, the process is simple, does not need to make the optimum design on a hardware system of equipment and has fine adaptability on the device of various structures and types.

Description

A kind of polycrystalline silicon etching process that can prevent the device plasma damage

Technical field

The present invention relates to semiconductor fabrication process, specifically, relate to the method that reduces plasma damage in the deep submicron process.

Background technology

Along with the semiconductor manufacturing enters into the deep-submicron stage, the chip features size is further dwindled, and the integrated level of integrated circuit constantly increases, and semiconductor fabrication process is had higher requirement.Should reduce plasma damage, because it can cause the degeneration of semiconductor device electric property for this reason as far as possible.

Existing etching technics step comprises and running through step, main etching step, over etching step, do not have the damage of article on plasma body to protect targetedly.

The mechanism of plasma damage mainly contain following some: the accumulative total effect of electric charge, the ionisation effect of UV ray, influences such as the antenna effect of design layout.Electric charge accumulative total effect most importantly wherein, its mechanism be as shown in Figure 1: electric charge accumulates in silicon chip surface in technical process, produces tunnelling current to back to a certain degree, thereby forms the damage of dielectric layer electric stress.

U.S. Pat provides a kind of method of protecting semiconductor-based bottom material to avoid the plasma current damage for No. 6309979; the plasma main etching that this method is carried out comprises two steps: the first step is main 1 (ME1) of quarter; adopt high-power lithographic method; therefore the density of the plasma that is produced is also very big; second step was main 2 (ME2) of quarter; select the small-power setting for use, though etching speed is slow, the charging damage that causes is also very little.Typical technology such as table 1:

Table 1ME1 and the contrast of ME2 technology

	RFs (W)	RFb (W)	Pressure (mT)	Cl ₂ (sccm)	BCl ₃ (sccm)	N ₂ (sccm)
	RFs (W)	RFb (W)	Pressure (mT)	Cl ₂ (sccm)	BCl ₃ (sccm)	N ₂ (sccm)	ME1	400-700	100-300	6-20	10-150	10-150	0-25
ME2	0-150	100-400	6-50	10-150	10-150	0-25	ME1	400-700	100-300	6-20	10-150	10-150	0-25

But still there is defective in this method: 1, process window and process results are produced certain influence; 2, can't solve the damage that in the silicon chip unloading process silicon chip is caused.So the method that still needs to provide new is to avoid the damage of deep submicron process ionic medium body.

Summary of the invention

(1) technical problem that will solve

Purpose of the present invention aims to provide a kind of new method, makes it can reduce the electric charge that silicon chip working process the produced accumulation that comprises the silicon chip unloading process, reduces plasma damage.

(2) technical scheme

For achieving the above object, the invention provides the method that a kind of new minimizing deep submicron process ionic medium body damages, this method may further comprise the steps: run through step, main etching step, the step of stop, over etching step and silicon chip unloading and go on foot.

The process conditions in wherein said stop step are: pendulum valve standard-sized sheet, upper/lower electrode power is 0w, gas flow is 0sccm, time is 5-300s, the preferred time is 20-30s, if main etching step process overlong time (＞60s) or upper/lower electrode power excessive (top electrode＞400W, lower electrode power＞60W), then stop the corresponding growth of time in step; Otherwise then reduce.

The process conditions in wherein said silicon chip unloading step are: chamber pressure 10-80mT, and upper electrode power 200-400W and adopt slope mode (Ramp Down) to close, slope time 1-5 second, lower electrode power 0W, process gas uses Ar or O ₂, flow is 200-300sccm, process time 1-10s.Preferred processing condition is: chamber pressure 15mT, and upper electrode power 300W, slope time 2s, lower electrode power 0W, process gas flow are 200sccm, process time 5s.

Because method of the present invention is when carrying out electrostatic chuck electrode reverse turn operation, the top electrode build-up of luminance, and top electrode adopts ramp mode to close, and avoided the electric charge accumulation in this process.

Causing the main cause of electric charge accumulation in the existing etching technics is that plasma distribution is inhomogeneous, and the silicon chip unloading misoperation etc., and the present invention mainly optimizes technical process from above two aspects.

(3) beneficial effect

Method of the present invention has reduced the electric charge accumulation of silicon chip surface in polycrystalline silicon etching process, reduced plasma damage.And technology is simple, need not the hardware system of equipment is optimized design, and different shape, types of devices are all had good adaptability.

Description of drawings

Fig. 1 is a plasma damage mechanism schematic diagram;

Fig. 2 is the FE-SEM picture after the existing technology etching;

Fig. 3-5 is the FE-SEM picture after the technology etching of the present invention;

Optical viewer is the HitachiS-4700 field emission scanning electron microscope.

Embodiment

Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment only to be used to the present invention is described and be not used in and limit the scope of the invention.

The grid structure that relates in the following example is: substrate silicon chip → silicon dioxide ( ) → polysilicon (

) → silicon oxynitride (

) → photoresistance (

).

The following example carries out on northern microelectronics inductive couple plasma etching machine (200mm silicon chip erosion machine), can reflect the 130-180nm process results, need to prove, technology has downward compatibility, in the time of can satisfying high-end 65-90nm technology, the 130-250nm technology of low side etc. can meet the demands fully.The present invention is applicable to 200mm-300mm silicon chip erosion machine simultaneously.

Embodiment 1

In the etching technics, at first import silicon chip into etching reaction chamber, fixing by electrostatic chuck absorption, chamber temp is controlled to be 60 ℃, silicon temperature control system design temperature is 60 ℃, blow system pressure and be set at 8T for improving the He gas back of the body that temperature homogeneity adds, after the auxiliary process conditional stability, carry out etching technics.

BT (break through runs through) goes on foot etching: chamber pressure 7mT, last RF power 300W, following RF power 40W, process gas CF ₄Flow 50sccm, process time 5s.

Main etching step etching: chamber pressure 10mT, last RF power 350W, following RF power 40W, process gas is Cl ₂30sccm, HBr 170sccm, HeO ₂The mist of (the two volume ratio is 7: 3, down together) 15sccm, process time control detects control by end-point detecting system.

Over etching step etching: chamber pressure 80mT, last RF power 350W, following RF power 40W, process gas are 150sccm HBr, 100sccm He, 15sccm HeO ₂The mist of forming, process time 50s.

After etching technics is finished, observe the flaking result, see shown in Figure 2 by FE-SEM.Find to have little raceway groove (Microtrench) phenomenon near lines, this phenomenon is relevant with the surface charge skewness, and promptly it is relevant with potential plasma damage.

Embodiment 2

Adopt the method for embodiment 1, its difference is that main etching step back increases the stop step, and concrete technology is: pendulum valve standard-sized sheet, and upper/lower electrode power is 0w, and gas flow is 0sccm, and the time is 30s.

The concrete technology in silicon chip unloading step is in addition: chamber pressure 15mT, and upper electrode power 300W (adopting ramp mode 2s to close), lower electrode power 0W, the flow of process gas Ar are 200sccm, process time 5s.

The FE-SEM flaking the results are shown in shown in Figure 3, does not find little raceway groove (Microtrench) phenomenon, illustrates that potential plasma damage obviously improves.

Embodiment 3

Adopt the method for embodiment 2, its difference is that main etching step back increases the stop step, and concrete technology is: pendulum valve standard-sized sheet, and upper/lower electrode power is 0w, and gas flow is 0sccm, and the time is 300s.Wherein the concrete technology in silicon chip unloading step is: chamber pressure 10mT, upper electrode power 200W (adopting ramp mode 5s to close), lower electrode power 0W, process gas O ₂Flow be 300sccm, process time 5s.

FE-SEM the results are shown in shown in Figure 4, does not find micro-channel phenomenon.

Embodiment 4

Adopt the method for embodiment 2, its difference is that main etching step back increases the stop step, and concrete technology is: pendulum valve standard-sized sheet, and upper/lower electrode power is 0w, and gas flow is 0sccm, and the time is 5s.

Wherein the concrete technology in silicon chip unloading step is: chamber pressure 80mT, and upper electrode power 400W (adopting ramp mode 1s to close), lower electrode power 0W, the flow of process gas Ar are 250sccm, process time 1s.

The FE-SEM flaking the results are shown in shown in Figure 5, does not find micro-channel phenomenon.

Claims

1. polycrystalline silicon etching process that can prevent the device plasma damage, may further comprise the steps: run through the step, the main etching step, over etching step and silicon chip unloading step, it is characterized in that, increased the stop step after step at main etching, the process conditions in described stop step are: pendulum valve standard-sized sheet, upper/lower electrode power is 0w, gas flow is 0sccm, time is 5-300s, and the process conditions in described silicon chip unloading step are: chamber pressure 10-80mT, upper electrode power 200-400W, and adopt the slope mode to close, slope time 1-5s, lower electrode power 0W, process gas are Ar or O ₂, flow is 200-400sccm, process time 1-10s.

2. polycrystalline silicon etching process as claimed in claim 1 is characterized in that the time in described stop step is 20-30s.

3. polycrystalline silicon etching process as claimed in claim 1 or 2 is characterized in that described silicon chip unloading step middle chamber pressure 15mT, upper electrode power 300W, and slope time 2s, process gas flow are 200sccm, the process time is 5s.