CN101533772A - Technological method for etching tungsten gate - Google Patents
Technological method for etching tungsten gate Download PDFInfo
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- CN101533772A CN101533772A CN200810101804A CN200810101804A CN101533772A CN 101533772 A CN101533772 A CN 101533772A CN 200810101804 A CN200810101804 A CN 200810101804A CN 200810101804 A CN200810101804 A CN 200810101804A CN 101533772 A CN101533772 A CN 101533772A
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Abstract
The invention discloses a technological method for etching tungsten gate, pertaining to the field of semiconductor processing and manufacturing; the method comprises the following steps: a semiconductor silicon wafer is moved into a reaction chamber and heated to a high temperature; a first reaction gas is pumped into the reaction chamber; radio frequency power is imposed on the reaction chamber after the airflow of the first reaction gas becomes stable; and then, the first reaction gas etches the tungsten silicide layer or tungsten layer of the semiconductor silicon wafer; after the etching is finished, the pumping of the first reaction gas and the imposing of the radio frequency power are stopped; a second reaction gas is pumped into the reaction chamber; the radio frequency power is imposed on the reaction chamber after the airflow of the second reaction gas becomes stable; the second reaction gas etches the polysilicon layer of the semiconductor silicon wafer; after the etching is finished, the pumping of the second reaction gas and the imposing of the radio frequency power are stooped; and the semiconductor silicon wafer is moved out of the reaction chamber. The technological method improves the selection ratio between the tungsten silicide layer or tungsten layer and the polysilicon layer in the tungsten gate etching technology.
Description
Technical field
The present invention relates to field of semiconductor processing and manufacturing, particularly a kind of process of etching tungsten gate.
Background technology
In the machining process of semicon industry large scale integrated circuit, need process the figure of fine dimension usually at silicon chip surface, wherein the tungsten gate etching process is widely used in the manufacturing of memory chip or flash memory disk chip.Tungsten grid structure generally is divided into multilayer, mainly comprises tungsten silicide layer/tungsten layer and polysilicon layer or the like, and wherein the thickness of tungsten silicide layer has determined the size of memory chip or flash chip memory space.The lithographic method that the tungsten gate etching process is relatively more commonly used is the distribution etching, and promptly tungsten silicide layer/tungsten layer was finished with main etching and two steps of over etching, and polysilicon layer adopts main etching and two steps of over etching to finish too.Tungsten silicide layer/tungsten layer main etching mainly is by the mist that applies certain power tungsten silicide layer/tungsten layer to be carried out etching, and mist mainly comprises chlorine and oxygen, can also comprise inert gases such as helium; Over etching also is further tungsten silicide layer/tungsten layer to be carried out etching by the mist identical with the main etching use that applies certain power, and its main purpose is that all tungsten silicide layers/tungsten layer etching is finished.The main etching of polysilicon layer and over etching also are by the mist that applies certain power polysilicon layer to be carried out etching, and mist mainly comprises chlorine, hydrogen bromide and oxygen, can also comprise inert gases such as helium.Mist carries out the plasma etching of certain hour to tungsten silicide layer/tungsten layer and polysilicon layer, and the length of etch period depends on the size of the consumption and the power of mist.
Along with the continuous increase to the chip-stored space requirement, the thickness of tungsten silicide layer/tungsten layer also can increase thereupon.Yet, the thickness of tungsten silicide layer/tungsten layer is big more, the difficulty of etching processing technology is also just big more, if tungsten silicide layer/tungsten layer to the selection of polysilicon layer than not high enough, the residue (as shown in Figure 1) that will certainly cause tungsten silicide layer/tungsten layer tungstenic composition in the etching course of processing, will influence the interface of tungsten silicide layer/tungsten layer and polysilicon layer like this, cause polysilicon layer can be remained, thereby have influence on the yield of product because of remaining stopping also of tungstenic composition.
Summary of the invention
For tungsten silicide layer/tungsten layer of improving semi-conductor silicon chip selection ratio to the etch rate of polysilicon layer, and improve the product yield, the invention provides a kind of process of etching tungsten gate, described method comprises:
Steps A: semi-conductor silicon chip is moved to reaction chamber inside, and described semi-conductor silicon chip is heated to high temperature;
Step B: first reacting gas is fed described reaction chamber inside, and treat to apply radio-frequency power to described reaction chamber behind the described first reacting gas steady air current;
Step C: described first reacting gas carries out etching to the tungsten silicide layer/tungsten layer of described semi-conductor silicon chip, and after etching is finished, stops to import described first reacting gas and applying radio-frequency power to described reaction chamber;
Step D: second reacting gas is fed described reaction chamber inside, and treat to apply radio-frequency power to described reaction chamber behind the described second reacting gas steady air current;
Step e: described second reacting gas carries out etching to the polysilicon layer of described semi-conductor silicon chip, and after etching is finished, stops to import described second reacting gas and applying radio-frequency power to described reaction chamber;
Step F: described semi-conductor silicon chip is shifted out described reaction chamber.
The step that in the described steps A described semi-conductor silicon chip is heated to high temperature specifically is to realize by the temperature that control is fixed on the electrostatic chuck internal liquid of described semi-conductor silicon chip below.
Described steps A is specially: semi-conductor silicon chip is moved to reaction chamber inside, and described semi-conductor silicon chip is heated to 75 degrees centigrade.
Described step B specifically comprises:
Step B1: first reacting gas is fed described reaction chamber inside, and described reaction chamber pressure inside is controlled at less than 50mTorr;
Step B2: behind the described first reacting gas steady air current, the radio-frequency power that applies 100-300w and 10-50w respectively to the top electrode and the bottom electrode of described reaction chamber.
Described step D specifically comprises:
Step D1: second reacting gas is fed described reaction chamber inside, and described reaction chamber pressure inside is controlled at 50-100mTorr;
Step D2: behind the described second reacting gas steady air current, the radio-frequency power that applies 300-500w and 10-50w respectively to the top electrode and the bottom electrode of described reaction chamber.
Described first reacting gas is chlorine-containing gas or the mist that contains chlorine-containing gas.
Described first reacting gas is the mist of chlorine and oxygen; Wherein, described chlorine gas flow is 50-200sccm, and described oxygen gas flow is 15-30sccm.
Described second reacting gas is chlorine-containing gas or the mist that contains chlorine-containing gas.
Described second reacting gas is the mist of chlorine, oxygen and hydrogen bromide; Wherein, described bromize hydrogen gas flow is 50-300sccm, and described chlorine gas flow is 50-200sccm, and described oxygen gas flow is 0-10sccm.
The beneficial effect of technical scheme provided by the invention is: the present invention is by under hot environment, tungsten silicide layer/tungsten layer and polysilicon layer to semi-conductor silicon chip carry out plasma etching, can effectively improve in the tungsten gate etching process tungsten silicide/tungsten layer to the selection ratio of polysilicon layer, it is residual to remove silicide, improves the product yield.
Description of drawings
Fig. 1 has the remaining schematic diagram of the tungsten layer of containing in the semiconductor silicon dies etching process in the prior art;
Fig. 2 is the process method flow chart of the etching tungsten gate that provides of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
The technical scheme difference from prior art that the embodiment of the invention provides is: the embodiment of the invention is that tungsten grid structural semiconductor silicon chip surface to be processed is heated to high temperature, and under this hot environment semi-conductor silicon chip is carried out etching.Be example so that tungsten grid structural semiconductor silicon chip surface temperature is heated to 75 degrees centigrade below, set forth the technical scheme that the embodiment of the invention provides.
Referring to Fig. 2, the process of the etching tungsten gate that the embodiment of the invention provides specifically may further comprise the steps:
Step 101: tungsten grid structural semiconductor silicon chip to be processed is moved to reaction chamber inside, and the surface of semi-conductor silicon chip is heated to 75 degrees centigrade;
The surface of tungsten grid structural semiconductor silicon chip is heated to 75 degrees centigrade can realize by existing multiple technologies means, for example: can the semi-conductor silicon chip surface be heated to 75 degrees centigrade by the temperature that control is fixed on the electrostatic chuck internal liquid of tungsten grid structural semiconductor silicon chip below; In actual applications, because there is thermal loss in electrostatic chuck, so in order to make the semi-conductor silicon chip surface can reach 75 degrees centigrade, usually need the temperature of liquid in the control electrostatic chuck to be higher than 75 degrees centigrade, the temperature of liquid can be provided with according to the size and the ambient temperature of electrostatic chuck area under the actual scene in the electrostatic chuck; The temperature of liquid realizes the semiconductor silicon chip surface is heated to 75 degrees centigrade in can adopting the control electrostatic chuck, the technological means that the realization that can also adopt those skilled in the art to habitually practise is heated the semiconductor silicon chip surface, the embodiment of the invention does not limit the specific implementation technological means that the semi-conductor silicon chip surface is heated to high temperature;
Step 102: first reacting gas is fed reaction chamber inside, and treat to apply radio-frequency power to reaction chamber behind the first reacting gas steady air current;
Since the tungsten grid material can with chlorine-containing gas (Cl for example
2) chemical reaction takes place, thus feed the mist that first reacting gas of reaction chamber is generally chlorine-containing gas or contains chlorine-containing gas, for example: Cl
2Or Cl
2With other gas (O
2, N
2, CF
4, SF
6, NF
3, gas such as He and HBr) mixture; In actual applications, in order to carry out etching to the semiconductor silicon chip surface with stable speed, usually make the inner pressure stable state that keeps of reaction chamber, behind the first reacting gas steady air current that for example can be to be fed, come the stable of realization response chamber interior pressure by the adjusting control valve door; In concrete production practices, can control the reaction chamber pressure inside less than 50mTorr, can be specially 10-20mTorr;
Generally, be separately installed with top electrode and bottom electrode in the above and below of reaction chamber, and on top electrode and bottom electrode, apply radio-frequency power respectively, and can make the inner plasma environment that forms of reaction chamber like this, help the even etching of semi-conductor silicon chip; In concrete production practices, top electrode can apply the radio-frequency power of 100-300w, and bottom electrode can apply the radio-frequency power of 10-50w;
Step 103: in reaction chamber inside, first reacting gas carries out main etching and over etching respectively to the tungsten silicide layer/tungsten layer of semiconductor silicon chip surface, and after etching is finished, stops to import first reacting gas and applying radio-frequency power to reaction chamber;
In the present embodiment, carry out in the process of main etching and over etching at tungsten silicide layer/tungsten layer the semiconductor silicon chip surface, the mist that first reacting gas that uses is made up of chlorine and oxygen, wherein the chlorine gas flow can be controlled at 50-200sccm, and the oxygen gas flow can be controlled at 15-30sccm;
In reaction chamber inside, first reacting gas (chlorine and oxygen) carries out plasma etching to the tungsten silicide layer/tungsten layer of semiconductor silicon chip surface, and its operation principle is: under the electric field action that produces between top electrode and the bottom electrode, and Cl
2And O
2Be ionized to charged ion, molecule, electronics and atomic group, the charged particle that ionization generates is diffused into semi-conductor silicon chip surface (tungsten grid material), and chemical reaction takes place with it, generate the silicon tetrachloride of gaseous state and the tungsten chloride mixture of on-gaseous, the silicon tetrachloride of gaseous state is detached reaction chamber by vacuum equipment, and the tungsten chloride mixture of on-gaseous remains in the semi-conductor silicon chip surface; The chemical reaction of chlorine and tungsten grid material can increase reaction speed greatly under hot conditions, stimulate the increase of product; In actual applications, etch period can be set as the case may be, for example etch period (main etching and over etching) can be set to 40-80s;
Step 104: second reacting gas is fed reaction chamber inside, and treat to apply radio-frequency power to reaction chamber behind the second reacting gas steady air current;
Since polycrystalline silicon material can with chlorine-containing gas (Cl for example
2) chemical reaction takes place, thus feed the mist that second reacting gas of reaction chamber is generally chlorine-containing gas or contains chlorine-containing gas, for example: Cl
2Or Cl
2With other gas (O
2, N
2, CF
4, SF
6, NF
3, gas such as He and HBr) mixture; In actual applications, in order to carry out etching to the semiconductor silicon chip surface with stable speed, usually make the inner pressure stable state that keeps of reaction chamber, behind the second reacting gas steady air current that for example can be to be fed, come the stable of realization response chamber interior pressure by the adjusting control valve door; In concrete production practices, can control the reaction chamber pressure inside at 50-100mTorr;
Generally, be separately installed with top electrode and bottom electrode in the above and below of reaction chamber, and on top electrode and bottom electrode, apply radio-frequency power respectively, and can make the inner plasma environment that forms of reaction chamber like this, help the even etching of semi-conductor silicon chip; In concrete production practices, top electrode can apply the radio-frequency power of 300-500w, is specifically as follows the radio-frequency power of 350-400w, and bottom electrode can apply the radio-frequency power of 10-50w;
Step 105: in reaction chamber inside, second reacting gas carries out main etching and over etching respectively to the polysilicon layer of semi-conductor silicon chip, and after etching is finished, stops to import second reacting gas and applying radio-frequency power to reaction chamber;
In the present embodiment, carry out in the process of main etching and over etching at polysilicon layer semi-conductor silicon chip, the mist that second reacting gas that uses is made up of chlorine, hydrogen bromide and oxygen, wherein the bromize hydrogen gas flow can be controlled at 50-300sccm, is specially 200-250sccm; The chlorine gas flow can be controlled at 50-200sccm, is specially 100-150sccm; The oxygen gas flow can be controlled at 0-10sccm;
Step 106: the semi-conductor silicon chip that etching is intact shifts out reaction chamber, and after this semi-conductor silicon chip being carried out the series of processes processing, detects the yield of this semi-conductor silicon chip finished product;
Generally, after the intact semi-conductor silicon chip of etching shifts out reaction chamber, also to carry out after a series of long rete, shop photoresist, development, etching and cleaning or the like operation finishes, detect the yield of this semi-conductor silicon chip finished product again semi-conductor silicon chip.
The embodiment of the invention is by under hot environment, and the tungsten silicide layer/tungsten layer and the polysilicon layer of semi-conductor silicon chip carried out plasma etching, (the Cl for example because tungsten grid material and chlorine-containing gas
2) chemical reaction velocity that takes place is greater than the chemical reaction velocity of polycrystalline silicon material with the chlorine-containing gas generation, and the degree of the chemical reaction temperature influence that polycrystalline silicon material and chlorine-containing gas take place is more steady, so so just improved the selection ratio of tungsten silicide layer/tungsten layer to the etch rate of polysilicon layer, improved the product yield effectively, it is residual simultaneously can also effectively to remove silicide, and can see that the Si-gate lines after the etching have reasonable cross section pattern; In addition, because etch rate so just can shorten etch period than very fast under the hot environment, improved production efficiency.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the process of an etching tungsten gate is characterized in that, described method comprises:
Steps A: semi-conductor silicon chip is moved to reaction chamber inside, and described semi-conductor silicon chip is heated to high temperature;
Step B: first reacting gas is fed described reaction chamber inside, and treat to apply radio-frequency power to described reaction chamber behind the described first reacting gas steady air current;
Step C: described first reacting gas carries out etching to the tungsten silicide layer/tungsten layer of described semi-conductor silicon chip, and after etching is finished, stops to import described first reacting gas and applying radio-frequency power to described reaction chamber;
Step D: second reacting gas is fed described reaction chamber inside, and treat to apply radio-frequency power to described reaction chamber behind the described second reacting gas steady air current;
Step e: described second reacting gas carries out etching to the polysilicon layer of described semi-conductor silicon chip, and after etching is finished, stops to import described second reacting gas and applying radio-frequency power to described reaction chamber;
Step F: described semi-conductor silicon chip is shifted out described reaction chamber.
2. the process of etching tungsten gate as claimed in claim 1, it is characterized in that the step that in the described steps A described semi-conductor silicon chip is heated to high temperature specifically is to realize by the temperature that control is fixed on the electrostatic chuck internal liquid of described semi-conductor silicon chip below.
3. the process of etching tungsten gate as claimed in claim 1 is characterized in that, described steps A is specially: semi-conductor silicon chip is moved to reaction chamber inside, and described semi-conductor silicon chip is heated to 75 degrees centigrade.
4. the process of etching tungsten gate as claimed in claim 1 is characterized in that, described step B specifically comprises:
Step B1: first reacting gas is fed described reaction chamber inside, and described reaction chamber pressure inside is controlled at less than 50mTorr;
Step B2: behind the described first reacting gas steady air current, the radio-frequency power that applies 100-300w and 10-50w respectively to the top electrode and the bottom electrode of described reaction chamber.
5. the process of etching tungsten gate as claimed in claim 1 is characterized in that, described step D specifically comprises:
Step D1: second reacting gas is fed described reaction chamber inside, and described reaction chamber pressure inside is controlled at 50-100mTorr;
Step D2: behind the described second reacting gas steady air current, the radio-frequency power that applies 300-500w and 10-50w respectively to the top electrode and the bottom electrode of described reaction chamber.
6. as the process of claim 1 or 4 described etching tungsten gates, it is characterized in that described first reacting gas is chlorine-containing gas or the mist that contains chlorine-containing gas.
7. the process of etching tungsten gate as claimed in claim 6 is characterized in that, described first reacting gas is the mist of chlorine and oxygen; Wherein, described chlorine gas flow is 50-200sccm, and described oxygen gas flow is 15-30sccm.
8. as the process of claim 1 or 5 described etching tungsten gates, it is characterized in that described second reacting gas is chlorine-containing gas or the mist that contains chlorine-containing gas.
9. the process of etching tungsten gate as claimed in claim 8 is characterized in that, described second reacting gas is the mist of chlorine, oxygen and hydrogen bromide; Wherein, described bromize hydrogen gas flow is 50-300sccm, and described chlorine gas flow is 50-200sccm, and described oxygen gas flow is 0-10sccm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810101804A CN101533772A (en) | 2008-03-12 | 2008-03-12 | Technological method for etching tungsten gate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810101804A CN101533772A (en) | 2008-03-12 | 2008-03-12 | Technological method for etching tungsten gate |
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| CN101533772A true CN101533772A (en) | 2009-09-16 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107591343A (en) * | 2016-07-06 | 2018-01-16 | 北京北方华创微电子装备有限公司 | Semiconductor technology control method, device and semiconductor manufacturing equipment |
| WO2019019939A1 (en) * | 2017-07-28 | 2019-01-31 | 北京北方华创微电子装备有限公司 | Etching method and etching system |
| CN109461767A (en) * | 2018-10-25 | 2019-03-12 | 深圳市金鑫城纸品有限公司 | A kind of super-junction structure and preparation method thereof |
| CN112331554A (en) * | 2019-08-05 | 2021-02-05 | 长鑫存储技术有限公司 | Thin film deposition method, semiconductor device manufacturing method and semiconductor device |
-
2008
- 2008-03-12 CN CN200810101804A patent/CN101533772A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107591343A (en) * | 2016-07-06 | 2018-01-16 | 北京北方华创微电子装备有限公司 | Semiconductor technology control method, device and semiconductor manufacturing equipment |
| WO2019019939A1 (en) * | 2017-07-28 | 2019-01-31 | 北京北方华创微电子装备有限公司 | Etching method and etching system |
| CN109461767A (en) * | 2018-10-25 | 2019-03-12 | 深圳市金鑫城纸品有限公司 | A kind of super-junction structure and preparation method thereof |
| CN109461767B (en) * | 2018-10-25 | 2022-03-29 | 深圳市金鑫城纸品有限公司 | Manufacturing method of super junction structure |
| CN112331554A (en) * | 2019-08-05 | 2021-02-05 | 长鑫存储技术有限公司 | Thin film deposition method, semiconductor device manufacturing method and semiconductor device |
| CN112331554B (en) * | 2019-08-05 | 2022-03-04 | 长鑫存储技术有限公司 | Thin film deposition method, semiconductor device manufacturing method and semiconductor device |
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Open date: 20090916 |