CN107017162A - The polysilicon etch of super high selectivity with high yield - Google Patents

The polysilicon etch of super high selectivity with high yield Download PDF

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Publication number
CN107017162A
CN107017162A CN201610996940.XA CN201610996940A CN107017162A CN 107017162 A CN107017162 A CN 107017162A CN 201610996940 A CN201610996940 A CN 201610996940A CN 107017162 A CN107017162 A CN 107017162A
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CN
China
Prior art keywords
chip
polysilicon
remote plasma
based material
plasma
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CN201610996940.XA
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Chinese (zh)
Inventor
杨登亮
夸梅·伊森
费萨尔·雅各布
乔恩·宏·帕克
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诺发系统公司
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Priority to US14/938,635 priority Critical
Priority to US14/938,635 priority patent/US10283615B2/en
Application filed by 诺发系统公司 filed Critical 诺发系统公司
Publication of CN107017162A publication Critical patent/CN107017162A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present invention relates to the polysilicon etch of the super high selectivity with high yield.There is provided the method and apparatus for removing the polysilicon layer on chip, wherein chip can include nitride layer, low k dielectric, oxide skin(coating) and other films.The plasma of hydrogen-based material and fluorine-based material is produced in remote plasma source, and exposes a wafer to plasma at relatively low temperatures to limit the formation of solid by-product.In some implementations, chip is maintained at the temperature below about 60 DEG C.Polysilicon layer is removed with very high etch-rate, and polysilicon is very high relative to the selection ratio of nitride layer and oxide skin(coating).In some implementations, chip is supported in the die support with multiple hot-zones, and the multiple hot-zone is configured as limiting multiple different temperatures on whole chip.

Description

The polysilicon etch of super high selectivity with high yield

Technical field

The disclosure relates generally to the etching of the polysilicon on chip, more particularly, to high selectivity on chip Polysilicon carry out the etching based on plasma.

Background technology

Etching based on plasma can be the important procedure of processing in the manufacture of semiconductor devices and integrated circuit.

Generally, wet method or dry process reaction ion(ic) etching (RIE) technique can be used to perform the removal of polysilicon.So And, the low etch-rate of polysilicon may be caused for removing the wet etching process of polysilicon, this causes low yield.This Outside, for remove the wet etching process of polysilicon may not realize it is high relative to other materials as dry method etch technology The selection ratio of material.Dry method RIE techniques using external bias at least partially due to control the complexity of ion direction and energy hard Part and cause higher cost.In addition, surrounding may be damaged by exposure to ion and photon flux using dry method RIE techniques Structure.Surrounding structure can be the side wall being made up of the nitride and/or oxide for example exposing.This surrounding structure can be wrapped Include low k dielectric, silicon nitride (Si3N4), titanium nitride (TiN) and the silica (SiO including thermal oxidation silicon2)。

Can in addition, there is natural oxidizing layer on the surface of many materials (including semiconductor wafer containing silicon and metal) The patterning of this material can be negatively affected.This can be the manufacture in semiconductor chip, storage component part or logical device In pith.For example, the natural oxidizing layer on polysilicon can substantially suppress and reduce the uniformity of polysilicon etch. When being exposed to environmental condition or oxygen containing silicon face, natural oxidizing layer can be formed.

Generally, wet processing can be used to carry out the removal of natural oxide, for example, handle nature with diluted hydrofluoric acid (HF) Oxide.However, it is probably expensive to remove natural oxide using this wet etching process, serious safety may be caused Problem, it may not be possible to realize the high selectivity relative to other materials, and may cause it is extra exposed to environmental condition with Natural oxide is allowed to be regrowed before etching polysilicon.Wet processing may also for being related to the device of high aspect ratio features It is problematic.

The content of the invention

This disclosure relates to a kind of method that polysilicon layer is removed from chip.Methods described includes:There is provided has polysilicon layer Chip;The etchant comprising hydrogen-based material and fluorine-based material is set to flow into remote plasma source, wherein the hydrogen-based material Concentration be more than the fluorine-based material concentration;Remote plasma is produced in the remote plasma source, wherein described Free radical of the remote plasma comprising the hydrogen-based material and the fluorine-based material;And by the chip exposed to described remote Journey plasma is to remove the polysilicon layer, wherein the chip is maintained within the scope of certain temperature so that the chip Substantially free of solid by-product residue during exposed to the remote plasma.

In some implementations, the chip includes the nitride and/or oxide structure of exposure.In some realization sides In case, during remove the polysilicon layer, nitride and/or oxide structure of the polysilicon relative to the exposure Select ratio greater than about 500:1.In some implementations, the hydrogen-based material includes hydrogen or ammonia, and the fluorine-based material bag Include Nitrogen trifluoride or carbon tetrafluoride.In some implementations, the temperature range is below about 60 DEG C.In some implementations In, the chip is exposed to the remote plasma in the room of the pressure with less than about 5 supports.In some implementations In, the chip is supported on the electrostatic chuck with multiple hot-zones, and the multiple hot-zone is configured as limiting entirely described Multiple different temperatures on chip.In some implementations, the etch-rate removal to be greater than about 2000 angstrom mins is described more Crystal silicon layer.In some implementations, the concentration of the fluorine-based material be between about 0.7Vol% between about 10Vol%, and And the concentration of wherein described hydrogen-based material is greater than about 50Vol%.In some implementations, the etchant also includes being different from The modified gas material of the fluorine-based material, wherein the modified gas material includes Nitrogen trifluoride, carbon tetrafluoride, fluomethane At least one of with sulfur hexafluoride.In some implementations, the chip is supported on electrostatic chuck and also included Natural oxidizing layer, and methods described also includes:To the electrostatic chuck apply biasing with the remote plasma source and The capacitance coupling plasma of at least fluorine-based chemistry is produced between the electrostatic chuck;And by the chip exposed to described Capacitance coupling plasma is to remove the natural oxidizing layer, wherein the removal of the natural oxidizing layer and the polysilicon layer Remove in situ perform.

The disclosure further relates to a kind of device for being used to remove polysilicon layer from chip.Described device includes:Plasma loses Carve room, wherein the plasma etch chamber include remote plasma source and for support chip and positioned at the long-range grade from Die support outside daughter source, wherein the chip includes oxide skin(coating) and at least one in nitride layer and polysilicon Layer.Described device also includes being configured to supply the controller for performing the instruction operated below:(a) make to include hydrogen-based material Flowed into the etchant of fluorine-based material in the remote plasma source, wherein the concentration of the hydrogen-based material is more than described fluorine-based The concentration of material;(b) remote plasma is produced in the remote plasma source, wherein the remote plasma is included The free radical of the hydrogen-based material and the fluorine-based material;And (c) by the chip exposed to the remote plasma with The polysilicon layer is removed, wherein the chip is maintained so that chip base during exposed to the remote plasma Without within the temperature range of solid by-product residue in sheet.

In some implementations, described device be additionally included in the die support and the remote plasma source it Between shower nozzle, wherein the plasma etch chamber be configured as producing in the remote plasma source inductively wait from Daughter, and wherein described plasma etch chamber is configured as producing electric capacity between the die support and the shower nozzle Coupled plasma.In some implementations, the die support includes multiple hot-zones, and the multiple hot-zone is configured as Limit multiple different temperatures on the whole chip.In some implementations, the temperature range is below about 60 DEG C.One In a little implementations, the etchant also includes the modified gas material different from the fluorine-based material, wherein the modified gas Body material includes at least one of Nitrogen trifluoride, carbon tetrafluoride, fluomethane and sulfur hexafluoride.In some implementations, The chip is included in the natural oxidizing layer on the polysilicon layer, and wherein described controller be also configured with being used for performing with The instruction of lower operation:To the substrate support apply biasing with the remote plasma source and the die support it Between produce the capacitance coupling plasma of at least fluorine-based chemistry;And the chip is exposed to the capacitiveiy coupled plasma Body is to remove the natural oxidizing layer, wherein the removal of the natural oxidizing layer and the removal original position of the polysilicon layer are performed.

Specifically, some aspects of the invention can be described below:

1. a kind of method that polysilicon layer is removed from chip, methods described includes:

Chip with polysilicon layer is provided;

The etchant comprising hydrogen-based material and fluorine-based material is set to flow into remote plasma source, wherein the hydrogen-based material is dense Concentration of the degree more than the fluorine-based material;

Remote plasma is produced in the remote plasma source, wherein the remote plasma includes the hydrogen-based thing The free radical of matter and the fluorine-based material;And

By the chip exposed to the remote plasma to remove the polysilicon layer, wherein the chip maintain so that The chip during exposed to the remote plasma substantially free of solid by-product residue within the temperature range of.

2. the method according to clause 1, wherein the chip includes the nitride and/or oxide structure of exposure.

3. the method according to clause 2, wherein the nitride structure of the exposure is included in silicon nitride and titanium nitride at least One kind, and the oxide structure of wherein described exposure at least includes thermal oxidation silicon.

4. the method according to clause 2, wherein during the polysilicon layer is removed, the polysilicon is relative to the exposure Nitride and/or oxide structure selection ratio greater than about 500:1.

5. the method according to clause 1, wherein the hydrogen-based material includes hydrogen or ammonia, and wherein described fluorine-based material includes Nitrogen trifluoride or carbon tetrafluoride.

6. the method according to any one of clause 1-5, wherein the temperature range is below about 120 DEG C.

7. the method according to clause 6, wherein the temperature range is below about 60 DEG C.

8. the method according to any one of clause 1-5, wherein the chip is sudden and violent in the room of the pressure with less than about 5 supports It is exposed to the remote plasma.

9. the method according to clause 8, wherein the chip is exposed to described remote in the room of the pressure with less than about 1 support Journey plasma.

10. the method according to any one of clause 1-5, wherein the chip is supported on the electrostatic card with multiple hot-zones On disk, the multiple hot-zone is configured as limiting multiple different temperatures on the whole chip.

11. the method according to clause 10, it also includes:

Apply multiple in the hot-zone of the electrostatic chuck during the chip is exposed into the remote plasma Different temperature is to improve the uniformity of the removal of the polysilicon layer.

12. the method according to any one of clause 1-5, wherein removing institute with the etch-rate for being greater than about 2000 angstrom mins State polysilicon layer.

13. the method according to any one of clause 1-5, wherein the concentration of the fluorine-based material is between about 0.7Vol% is between about 10Vol%, and the concentration of wherein described hydrogen-based material is greater than about 50Vol%.

14. the method according to any one of clause 1-5, wherein the etchant is also included different from the fluorine-based material Modified gas material, wherein the modified gas material is included in Nitrogen trifluoride, carbon tetrafluoride, fluomethane and sulfur hexafluoride It is at least one.

15. the method according to clause 14, wherein the concentration of the modified gas material is less than about 10Vol%.

16. the method according to any one of clause 1-5, wherein the chip is supported on electrostatic chuck and also included Natural oxidizing layer on the polysilicon layer, methods described also includes:

Apply biasing to produce at least fluorine between the remote plasma source and the electrostatic chuck to the electrostatic chuck The capacitance coupling plasma of base etchant;And

By the chip exposed to the capacitance coupling plasma to remove the natural oxidizing layer, wherein the autoxidation The removal of layer and the removal original position of the polysilicon layer are performed.

17. a kind of device for being used to remove polysilicon layer from chip, described device includes:

Plasma etch chamber, wherein the plasma etch chamber includes:

Remote plasma source;With

Die support, it is used to support chip and outside the remote plasma source, wherein the chip includes oxygen Compound layer and at least one in nitride layer and polysilicon layer;

Controller, it is configured to supply for performing the instruction operated below:

(a) etchant comprising hydrogen-based material and fluorine-based material is made to flow into the remote plasma source, wherein the hydrogen-based The concentration of material is more than the concentration of the fluorine-based material;

(b) remote plasma is produced in the remote plasma source, wherein the remote plasma includes the hydrogen The free radical of substratess matter and the fluorine-based material;And

(c) chip is exposed to the remote plasma to remove the polysilicon layer, wherein the chip is maintained So that chip temperature range substantially free of solid by-product residue during exposed to the remote plasma It is interior.

18. the device according to clause 17, it also includes:

Shower nozzle between the die support and the remote plasma source, wherein the plasma etch chamber by with Be set in the remote plasma source and produce inductively coupled plasma, and wherein described plasma etch chamber by with It is set to and produces capacitance coupling plasma between the die support and the shower nozzle.

19. the device according to clause 17, wherein the die support includes multiple hot-zones, the multiple hot-zone is configured To limit multiple different temperatures on the whole chip.

20. the device according to clause 17, wherein the nitride layer at least includes one in silicon nitride layer and titanium nitride layer It is individual, and wherein described oxide skin(coating) at least includes thermal silicon oxide layer.

21. the device according to clause 17, wherein the hydrogen-based material includes hydrogen or ammonia, and wherein described fluorine-based material bag Include Nitrogen trifluoride or carbon tetrafluoride.

22. the device according to any one of clause 17-21, wherein the temperature range is below about 60 DEG C.

23. the device according to any one of clause 17-21, wherein the pressure in the plasma etch chamber is less than About 1 support.

24. the device according to any one of clause 17-21, wherein the etchant also includes being different from the fluorine-based material Modified gas material, wherein the modified gas material include Nitrogen trifluoride, carbon tetrafluoride, fluomethane and sulfur hexafluoride in At least one.

25. the device according to any one of clause 17-21, wherein the chip is included in the nature on the polysilicon layer Oxide layer, and wherein described controller is also configured with for performing the instruction operated below:

To the substrate support apply biasing with produced between the remote plasma source and the die support to The capacitance coupling plasma of few fluorine-based chemistry;And

By the chip exposed to the capacitance coupling plasma to remove the natural oxidizing layer, wherein the autoxidation The removal of layer and the removal original position of the polysilicon layer are performed.

These and other embodiment is further described below with regard to accompanying drawing.

Brief description of the drawings

Fig. 1 shows the example with the polysilicon layer above lower coating and the structure with multiple vertical stratifications Cross section.

Fig. 2 shows the transversal of the example of the structure of autoxidation silicon layer with polysilicon layer and on the polysilicon layer Face.

Fig. 3 A show the schematic three dimensional views of the part of exemplary fin formula field effect transistor (finFET) structure.

Fig. 3 B show the zoomed-in view after etching polysilicon of Fig. 3 A example finFET structures.

Fig. 3 C show another zoomed-in view after etching polysilicon of Fig. 3 A example finFET structures.

Fig. 4 A show the cross-sectional view after etching polysilicon of the device architecture with salt residue.

Fig. 4 B show the cross-sectional view after etching polysilicon of the device architecture without salt residue.

Fig. 5 A-5C are shown for detecting ammonium hexafluorosilicate ((NH under various state of temperatures4)2SiF6) have vibration FFIR (FTIR) curve map at peak.

Fig. 6 shows the flow chart of the exemplary process for removing polysilicon from chip.

Fig. 7 shows the curve map of the functional relation of polysilicon etch speed and temperature.

Fig. 8 A show the polysilicon etch uniformity on chip for exemplary single area's electrostatic chuck.

Fig. 8 B show the polysilicon etch uniformity on chip for exemplary plural zone domain electrostatic chuck.

Fig. 9 shows the flow chart of the illustrative processes for removing natural oxide and polysilicon from chip.

Figure 10 shows the schematic diagram of the plasma processing apparatus for performing the technique that polysilicon is removed from chip.

Embodiment

Introduce

In the following description, many details are elaborated to provide the thorough understanding to being presented.Can be with Presented design is put into practice in the case of without some or all of these details.In other cases, without detailed The thin known processing operation of description, so as not to can unnecessarily make described design indigestion.Although specific reality will be combined The mode of applying describes some designs, it will be appreciated that, these embodiments are not meant as being restricted.

Etching based on plasma can be used in the manufacture of integrated circuit.For multiple technologies node, such as in 1x- In nm or 2x-nm nodes, the new material type for such as structure of memory-device stack etc can provide huge Advantage.The manufacturing process of the etching of such as certain layer etc may need to be relatively benign to this new material, at the same also with High efficiency is etched.Although realizing that the etchings of some materials (such as polysilicon) is probably in accordance with the phase to obtain high yield with high efficiency Hope, it is also possible to needing to make the minimization of loss of exposed material around avoid adversely affecting device performance.

Long-range or downstream plasma can provide acceptable etch-rate, while making the minimization of loss of adjacent material. In some implementations, for example, material may include Si3N4And/or TiN.Si3N4It may be used as sept, pad and/or lose Stop-layer is carved, and TiN may be used as metal gate structure or electrode.Long-range or downstream plasma can be provided can be minimum Change and the caused condition damaged is exposed by direct plasma, the damage includes ion impact damage, charging damage and by high energy Defect caused by the high flux of photon.

Device architecture

Fig. 1 shows the cross section of the example of the device architecture with polysilicon layer.Such as the institute of device architecture 100 in Fig. 1 Show, polysilicon layer 110 can be on underlying bed 120, and underlying bed 120 can include Si3N4.Polysilicon layer 110 can also be by multiple Vertical stratification 130 is separated, and each vertical stratification 130 can include such as TiN and/or Si3N4.In some implementations, polycrystalline Silicon layer 110 can include the polysilicon being annealed.The polysilicon of annealing can than non-annealing polysilicon more in crystalline state and more Relaxation, and can be etched with the speed different from the speed for etching unannealed polysilicon.Ordinary skill people Member will be understood that polysilicon layer 110 can be surrounded and/or separated by any amount of different materials.

In the example of fig. 1, device architecture 100 can be storage component part or logical device.The Si underlied3N4Layer 120 can For use as etching stopping layer, and TiN and Si3N4Vertical stratification 130 can be electrode.In some implementations, polycrystalline is etched Silicon layer 110, then fills TiN and Si with dielectric material3N4Space between vertical stratification 130, with TiN and Si3N4Vertical junction Capacitor is produced between structure 130.

In the example of fig. 1, the thickness of polysilicon layer 110 can be between about 1 μm and about 2 μm, such as at about 1.10 μm Between about 1.35 μm.In addition, TiN and Si3N4The thickness of vertical stratification 130 can also for example exist between about 1 μm and about 2 μm Between about 1.10 μm and about 1.35 μm.It will be appreciated by the skilled addressee that memory or logical device structure 100 can have The thickness and orientation changed.

In the example of fig. 1, the size of polysilicon and other features can depend on application and technology node.In some realities In existing scheme, the thickness for the polysilicon of removal can be about 1.3 μm, and it may correspond to 2x-nm nodes.For belonging to 2x-nm Technology node for, this may correspond to about 22nm or smaller feature (for example, grid width).In some implementations, Thickness for the polysilicon of removal can be about 1.5 μm, and it may correspond to 1x-nm node.Skill for belonging to 1x-nm nodes Art node, this can correspond to about 16nm or smaller feature (for example, grid width).

Polysilicon or any other removal containing silicon structure may be hindered due to the presence of natural oxide.Polycrystalline Silicon layer or other silicon-containing layers can be formed on autoxidation silicon layer when exposed to environmental condition or oxygen.Fig. 2 shows nature The cross section of the example of the structure of silicon oxide layer on the polysilicon layer.

In fig. 2, device architecture 200 can be similar to the device architecture 100 provided in Fig. 1 above.Polysilicon layer 210 can With by each including TiN and/or Si3N4Vertical stratification 230 separate.Polysilicon layer 210 can also be arranged on underlying bed 220 On, underlying bed 220 can include Si3N4.In some implementations, device architecture 200 can be storage component part or logic device Part, wherein underlying bed 220 are etching stopping layers, and vertical stratification 230 is electrode.Nature can be formed on polysilicon layer 210 Silicon oxide layer 240.In some implementations, can be in the Si in vertical stratification 2303N4Upper formation oxygenous layer is (for example, oxynitriding Silicon).

When oxygen and the pasc reaction at the surface containing silicon structure, autoxidation silicon layer 240 can be formed.Natural silicon oxide Layer 240 can have about(angstrom) peace treatyBetween or aboutPeace treatyBetween thickness.Due to autoxidation Silicon layer 240 is not intentional manufacture or synthesized, but is formed when under any environment comprising oxidant, therefore natural The structure of silicon oxide layer 240 can be uneven and highly unbodied.

When attempting to be chemically reacted on the material underlied, the presence of autoxidation silicon layer 240 can hinder chemical anti- Should.Specifically, autoxidation silicon layer 240 can hinder the etching of polysilicon layer 210, suppress and strengthen the inequality that polysilicon is removed Even property.This may negatively affect yield and device performance.

Desirably, autoxidation silicon layer 240 is removed before polysilicon layer 210 is removed, while causing material around Material is (such as comprising TiN and/or Si3N4Vertical stratification 230) minimization of loss.In some implementations, desirably It is to remove both autoxidation silicon layer 240 and polysilicon layer 210, also result in the minimization of loss of adjacent material.

Generally, the removal of the autoxidation silicon layer on chip is realized by wet etch process, for example, is immersed chip In bath containing dilute HF, another reative cell is then transferred into for further processing.This wet etching process may have Some shortcomings, for example, cause natural oxide in (quene) regrowth during the time of queuing up in transferring plates, relatively high gather around There is cost and utilize poisonous, dangerous and not environment friendly solvent.In addition, wet-treating may damage what is found in the devices The integrality of high-aspect-ratio structure.However, disclosed implementation as described herein can be by applying with high selectivity simultaneously The method of the autoxidation silicon layer on chip is removed using dry plasma etch process to mitigate in these shortcomings extremely It is few.In some cases, it can be lost for removing the dry plasma etch process of autoxidation silicon layer with polysilicon Carving technology original position is carried out.

Fig. 3 A show the schematic three dimensional views of the part of exemplary fin formula field effect transistor (finFET) structure. FinFET structures 300 can include semiconductor wafer 305.Semiconductor wafer 305 can include the multiple fin 305a being made up of silicon. The dielectric material 320 of such as shallow trench isolation (STI) oxide etc is formed between adjacent silicon fin 305a.Dielectric material 320 can include low dielectric oxide material, such as silica.Multiple polysilicon layers 310 can be formed in dielectric material 320 On part.In some implementations, polysilicon layer 310 can include the vertical stratification of the polysilicon perpendicular to silicon fin 305a. FinFET structures 300 can also include forming the silicon nitride liner 330 on dielectric material 320 and around polysilicon layer 310. FinFET structures 300 are additionally may included in the mask 340 in silicon nitride liner 330 and silicon fin 305a.

Fig. 3 B show the zoomed-in view after etching polysilicon of Fig. 3 A exemplary finFET structures.Fig. 3 C are shown Another zoomed-in view after etching polysilicon of Fig. 3 A exemplary finFET structures.Dry method etch technology can be selected Remove polysilicon layer 310 to property.Dry method etch technology can be to protection silicon fin 305a, dielectric material 320 and silicon nitride liner 330 Thin oxide layer (not shown) there is high selectivity.Therefore, dry method etch technology can effectively remove polysilicon, while right Protecting the thin oxide layer of silicon, silica and silicon nitride has selectivity.In Fig. 3 B and 3C, dry method etch technology removes polycrystalline Silicon layer, while silicon fin 305a, dielectric material 320 and silicon nitride liner 330 are left, without residue and defect.

Process conditions

This disclosure relates to it is a kind of with high etch rates with to the high selectivity of exposed nitride and/or oxide skin(coating) remove The method of polysilicon.This method includes providing the chip with polysilicon layer.In some implementations, chip is further included Square natural oxidizing layer, and also include at least one of nitride layer and oxide skin(coating) on the polysilicon layer.This method is also Including making the etchant comprising hydrogen-based material and fluorine-based material flow into remote plasma source, the concentration of wherein hydrogen-based material is more than The concentration of fluorine-based material.Remote plasma is produced in remote plasma source, wherein remote plasma includes hydrogen-based thing The free radical of matter and fluorine-based material.Chip is exposed to remote plasma to remove polysilicon layer, and wherein chip is maintained at certain In temperature range so that chip there is no solid by-product residue during exposed to remote plasma.At some In implementation, have greater than about under greater than about 2000 angstroms etch-rates per minute and to nitride and/or oxide skin(coating) 500:The removal of polysilicon layer is performed in the case of 1 selection ratio.

Chip can include any semiconductor wafer, the circuit being partly integrated, printed circuit board (PCB) or other appropriate works Part.Process conditions can change according to wafer size.Generally, many manufacturing facilities are arranged to 200mm chips, 300mm Or 450mm chips.Disclosed implementation as described herein is configured as operating on any suitable wafer size, for example 300mm and 450mm wafer technologies.

In some implementations, can be (such as relative by the plasma processing apparatus with remote plasma source In plasma processing apparatus or plasma reactor described by Figure 10) perform the removal of polysilicon.It is incorporated into figure The gas in plasma reactor described in 10 can be varied depending on the application.In some implementations, hydrogen-based can be used Etchant performs etching reaction.Hydrogen-based etchant can include such as hydrogen (H2).Another example can include ammonia (NH3).One In a little embodiments, H can be used2With fluorine-based material (such as Nitrogen trifluoride (NF3), carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6)) combination perform etching reaction.Such as H2And NF3Etc gas be nontoxic, it is and generally not unfavorable to environment Influence.

Polysilicon is effectively etched using hydrogen-based material as etchant while as reducing agent, so that what other exposed Material (such as TiN, Si3N4And SiO2) oxidation and minimization of loss.The oxidant of such as oxygen etc can increase the erosion of polysilicon Etching speed, but loss that is also oxidable and increasing other exposed materials.Adding fluorine-based material can as etchant and hydrogen-based material To increase the etch-rate of polysilicon, but if the concentration of fluorine-based material exceedes certain limit, it can also increase other exposure materials The loss of material.

As discussed previously herein, hydrogen-based material can include H2Or NH3, and fluorine-based material can include NF3、CF4 Or SF6.Other examples of fluorine-based material can include perfluoroethane (C2F6), fluoroform (CHF3), difluoromethane (CH2F2), fluorine Methane (CH3F), octafluoropropane (C3F8), octafluorocyclobutane (C4F8), octafluoro [1-] butane (C4F8), octafluoro [2-] butane (C4F8), octafluoroisobutene (C4F8), fluorine (F2) etc..Plasma reactor can activate hydrogen-based material and fluorine-based material to be formed Free radical, ion and other plasma activated materials.Plasma reactor can be produced comprising hydrogen-based material and fluorine-based thing The plasma of the free radical of matter.Plasma can be used for the plasma etching for performing polysilicon, the erosion of its plasma Quarter can be H2/NF3Plasma etching.

The process conditions of plasma etching can influence polysilicon and the nitride and/or the etching speed of oxide of exposure Rate.Such as relative concentration of surface temperature, pressure, source power, specific gas flow rate, gas composition, wafer size and etchant gasses Etc various technological parameters can influence process conditions, and therefore influence polysilicon and the nitride and/or oxide of exposure Etch-rate.This technological parameter can be optimized in " process window " to maximize the etch-rate of polysilicon, same to time limit Make the nitride of exposure and/or the etch-rate of oxide.

Hydrogen-based material provide will in remote plasma source ionization or free radical to form the active matter of plasma Matter.Without wishing to be bound by any theory, the etching of polysilicon can be by being added continuously to silicon atom with shape by the hydrogen atom of absorption Into Si-HxCompound and occur, the wherein number of the hydrogen atom of chemisorbed changes from x=1,2 and 3, as SiH, SiH2With SiH3.This reaction mechanism is at least in pure H2Occur in the presence of plasma.To SiH3Addition hydrogen atom promotes to form volatility Silane, i.e. SiH4, it promotes the etching of polysilicon.Below equation can describe whole Si etching reactions:Si(s)+4H*→ SiH4(g)

Other chemical reactions can promote the removal of polysilicon.Fluoro free radical can react with silicon atom, and following anti- Middle it should form volatility tetrafluorosilane (SiF4):Si(s)+4F*→SiF4(g).When hydroperoxyl radical and fluoro free radical respectively with silicon atom When reaction is to form volatile silanes and tetrafluorosilane, no solid by-product is formed.Silicon atom is removed without forming solid pair The process window of product can be referred to as " cleaning solution " (" clean regime ").

Generally, hydrogen-based material and fluorine-based material formation vapor-phase reactant, such as HF, NH are introduced in the plasma4F·HF And NH4F.These vapor-phase reactants and other plasma activated materials potentially may react to form solid pair with silicon atom Product, such as ammonium hexafluorosilicate ((NH4)2SiF6).The example of this chemical reaction can be shown in following chemistry route: Si(s)+4HF(g)+2NH4F(g)→((NH4)2SiF6)(s)+2H2(g).The technique for removing silicon atom but being related to the formation of solid by-product Window can be described as " deposition approach ".Solid by-product can distil at slightly elevated temperature, such as at greater than about 60 DEG C or high In about 75 DEG C of distillations so that polysilicon is removed and only forms gaseous by-product after polysilicon is removed.

Fig. 4 A show the cross-sectional view of the device architecture after etching polysilicon with salt residue.In etching After polysilicon (not shown), device architecture 400a is included in the groove 440 between vertical stratification 430.Vertical stratification 430 can be with Include silicon nitride and/or silica (such as thermal oxidation silicon) layer.Device architecture 400a also includes underlying bed 420, and it can be included Silicon nitride and/or silica.Etching polysilicon can occur until underlying bed 420 to form groove 440.In some implementations In, underlying bed 420 is etching stopping layer, and vertical stratification 430 is electrode.In Figure 4 A, salt residue 450 can be formed On the surface of the upper and lower volt layer 420 of side wall of vertical stratification 430.Comprising the process conditions including temperature and pressure kinetically Advantageously form salt residue 450 in Figure 4 A.Desalination residue 450 is gone to need Temperature Treatment to remove polysilicon During or after distil salt residue 450.The presence of salt residue 450 can limit output and negatively affect device performance.

Fig. 4 B, which are shown after etching polysilicon, does not have the cross-sectional view of the device architecture of salt residue.In etching After polysilicon (not shown), device architecture 400b is comprising the groove 440 without salt residue 450, vertical stratification 430 and underlies Layer 420.It can kinetically be conducive to the reaction under cleaning solution comprising the process conditions including temperature and pressure.So, Yield can distil salt residue 450 without single temperature treatment steps by etching polysilicon and improve.

As set forth above, it is possible to remove polysilicon by least one of following chemistry route:(1)Si(s)+4H*→ SiH4(g);(2)Si(s)+4F*→SiF4(g);(3) Si(s)+4HF(g)+2NH4F(g)→((NH4)2SiF6)(s)+2H2(g).First two Chemistry route avoids the formation of solid by-product or salt, and last chemistry route is related to the formation of solid by-product or salt. Process conditions, such as feed gas ratio, chamber pressure and chip temperature, can influence kinetics to be conducive to some chemistry ways Footpath rather than other chemistry routes.Kinetics can be driven by the activation energy and diffusivity of the material of wafer surface.Not by Any theoretical limitation, gaseous matter (such as NH4F diffusivity) can subject wafer temperature influence.The control of chip temperature can be with Control gaseous material (such as NH4F diffusion), so as to limit solid by-product (such as (NH4)2SiF6) formation.Therefore, suitably Process conditions can control under cleaning solution or deposition approach etch polysilicon chemistry route selection.

The process conditions of cleaning solution can occur at relatively low temperature and/or lower pressure.In some realization sides In case, the temperature of chip can be below about 120 DEG C, or below about 60 DEG C.For example, the temperature of chip can be at about 20 DEG C and about 120 Between DEG C, or between about 20 DEG C and about 50 DEG C.In some embodiments, chamber pressure is less than about 5 supports, or less than about 1 support.Example Such as, chamber pressure can be between about 0.1 support and about 5 supports.

In some implementations, under cleaning solution, can be greater than about 1000 angstrom mins, even greater than 2000 angstroms/ The removal of polysilicon occurs for the etch-rate of minute.In some implementations, chip can comprising exposure nitride and/or Oxide skin(coating), wherein exposed nitride layer can include silicon nitride, and the oxide skin(coating) of exposure can include thermal oxidation silicon. Exposed nitride and/or the etch-rate of oxide skin(coating) can be less than about 5 angstrom mins, or less than about 2 angstrom mins, or be less than About 1 angstrom min.Therefore, polysilicon can be greater than about 100 to the selection ratio of exposed nitride and/or oxide:1, or be more than About 500:1.This high selectivity can be realized when polysilicon etch speed is greater than about 2000 angstrom min.

In some implementations, wherein chip temperature can distil salt residue higher than 60 DEG C of process conditions, wherein rising Such chip temperature of magnificent salt residue can represent deposition approach.Wherein process conditions of the chip temperature less than 60 DEG C do not cause Salt is formed, wherein cleaning solution can be represented by not causing this chip temperature of salt formation.In some implementations, in cleaning side Process conditions under case can be with more than the etch-rate of 2000 angstrom mins etching polysilicon.In addition, for TEOS selection ratio 500 can be more than:1, and for Si3N4Selection ratio can be more than 100:1.Therefore, not only cleaning solution avoid it is undesirable The deposition of some solid by-products, and compared with deposition approach, cleaning solution can provide higher polycrystalline than deposition approach Silicon etch rate, and the selection ratio that is directed to oxide and nitride bigger than deposition approach offer.

Fig. 5 A-5C show the detection (NH under various state of temperatures4)2SiF6With vibration peak FTIR figure.Chemicals The detection of matter can be carried out by indicating to undergo the key of some kinds of vibration mode (such as stretch and bend).In Fig. 5 A In, to (NH4)2SiF6Detection can be by indicating in about 3300cm-1Peak at the N-H keys of experience midplane extrusion carry out. In Fig. 5 B, to (NH4)2SiF6Detection can be by indicating in about 1425cm-1Peak at experience bending (for example, shake) N-H Key is carried out.In figure 5 c, to (NH4)2SiF6Detection can be by about 717cm-1Peak indicated at Si-F keys carry out. In each FTIR figures, (NH is detected at a temperature of deposition approach4)2SiF6Presence.However, in cleaning solution, not examining Measure (NH4)2SiF6.Although the chip temperature (for example, 60 DEG C and higher) in deposition approach results in solid by-product, The chip temperature (such as 40 DEG C and lower) that will remain in cleaning solution avoids the formation of solid by-product.

Fig. 6 shows the flow chart of the illustrative processes for removing polysilicon from chip.Operation in technique 600 can be with Perform in a different order and/or with different, less or additional operation.

Technique 600 can begin at frame 605, wherein providing the chip with polysilicon layer.In some implementations, chip Can be semiconductor wafer, such as 200mm, 300mm or 450mm chip, comprising deposited one or more materials above (for example Dielectric material, conductive material or semi-conducting material) layer silicon wafer.In some implementations, chip can be memory device A part for part or logical device.Memory or logical device can comprising it is all as shown in Figure 1, Figure 2 with those shown in Fig. 3 A-3C The structure of structure etc.Chip can have polysilicon layer and at least one of nitride layer and oxide skin(coating), wherein nitrogen Compound layer can include silicon nitride or titanium nitride, and wherein oxide skin(coating) can include silica, such as thermal oxidation silicon.One In a little implementations, chip can also include various shape characteristics.Such feature can have at least about 2:1st, at least about 10: 1 or at least about 20:Aspect ratio of 1 height than lateral dimension.In some implementations, in silicon nitride and silicon oxide layer extremely Few one can be a part for these features.

Chip can be placed in the die support in plasma processing apparatus.In some implementations, it is brilliant Piece support member can be electrostatic chuck (ESC).In some implementations, electrostatic chuck can include multiple hot-zones, and it is configured To define multiple different temperatures on whole chip.Each hot-zone can be individually controllable.Multiple hot-zones can from center to Edge is radially distributed on whole electrostatic chuck.So, different chip temperatures can be applied from the center of chip to edge.

At the frame 610 of technique 600, the etchant comprising hydrogen-based material and fluorine-based material flows into remote plasma source. In some implementations, the concentration of hydrogen-based material is more than the concentration of fluorine-based material.In some implementations, hydrogen-based material bag Containing H2Or NH3.In some implementations, fluorine-based material includes NF3Or CF4.Polysilicon can generally be improved by adding fluorine-based material Etch-rate.The relative concentration of fluorine-based material can reach certain limit with relative to nitride and/or oxide skin(coating) holding Desired selectivity.In some implementations, the concentration of fluorine-based material can be, less than about 50Vol%, to be less than about 20Vol%, or between about 0.7Vol% between about 10Vol%.In some implementations, the concentration of hydrogen-based material be more than About 50Vol%, greater than about 80Vol%, or greater than about 90Vol%.

In some implementations, inert carrier gas can be introduced with etchant.Believe that inert carrier gas can be reduced in gas phase The possibility of free radical restructuring.Inert carrier gas can influence the etch-rate of polysilicon.The example of inert carrier gas can include inertia Gas, such as helium (He), neon (Ne) and argon (Ar).

Etchant can be flow in remote plasma source towards the chip in plasma processing apparatus.Plasma Body processing unit can be introduced in and chip comprising the shower nozzle for being connected to remote plasma source, etchant by shower nozzle The adjacent process chamber of support member or region.Remote plasma source and shower nozzle can be positioned above die support.It can join Examine the details that Figure 10 describes exemplary remote plasma source.

At the frame 615 of technique 600, remote plasma is produced in remote plasma source.Remote plasma can With the free radical comprising hydrogen-based material and fluorine-based material.Various materials may reside in remote plasma, for example ion, electricity Son, free radical, neutral substance, metastable state material and other materials.Remote plasma can be in the upstream of chip and process chamber Outside or adjacent with die support region is produced.

When hydrogen-based material and fluorine-based material are incorporated into remote plasma source, it can be applied to remote plasma source Plus source power.Source power can encourage induction coil to produce remote plasma, remote plasma can be it is long-range wait from Inductively coupled plasma in daughter source.Remote plasma source can produce reactive materials, and the reactive materials include The plasma activated material (for example, free radical) of hydrogen-based material and fluorine-based material.This plasma activated material can be by The dissociation of hydrogen-based material and fluorine-based material is produced.For example, the H in remote plasma2And NF3Dissociation can produce comprising F*, N*、NFx* with H* free radical.In some cases, free radical can be combined to form HF and NH in remote plasma4F Gaseous by-product.

Process conditions in remote plasma source can influence the generation of plasma.For example, such as plasma frequency The technique bar such as rate, plasma power, etchant chemicals, admixture of gas, specific gas flow rate, chamber pressure, room temperature and sequential Part can increase or reduce the density of the free radical in plasma.The device design of remote plasma source can also influence The generation of gas ions.For example, the positioning of induction coil, the length of induction coil, the shape of remote plasma source, long-range etc. from The material of the material in daughter source, the distribution in the hole in shower nozzle and shower nozzle can increase or reduce the close of free radical in plasma Degree.In some implementations, the process conditions of remote plasma source and device design can be optimized to increase plasma The density of free radical in body.The aspect of device design can promote the plasma in remote plasma source to recycle, with Further increase the density of the free radical in plasma.High density free radical in plasma may correspond to the height of polysilicon Etch-rate and the high selectivity for nitride and/or oxide.

At the frame 620 of technique 600, expose a wafer to remote plasma to remove polysilicon layer.Chip is maintained at In certain temperature range so that chip is during exposed to remote plasma substantially free of solid by-product residue.Can With by controlling the temperature of die support to control chip temperature.The ion produced in remote plasma can pass through spray Head filtering so that chip can be more exposed to the free radical of hydrogen-based material and fluorine-based material.H* free radicals and F* free radicals (that is, atomic hydrogen and atomic fluorine) can react to etch polysilicon with polysilicon layer.H* free radicals can be formed with pasc reaction The gaseous by-product of silane.F* free radicals can form the gaseous by-product of tetrafluorosilane with pasc reaction.Therefore, polysilicon layer It can not only be etched, and can be etched by atomic fluorine by atomic hydrogen.The temperature of chip may remain in suppression solid by-product Such as (NH4)2SiF6Formation temperature.In some implementations, temperature range below about 120 DEG C, below about 60 DEG C or Between about 20 DEG C to about 50 DEG C.Chamber pressure can also be controlled to suppress the formation of solid by-product.In some implementations, room Pressure can be less than about 5 supports, or less than about 1 support.Without wishing to be bound by any theory, control chip temperature or chamber pressure can limit HF And/or NH4Diffusivitys of the F at reaction surface, so as to suppress to be used to form (NH4)2SiF6Chemical reaction.Control chip temperature Degree can be with control surface reaction path.

Under certain processing conditions, for example at relatively low temperature and/or relatively low pressure, solid by-product can be suppressed The formation of thing or salt.This can be avoided or otherwise reduce the undesirable defect in chip and improve yield.It is this Process conditions can not only avoid undesired solid by-product residue, and can improve etch-rate and the increasing of polysilicon The big selectivity for nitride and/or oxide skin(coating).In some implementations, to be greater than about the etchings of 2000 angstrom mins Speed removes polysilicon layer.In some implementations, during polysilicon layer is removed, polysilicon relative to nitride and/or The selection ratio of oxide skin(coating) can be greater than about 500:1.

In some implementations, the mixing for the reactant species that the etch-rate of polysilicon may depend in etchant Thing.In addition to hydrogen-based material and fluorine-based material, etchant can also include the modification different from fluorine-based material and hydrogen-based material Gaseous matter, wherein modified gas material include NF3、CF4、CH3F and SF6At least one of.The concentration of modified gas material Less than about 10Vol%.The free radical of modified gas material can be produced, and chip can have exposed to such free radical Help remove polysilicon layer.

Fig. 7 shows the curve map of the functional relation of display polysilicon etch speed and temperature.Polysilicon etch speed with The reduction of electrostatic chuck temperature and increase, until forming salt accessory substance.Modified gas material is added to etchant in addition, working as When, the sensitivity of polysilicon etch rate against temperature is sexually revised.As shown in fig. 7, adding NF with the concentration less than 10Vol%3、CF4、 CH3F and SF6At least one of strengthen the sensitiveness of polysilicon etch rate against temperature.

Fig. 6 is returned to, in the implementation that chip is supported on the electrostatic chuck with multiple hot-zones, technique 600 is also It may be embodied in and expose a wafer to apply multiple different temperature many to improve in hot-zone during remote plasma The removal uniformity of crystal silicon layer.Multiple hot-zones can be with radial distribution so that can on chip radially distributed different temperature. It can be finely tuned from the center of chip to side by applying different temperature from the center for the electrostatic chuck for supporting chip to edge The etch-rate of the polysilicon of edge.

Fig. 8 A show the polysilicon etch uniformity on the chip for exemplary single area's electrostatic chuck.In whole electrostatic The single temperature of 100 DEG C of application on chuck, etching polysilicon scope is 73.8nm to 84.7nm.Average value is 78.7nm, 3 σ marks Quasi- deviation is 8.9nm (11.3%), and scope is 10.9nm (13.9%).

Fig. 8 B show the polysilicon etch uniformity on chip for exemplary plural zone domain electrostatic chuck.In electrostatic The center of chuck applies 110 DEG C of temperature, applies 100 DEG C of temperature in first ring at the center around electrostatic chuck, is enclosing Apply 95 DEG C of temperature in the second ring of the first ring, and at the periphery of electrostatic chuck and surround in the 3rd ring of the second ring The temperature of 100 DEG C of application.The scope of polysilicon etch is 83.9nm to 88.1nm.Average value is 86.5nm, and 3 σ standard deviations are 3.4nm (3.9%), scope is 4.2nm (4.8%).Polysilicon of the data display on whole chip shown in Fig. 8 A and 8B Etch uniformity can be by controlling the temperature on multiple hot-zones in electrostatic chuck to improve.

Fig. 6 is returned to, in the implementation that natural oxidizing layer is formed on the polysilicon layer, technique 600 can further comprise: Apply biasing to produce the electricity of at least fluorine-based chemistry between remote plasma source and die support to die support Hold coupled plasma, and expose a wafer to capacitance coupling plasma to remove removing natural oxidizing layer.In some realization sides In case, fluorine-based chemistry can include CF4.The removal of natural oxidizing layer and the removal of polysilicon layer in situ can be carried out.

The removal of polysilicon may be hindered due to the presence of natural oxide.Natural oxidizing layer (such as natural oxygen SiClx layer) when exposed to environmental condition or oxygen, it can be formed on the polysilicon layer, as shown in Figure 2.To chip to remove The exemplary corona treatment of some of natural oxide is described in documents below:On June 12nd, 2013 submit, title For " REMOVAL OF NATIVE OXIDE WITH HIGH SELECTIVITY " U.S. Patent application No.13/916,497, It is announced with United States Patent (USP) No.9,034,773 now, and in " CONTACT submit, entitled on December 19th, 2014 CLEAN IN HIGH-ASPECT RATIO STRUCTURES " U.S. Patent applications No.14/577,977, each of which passes through Reference be integrally incorporated herein and for all purposes.

In some implementations, the etchant for removing removing natural oxidizing layer can be in the etching for removing polysilicon layer Chip is flowed to before agent flowing.For going the etchant of removing natural oxidizing layer to include fluorine-based chemistry, such as CF4, or Hydrogen-based etchant and fluorine-based chemistry (such as H2And NF3) mixture.For going the etchant of removing natural oxidizing layer to set In the region between shower nozzle and die support.Biasing can be applied to die support with shower nozzle and die support Between produce capacitance coupling plasma, wherein shower nozzle can electrical ground.The capacitance coupling plasma can include fluorine based etch Ion, free radical and other plasma activated materials of agent.Autoxidation can be removed exposed to capacitance coupling plasma Layer is to perform natural oxide penetration step.Can be produced in remote plasma source after natural oxide penetration step Raw inductively coupled plasma is to remove polysilicon layer, and the wherein removal of natural oxide penetration step and polysilicon layer can be same Carried out in one plasma processing apparatus.In other words, the removal that natural oxide is penetrated with polysilicon layer in situ can occur, and make Single instrument or room need not be transferred to by obtaining chip.

Fig. 9 shows the flow chart of the exemplary process for removing natural oxide and polysilicon from chip.In technique 900 The explainable in situ example for removing natural oxide and polysilicon of operation.Operation in technique 900 can be in a different order And/or performed with different, less or additional operation.

Technique 900 may begin at frame 905, wherein chip is provided on multizone electrostatic chuck, and wherein chip has There are polysilicon layer, at least one of nitride layer and oxide skin(coating) and natural oxide on the polysilicon layer.At some In implementation, chip can be semiconductor wafer, such as 200mm, 300mm or 450mm chip, including deposit one above Or the silicon wafer of multiple material layers, the material such as dielectric (for example, low k dielectric) material, conductive material or semi-conducting material.One In a little implementations, chip can be a part for storage component part or logical device.Memory or logical device can be included All structures as shown in Figure 1, Figure 2 with those structures shown in Fig. 3 A-3C etc.In some implementations, nitride layer can be wrapped Silicon nitride comprising or titanium nitride, and oxide skin(coating) can include silica, such as thermal oxidation silicon.In some implementations, chip is also Various shape characteristics can be included.Such feature can have at least about 2:1st, at least about 10:1 or at least about 20:1 height With the aspect ratio of lateral dimension.In some implementations, at least one of nitride layer and oxide skin(coating) can be special for these The part levied.

Electrostatic chuck can include multiple hot-zones, and the plurality of hot-zone is configured as in each area providing individually controllable temperature Degree.Multiple hot-zones can be limited with radial configuration from center to edge.Hot-zone can be circular or annular.Can independently it control Heat area so that the radial temperature profile on whole chip can be applied to.The example of multizone electrostatic chuck was at 2006 11 The moon " ELECTROSTATIC CHUCK HAVING RADIAL TEMPERATURE CONTROL submit, entitled on the 22nd CAPABILITY " U.S. Patent application No.11/562, described in 884, it is incorporated herein by reference in their entirety, and is used for All purposes.Can be uniform to improve polysilicon etch by the temperature of each hot-zone in independent control multizone electrostatic chuck Property.

At the frame 910 of technique 900, CH4Towards chip flowing.Etchant can be provided to the region adjacent with chip In.In some implementations, etchant is transported in the region between die support and shower nozzle by shower nozzle.

In the frame 915 of technique 900, RF biass are applied to multizone electrostatic chuck, with shower nozzle and multizone electrostatic card CF is produced between disk4Capacitance coupling plasma.It can apply when shower nozzle is electrically grounded to multizone electrostatic chuck and bias.Should Capacitance coupling plasma can include CF4Ion, free radical and other plasma activated materials.In some implementations In, CF4Capacitance coupling plasma be CF4The in-situ plasma between shower nozzle and chip, wherein can control biasing To increase or decrease Ions Bombardment relative to produced in-situ plasma.In some implementations, biasing can be between Between about 100W and about 2000W.

In the frame 920 of technique 900, chip is exposed to capacitance coupling plasma to remove natural oxide.Exposed to electricity Natural oxide can be removed to perform natural oxide penetration step by holding coupled plasma.CF4Capacitiveiy coupled plasma Body can etch natural oxide with relatively high etch-rate, while avoiding salt formation and chemicals polymerization.In addition, electric capacity coupling The etching that plasma is closed for nitride and/or oxide skin(coating) can be selective.

In the frame 925, H of technique 9002And NF3Flow into remote plasma source, wherein H2Concentration be more than NF3Concentration. In some implementations, NF3Concentration can be less than about 50Vol%, less than about 20Vol%, or between about 0.7Vol% extremely Between about 10Vol%.In some implementations, H2Concentration be greater than about 50Vol%, greater than about 80Vol%, or greater than about 90Vol%.In some implementations, inert carrier gas can be with H2And NF3Flow together.The example of inert carrier gas can include inertia Gas, such as He, Ne and Ar.In some implementations, can be to H2And NF3Modified gas is added with the concentration less than about 10Vol% Body material (such as CF4、CH3F and SF6) to adjust the temperature sensitivity of polysilicon etch speed.

At the frame 930 of technique 900, H is produced in remote plasma source2And NF3Inductively coupled plasma, its Middle inductively coupled plasma includes hydroperoxyl radical and fluoro free radical.Various materials, example may be present in inductively coupled plasma Such as ion, electronics, free radical, neutral substance, metastable state material and other materials.Source power can encourage induction coil to produce Inductively coupled plasma.Inductively coupled plasma can be in the upstream of chip and the outside or adjacent with chip of process chamber Region is produced.

In some implementations, the process conditions and design of remote plasma source can be in inductively coupled plasmas High free base density is produced, wherein higher free base density may correspond to higher polysilicon etch speed, and increased molecule is blunt Change can cause compared with high selectivity.In some implementations, being applied to the coil voltage of the reduction of remote plasma source can subtract Few sputtering in remote plasma source and shower nozzle, so as to increase free base density.In some implementations, higher pressure Higher RF coupling efficiencies can be caused by force, so as to increase free base density.Pressure can be between about 0.1 support and 10 supports.Other Process conditions and device design aspect can increase the free base density in remote plasma source.

In the frame 935 of technique 900, chip is exposed to inductively coupled plasma to remove polysilicon layer, and wherein chip is protected Hold in the temperature less than 60 DEG C.Chip temperature can actively be controlled by multizone electrostatic chuck during corona treatment Degree.By the way that below 60 DEG C, chip temperature control can be promoted into some reaction paths, while other reaction ways can be suppressed Footpath.Specifically, reaction path Si(s)+4HF(g)+2NH4F(g)→((NH4)2SiF6)(s)+2H2(g)It is repressed simultaneously, reaction way Footpath Si(s)+4H*→SiH4(g)And Si(s)+4F*→SiF4(g)It is promoted.In some implementations, chip can be maintained between about 20 DEG C with about 50 DEG C at a temperature of between to avoid the formation of (NH4)2SiF6.The ion produced in inductively coupled plasma can To be filtered by shower nozzle so that chip can be more exposed to hydroperoxyl radical and fluoro free radical.In some implementations, can be with Control chamber pressure to form (NH to suppress4)2SiF6Reaction path.For example, chamber pressure can be less than about 5 supports, or less than about 1 support.

In some implementations, polysilicon layer is removed with the etch-rate for being greater than about 2000 angstrom mins.In some realizations In scheme, during polysilicon layer is removed, polysilicon can be greater than about relative to the selection ratio of nitride layer and/or oxide skin(coating) 500:1。

Device

Device for performing the removal of polysilicon and/or the removal of natural oxide can include corona treatment dress Put.Plasma processing apparatus can include plasma etch chamber.The above method can be in inductively coupled plasma chamber, electric capacity Performed in the combination of coupled plasma room or both.The removal of polysilicon and natural oxide can be in identical plasma Carried out in processing unit.In some implementations, plasma processing apparatus may be electrically connected to for producing inductively The source power of plasma and the bias power for producing capacitance coupling plasma.

Figure 10 shows the schematic diagram of the plasma processing apparatus for performing the technique that polysilicon is removed from chip.Deng Gas ions processing unit 1000 includes remote plasma source 1050 and the process chamber outside remote plasma source 1050 1025.Remote plasma source 1050 can be configured as producing remote plasma 1060, wherein remote plasma 1060 It can be inductively coupled plasma.The activated material 1004 of remote plasma 1060 can be from remote plasma source 1050 Introduced by shower nozzle 1054.Chip 1020 can be located in die support 1010, and wherein die support 1010 can pass through Chip 1020 is held in position in by electrostatic chuck.Other clamping devices can also be used.Chip 1020 can include all As shown in Figure 1, Figure 2 with the structure of those structures shown in Fig. 3 A-3C etc.

Processing gas 1002 can be fed to remote plasma source 1050 via gas access 1052.In some implementations In, processing gas 1002 includes hydrogen-based material (such as H2Or NH3) and fluorine-based material, such as NF3、CF4Or SF6.It is as described above its His carrier gas or modified gas material can be concomitantly introduced into processing gas 1002.Gas access 1052 can produce inductively wait from Processing gas 1002 is assigned in remote plasma source 1050 before daughter.One or more valves can control that gas will be handled Body 1002 is incorporated into remote plasma source 1050.Remote plasma source 1050 can be the container of any suitable shape, Such as cheese, cone or cylindrical shape.In some implementations, the container of remote plasma source 1050 can be shaped as Optimize plasma recirculation flow and plasma density.Gas access 1052 can be configured as towards remote plasma source 1050 side wall or the side wall distributing process gas 1002 along remote plasma source 1050.Remote plasma source 1050 Side wall, which can be included, can strengthen the material of electric field.For example, side wall can include dielectric material, for example quartz, aluminium, aluminum oxide or Ceramics.In some implementations, side wall can limit sputtering comprising ceramic coating.

Coil 1056 can surround at least a portion of the container of remote plasma source 1050.Coil 1056 can with It is electrically connected in the RF power supplys that remote plasma 1060 is produced in remote plasma source 1050.In some implementations, Coil 1056 can be around the top of container and the bottom of container.In some implementations, coil 1056 can be divided into top Portion coil 1056a and bottom coil 1056b, the region that wherein top winding 1056a compositions are powered by certain frequency, and bottom Portion coil 1056b constitutes another region powered by certain frequency.Although the plasma processing apparatus 1000 in Figure 10 shows Go out two single RF power sources for coil 1056, but plasma processing apparatus 1000 can be limited to be used for coil 1056 single RF power sources.

The arrangement of coil 1056 can influence the coupling of RF power and remote plasma 1060, to increase the close of free radical Degree.For example, the interval between the positioning of coil 1056, the length of coil 1056 and coil 1056 and container can influence RF work( Coupling between rate and remote plasma 1060.When processing gas 1002 is provided in remote plasma source 1050, and And coil 1056, when being energized, remote plasma 1060 can be energized to form the activated material of processing gas 1002 1004.Activated material 1004 can include free radical, ion and other active materials of processing gas 1002.Activated material 1004 It can be transmitted through shower nozzle 1054 towards chip 1020.In some embodiments, the activation from remote plasma 1060 Material 1004 can be used for etching the polysilicon on chip 1020 with high etch rates with high selectivity.In some embodiments In, shower nozzle 1054 can filter out the ion of activated material 1004.

In some implementations, die support 1010 can be the pedestal for supporting chip 1020, and it can be active cold But or active heating is to control the temperature of chip 1020.For example, the temperature of chip 1020 is positively retained in certain temperature range, example Such as it is below about 120 DEG C, below about 60 DEG C or between about 20 DEG C to about 50 DEG C.This can be in chip 1020 exposed to long-range etc. The formation of limitation solid by-product during gas ions 1060.

In some implementations, die support 1010 can include electrostatic chuck, and wherein electrostatic chuck can be included and is used for Apply the bias electrode of biasing to chip 1020 during etch process., can be in shower nozzle when applying biasing to chip 1020 Produce in-situ plasma 1030 between 1054 and chip 1020, wherein in-situ plasma 1030 can be Capacitance Coupled etc. from Daughter.Gas or admixture of gas 1006 can be introduced in the process chamber 1025 outside remote plasma source 1050.Gas Or admixture of gas 1006 from shower nozzle 1054 or can be coupled to one or more gas access (not shown) of process chamber 1025 and draw Enter.In some implementations, gas or admixture of gas 1006 can comprise at least fluorine-based chemistry, such as CF4.Applied Biasing can produce RF to the gas between shower nozzle 1054 and chip 1020 or admixture of gas 1006.Shower nozzle 1054 can electricity connect Ground and it can couple to encourage in-situ plasma with die support 1010.In some implementations, shower nozzle 1054 can be by Anodic oxidation.It is mixed to form gas or gas that the ionization of gas or admixture of gas 1006 can light in-situ plasma 1030 The activated material of compound 1006.In some implementations, the activated material of in-situ plasma 1030 can be used for etching chip On natural oxide 1020.

In some implementations, die support 1010 can include multiple hot-zones, and it is configured in each area and carried For can independent control temperature.Multiple hot-zones can be limited with radial configuration from center to edge.Hot-zone can be round ring Shape.Hot-zone can independently be controlled so that the radial temperature profile on whole chip 1020 can be applied to.Die support Hot-zone in 1010 can improve the uniformity of the etching on whole chip 1020.

In " METHOD FOR ACHIEVING ULTRA-HIGH submit, entitled on April 1st, 2015 Described in SELECTIVITY WHILE EETCHING SILICON NITRIDE " U.S. Patent application No.14/676,710 The details of exemplary plasma process device, is integrally incorporated herein and for all purposes by quoting.

Plasma processing apparatus 1000 can include controller 1040.Controller 1040 is a part for system, and this is System it is a part of can be plasma processing apparatus 1000 a part.Such system can be set including semiconductor processes Standby, semiconductor processing equipment includes one or more machining tools, one or more rooms, for the one or more flat of processing Platform, and/or specific processing component (die support, gas flow system etc.).These systems can be integrated with electronic device, with Just the operation of these systems is controlled before, during or after the processing of semiconductor wafer 1020.Electronic device can be referred to as " controller ", it can control the various assemblies or subdivision of one or more systems.According to processing requirement and/or the class of system Type, controller 1040 can be programmed, more any in technique disclosed in this invention to control, including control process gas Conveying, the setting (for example, heating and/or cool down) of temperature, the setting of pressure, the setting of vacuum, the setting of power, RF produce Setting, the setting of RF match circuits, the setting of frequency of device, the setting of flow rate, the setting of fluid conveying, position and operation are set Put, the turnover instrument of chip and other transfer tools and/or be connected to particular system or the load lock with particular system interface Transmission.

According to treatment conditions and/or the type of system, controller 1040 can be programmed, disclosed in this invention to control It is more any in technique, including the conveying of control process gas, the setting of temperature (for example, heating and/or cool down), pressure Setting, the setting of vacuum, the setting of power, the setting of RF generators, the setting of RF match circuits, the setting of frequency, flow rate Setting, the setting of position and operation, the turnover instrument of chip and other transfer tools and/or be connected to that setting, fluid are conveyed Particular system or the transmission with the load lock of particular system interface.Controller 1040 can be provided for realizing above-mentioned etching work The programmed instruction of skill.Programmed instruction can control various technological parameters, such as RF bias power levels, RF source power levels, many Electric current in the region of section coil, the temperature in the thermal region of multizone electrostatic chuck, chamber pressure, specific gas flow rate, gas composition Deng.For example, controller 1040 can provide the instruction for being maintained at a below chip within the temperature range of about 60 DEG C.Controller 1040 can be provided for being set up in plasma processing apparatus 1000 less than about 5 supports or between about 0.1 support between 5 supports Or the instruction of the pressure less than about 1 support.

In broad terms, controller 1040 can be defined as receiving instruction, send instruction, control operation, enable cleaning Operation, the electronic device with various integrated circuits, logic, memory, and/or software for enabling terminal measurement etc..This is integrated Circuit can include the chip that the storage program of form of firmware instructs, digital signal processor (DSP), be defined as special integrated electricity The chip on road (ASIC) and/or the one or more microprocessors or microcontroller of execute program instructions (for example, software).Program Instruction can be the instruction communicated with the controller 1040 of various single setting (or program file) forms, and the setting is defined on The operating parameter of particular procedure is carried out on semiconductor wafer or for semiconductor wafer or to system.In some embodiments, The operating parameter can be one or more (kind) layers, material, metal, the table to complete chip defined by process engineer A part for the formula of one or more of the manufacturing process in face, circuit and/or tube core process step.

In some implementations, controller 1040 can be in other words by network connection with the system integration, coupling A part for the computer of system or combinations thereof is coupled with the computer.For example, controller 1040 can be in " cloud End " or chip factory (fab) host computer system all or part of, they can allow remote access chip processing.Calculate Machine can enable the remote access to system to monitor the currently processed of manufacturing operation, check the history of past manufacturing operation, The trend or performance standard of multiple manufacturing operations are checked, changes currently processed parameter, sets process step current to follow Handle or start new technique.In some instances, remote computer (for example, server) can be carried by network to system For technical recipe, network can include local network or internet.Remote computer can include allowing input or program parameters And/or the user interface set, then these inputs or program parameters and/or setting are sent to system from remote computer. In some examples, controller 1040 receives the instruction of data mode, and these are indicated will during one or more operations The parameter of each process step performed.It should be appreciated that these parameters can be directed to the technology type and instrument that will be performed Type, controller 1040 is configured to connect or controls the tool types.Therefore, as described above, controller 1040 can be such as By being distributed including one or more discrete controllers, these discrete controllers by network connection together and court Common target (for example, technique of the present invention and control) work.The reality of distributed director for these purposes Example can be communicated with one or more remote integrated circuits (for example, in plateau levels or part as remote computer) Indoor one or more integrated circuits, they are combined to control chamber processes.

The system of example can include but is not limited to, plasma etch chamber or module, settling chamber or module, spin rinse Room or module, metal plating room or module, clean room or module, Chamfer Edge etching chamber or module, physical vapour deposition (PVD) (PVD) Room or module, chemical vapor deposition (CVD) room or module, ald (ALD) room or module, atomic layer etch (ALE) room Or module, ion implantation chamber or module, track chamber or module and can be closed in the preparation and/or manufacture of semiconductor wafer On connection or any other semiconductor processing system for using.

As described above, the one or more processing steps that will be performed according to instrument, controller 1040 can with one or Multiple other instrument circuits or module, other tool assemblies, combination tool, other tools interfaces, adjacent instrument, adjacent work Tool, the instrument in whole factory, main frame, another controller or the container of chip is being to and from semiconductor manufacturing The instrument communications used in the materials handling that tool location and/or load port in factory are carried.

Plasma processing apparatus 1000 can be configured as removing polysilicon layer from chip 1020.Chip 1020 includes many Crystal silicon layer and at least one of oxide skin(coating) and nitride layer.In some implementations, chip 1020 further comprises Natural oxidizing layer on the polysilicon layer.Plasma processing apparatus 1000 can include remote plasma source 1050 and be used for Support chip 1020 and the die support 1010 outside remote plasma source 1050.Plasma processing apparatus 1000 is also Including controller 1040, controller 1040 is configured to supply for performing the instruction operated below:(a) make to include hydrogen-based material Flowed into the etchant 1020 of fluorine-based material in the remote plasma source 1050, wherein the concentration of the hydrogen-based material is more than The concentration of the fluorine-based material;(b) remote plasma 1060 is produced in the remote plasma source 1050, wherein described Free radical 1004 of the remote plasma 1060 comprising the hydrogen-based material and the fluorine-based material;And (c) is by the chip 1020 are exposed to the remote plasma 1060 to remove the polysilicon layer, wherein the chip 1020 is maintained so that institute State the temperature model substantially free of solid by-product residue during exposed to the remote plasma 1060 of chip 1020 In enclosing.In some implementations, nitride layer includes at least one in silicon nitride layer and titanium nitride layer, and oxide skin(coating) At least include thermal silicon oxide layer.In some implementations, plasma processing apparatus 1000 is additionally included in die support Shower nozzle 1054 between 1010 and remote plasma source 1050, wherein plasma processing apparatus 1000 are configured as long-range Inductively coupled plasma 1060 is produced in plasma source 1050, and wherein plasma processing apparatus 1000 is configured as Capacitance coupling plasma 1030 is produced between die support 1010 and shower nozzle 1054.In some implementations, control Device 1040 can be further configured with for performing the instruction operated below:Application is biased to die support 1010 with long-range The capacitance coupling plasma 1030 of at least fluorine-based chemistry is produced between plasma source 1050 and die support 1010;With And be exposed to capacitance coupling plasma 1030 to go the removal of removing natural oxidizing layer, wherein native oxide layer by chip 1020 Removal original position with polysilicon layer is performed.

Lithographic patterning

Above-mentioned various apparatus and method can be used in combination with lithographic patterning instrument and/or technique, for example with manufacture or Prepare semiconductor devices, display, LED, photovoltaic panel etc..Generally, although being not required, by common manufacturing facility together And/or simultaneously using such instrument or carry out such technique.The lithographic patterning of film is generally included in following steps Some or all, each operation can use a variety of feasible instruments:(1) photoresist is applied using spin coating or Spray painting tool Overlay on workpiece, i.e., on substrate;(2) using hot plate or stove or UV tools of solidifying solidification photoresist;(3) such as chip is used Photoresist is exposed to visible ray or UV or X-ray by the instrument of step-by-step exposure machine etc;(4) make resist development so as to Resist is optionally removed using the instrument of such as wet type platform etc, so that it is patterned;(5) by using dry type or wait The lithography tool of gas ions assist type transfers resist patterns into underlie film or workpiece;And (6) use such as RF or microwave The instrument of plasma resist stripper etc removes resist.

Other embodiment

Although it is shown and described herein that illustrated embodiment and the application of the present invention, are held in the structure of the present invention It is feasible that many in think of, scope and spirit, which changes and modifications scheme, and these change programmes are for the common of this area Technical staff will become obvious after the application is read.Therefore, these embodiments be considered as it is illustrative rather than It is restricted, and the invention is not restricted to details given herein, but can scope of the following claims and etc. Tongfang Modified in case.

Claims (10)

1. a kind of method that polysilicon layer is removed from chip, methods described includes:
Chip with polysilicon layer is provided;
The etchant comprising hydrogen-based material and fluorine-based material is set to flow into remote plasma source, wherein the hydrogen-based material is dense Concentration of the degree more than the fluorine-based material;
Remote plasma is produced in the remote plasma source, wherein the remote plasma includes the hydrogen-based thing The free radical of matter and the fluorine-based material;And
By the chip exposed to the remote plasma to remove the polysilicon layer, wherein the chip maintain so that The chip during exposed to the remote plasma substantially free of solid by-product residue within the temperature range of.
2. according to the method described in claim 1, wherein the chip includes the nitride and/or oxide structure of exposure.
3. method according to claim 2, wherein the nitride structure of the exposure is included in silicon nitride and titanium nitride At least one, and the oxide structure of wherein described exposure at least includes thermal oxidation silicon.
4. method according to claim 2, wherein during the polysilicon layer is removed, the polysilicon is relative to described The selection ratio greater than about 500 of exposed nitride and/or oxide structure:1.
5. according to the method described in claim 1, wherein the hydrogen-based material includes hydrogen or ammonia, and wherein described fluorine-based material Including Nitrogen trifluoride or carbon tetrafluoride.
6. the method according to any one of claim 1-5, wherein the temperature range is below about 120 DEG C.
7. method according to claim 6, wherein the temperature range is below about 60 DEG C.
8. the method according to any one of claim 1-5, wherein the chip is in the room of the pressure with less than about 5 supports In be exposed to the remote plasma.
9. method according to claim 8, wherein the chip is exposed to institute in the room of the pressure with less than about 1 support State remote plasma.
10. the method according to any one of claim 1-5, wherein the chip is supported on the quiet of multiple hot-zones On electric card disk, the multiple hot-zone is configured as limiting multiple different temperatures on the whole chip.
CN201610996940.XA 2012-07-02 2016-11-11 The polysilicon etch of super high selectivity with high yield CN107017162A (en)

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KR20190097560A (en) 2018-02-12 2019-08-21 한국기계연구원 Atomic layer etching method for Si
US20200098586A1 (en) * 2018-09-21 2020-03-26 Applied Materials, Inc. Selective material removal

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