JP5176902B2 - Electronic device manufacturing method and setting apparatus - Google Patents

Description

  The present invention relates to a method for manufacturing an electronic device typified by a semiconductor device by processing an object to be processed by lithography and etching, and a setting device for setting etching conditions at the time of processing.

With the miniaturization and high integration of semiconductor devices, there is an increasing demand for dimensional accuracy in functional elements. In particular, the processing accuracy at the time of forming the gate electrode of the MOS transistor is required to be higher because it directly affects the variation in transistor characteristics.
In pattern formation at the time of LSI manufacture, a resist pattern is generally formed by lithography, and the object to be processed is processed by etching using the resist pattern as a mask. In order to obtain higher processing dimensional accuracy, the dimension of a resist pattern formed by lithography is measured, and a difference value between the actually measured dimension and a predetermined desired dimension (target dimension) is obtained. Etching conditions are adjusted so as to shorten. By adjusting the etching conditions, the dimensional variation after etching can be reduced. For example, Patent Document 1 discloses a technique for adjusting the recipe of an etching process after measuring the dimension of a resist pattern and stabilizing the dimension after etching.

JP 2005-109514 A

  In order to use the element dimension adjustment method by changing the conditions during etching, it is desirable that the difference between the dimension of the resist mask and the dimension of the object to be processed after etching is constant depending on the etching conditions. Factors cause this difference to vary. The fluctuation due to the state change of the etching apparatus during etching can be predicted by the state management of the etching apparatus for a sudden change, and the slow change can be corrected by the change management of the dimensional change.

  A problem in achieving higher dimensional accuracy is dimensional variation due to a change in the shape of the resist pattern. Even if the etching process is performed under the same conditions, if the resist shape varies, there may be no correlation between the resist dimensions and the element dimensions after etching. In this case, it becomes impossible to estimate the dimension of the object to be processed after etching from the measurement result of the dimension of the resist pattern, and the etching conditions cannot be substantially adjusted as in Patent Document 1. As described above, when the etching conditions are adjusted based only on the dimensions of the resist pattern, the dimensional variation increases, and the original processing accuracy cannot be improved.

  The present invention has been made in view of the above-described problems, and achieves extremely high dimensional accuracy of an object to be processed by lithography and etching even when electronic devices are further miniaturized and highly integrated, and has high reliability. An object of the present invention is to provide an electronic device manufacturing method and a setting apparatus that can realize a high electronic device.

One aspect of a method for manufacturing an electronic device includes a step of exposing a resist film formed on a workpiece to form a resist pattern, and etching the workpiece under predetermined etching conditions using the resist pattern as a mask. And measuring the width dimension , film thickness, and taper angle of the formed resist pattern , and measuring the width dimension , film thickness, and taper angle of the resist pattern, When the process of predicting the substantial width dimension of the resist pattern and the step of etching are executed, a desired width dimension of the resist pattern for calculating the etched width dimension of the object to be processed is calculated. A step of calculating a first difference value between the desired width dimension and the substantial width dimension of the resist pattern; Width of the processed object when ring to process is implemented, and a step of adjusting the etching condition based on the difference value such that the aimed width.

One aspect of the setting apparatus is an apparatus for setting etching conditions when etching the object to be processed using a mixed gas containing an etching gas using a resist pattern formed on the object to be processed as a mask. A dimension predicting unit for predicting a substantial width dimension of the resist pattern adjusted by the parameters for setting the target dimension to be processed using the width dimension , film thickness, and taper angle of the resist pattern as parameters; A difference value calculation unit for calculating a difference value between a desired width dimension of the resist pattern and the substantial width dimension, and based on the difference value, the width dimension of the object to be processed after etching becomes a target width dimension. And a condition adjusting unit for adjusting the etching conditions, and a desired width dimension of the resist pattern is a width dimension of the etched object to be processed. There is a width of the resist pattern when the aim width.

  According to each aspect described above, even when the electronic device is further miniaturized and highly integrated, extremely high dimensional accuracy of the workpiece is achieved by lithography and etching, and a highly reliable electronic device is realized.

―Basic outline of this embodiment―
Hereinafter, the basic outline of the present embodiment will be described. Here, a case where a gate electrode having a desired width dimension (target width dimension) of 40 nm is illustrated.

A polycrystalline silicon film is formed as a gate material to be processed on the silicon semiconductor substrate in which the element isolation and the formation of the gate insulating film have been completed, and a resist pattern is formed on the polycrystalline silicon film by lithography.
Subsequently, the polycrystalline silicon film is dry etched using the resist pattern as a mask. Here, under standard etching conditions, the width dimension of the gate electrode after etching is formed to be narrower by about 15 nm than the dimension of the resist pattern. In this example, since the target dimension of the gate electrode is 40 nm, the target dimension of the resist mask is about 55 nm obtained by adding 15 nm to the target width dimension of 40 nm of the gate electrode. Although a resist pattern is formed with this target dimension, dimensional variations occur in the formed resist pattern due to various fluctuations during lithography.

  When a resist pattern was actually formed with the above target dimensions, a resist pattern whose width dimension varied within a range of about 52 nm to 54 nm was obtained. FIG. 1 shows the result of examining the relationship between the width dimension of the formed gate electrode and the dimension of the resist mask by dry etching the polycrystalline silicon film using this resist pattern. It is considered that the relationship between the width dimension of the gate electrode and the dimension of the resist mask is ideally a straight line having a slope of 1 with the change of the width dimension caused by etching of the gate electrode being −15 nm. However, in the example of FIG. 1, no such correlation was found.

  In the present embodiment, the shape of the resist pattern is considered in addition to the dimension of the resist pattern as a parameter for adjusting the etching conditions. As the shape of the resist pattern, the film thickness (height) and taper angle of the resist pattern are suitable. Instead of the taper angle, a difference value between the upper end width and the lower end width of the resist pattern may be used. If the vertical cross section of the resist pattern is a trapezoid (or a shape that can be regarded as a substantially trapezoid), the difference value between the upper end width and the lower end width of the resist pattern is substantially the same if the film thickness of the resist pattern is constant. Is equivalent to the taper angle.

FIG. 2 shows the result of examining the relationship between the taper angle and the width dimension of the gate electrode for the resist pattern of FIG. From this result, it can be seen that the width dimension of the gate electrode changes in a relationship close to 1 / tan θ when the taper angle of the resist pattern is θ.
In order to predict the width dimension of the gate electrode after etching, the following model formula is adopted in this embodiment.
Resist pattern substantial dimension = resist pattern dimension + a × resist pattern film thickness / tan θ (1)
In equation (1), a is a coefficient and θ is the taper angle of the resist pattern. The coefficient a is a value that varies depending on the resist pattern size, etching conditions, and the like, and can be treated as a constant only in the case of the same lithography and etching process. Measured values are used for the resist pattern dimensions, film thickness, and taper angle.

  FIG. 3 shows the results of examining the relationship between the substantial dimension of the resist pattern and the width dimension of the gate electrode after etching when the coefficient a in the equation (1) is set to 0.437, for example, for the resist pattern of FIG. . In FIG. 3, it is confirmed that the relationship between the substantial dimension of the resist pattern and the width dimension of the gate electrode after etching shows a strong correlation with a straight line having a slope of 1 with an intercept of −15 nm. That is, the amount of dimensional change during etching can be accurately predicted based on the size, film thickness, and taper angle of the resist pattern. In this embodiment, when measuring the resist mask dimensions, in addition to the resist mask dimensions, the resist mask film thickness and taper angle are measured, and the resist mask dimensions, film thickness and taper angle are determined as etching conditions. It is a parameter for adjustment. By using these parameters and optimizing the etching conditions, it is possible to accurately process the object to be processed into a desired dimension.

―Specific Embodiment―
Hereinafter, specific embodiments will be described in detail with reference to the drawings based on the above basic outline. In this embodiment, the case where a MOS transistor is formed as a functional element is illustrated. This case can also be applied to a semiconductor device provided with other functional elements (semiconductor memory element or various capacitors). Further, the present invention can also be applied to electronic devices such as FPD (Flat Panel Display), MEMS (Micro-Electro-Mechanical Systems), and magnetic heads other than semiconductor devices.

FIG. 4 is a schematic sectional view showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.
First, as shown in FIG. 4A, an element isolation structure 11 is formed on a silicon semiconductor substrate 10.
Specifically, the element isolation structure 11 is formed on the surface layer of the silicon semiconductor substrate 10 by, for example, STI (Shallow Trench Isolation) method, and the element active region is defined on the semiconductor substrate 10.

Subsequently, as shown in FIG. 4B, a gate electrode 13 is formed on the semiconductor substrate 10 with a gate insulating film 12 interposed therebetween.
Specifically, after a thin gate insulating film 12 is formed in the element active region of the semiconductor substrate 10 by a thermal oxidation method or the like, for example, a polycrystalline silicon film is deposited on the gate insulating film 12 by a CVD method or the like. Then, the polycrystalline silicon film and the gate insulating film 12 are processed into electrode shapes by lithography and dry etching. Thus, the gate electrode 13 made of a polycrystalline silicon film is formed on the gate insulating film 13.

Subsequently, as shown in FIG. 4C, the extension region 14 is formed.
Specifically, using the gate electrode 13 as a mask, impurities are ion-implanted into the element active region with a predetermined dose and acceleration energy to form a pair of extension regions 14. As an impurity to be ion-implanted, a P-type impurity such as boron (B ⁺ ) is used when a PMOS transistor is manufactured, and an N-type such as phosphorus (P ⁺ ) or arsenic (As ⁺ ) is used when an NMOS transistor is manufactured. Impurities are used.

Subsequently, as shown in FIG. 4D, sidewall insulating films 15 and source / drain regions 16 are sequentially formed.
More specifically, first, for example, a silicon oxide film is deposited on the entire surface by a CVD method or the like, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surface of the gate electrode 13 and the sidewall insulating film 15. Form.
Next, using the gate electrode 13 and the sidewall insulating film 15 as a mask, an impurity is ion-implanted into the element active region under the condition that it is deeper than the extension region 14 to form a pair of source / drain regions 16. As an impurity to be ion-implanted, a P-type impurity such as boron (B ⁺ ) is used when a PMOS transistor is manufactured, and an N-type such as phosphorus (P ⁺ ) or arsenic (As ⁺ ) is used when an NMOS transistor is manufactured. Impurities are used.
Thus, a MOS transistor having the gate electrode 13, the extension region 14, and the source / drain region 16 is formed.

Subsequently, as shown in FIG. 4E, an interlayer insulating film 17 and contact plugs 18 electrically connected to the source / drain regions 18 in the interlayer insulating film 17 are sequentially formed.
Specifically, first, for example, a silicon oxide film is deposited by CVD or the like so as to cover the MOS transistor, and an interlayer insulating film 17 is formed.
Next, the interlayer insulating film 17 is processed by lithography and subsequent dry etching so that a part of the surface of the source / drain region 16 is exposed, and a contact hole 18 a is formed in the interlayer insulating film 17.

Next, Ti, TiN, a laminated film of Ti and TiN, or the like is deposited on the interlayer insulating film 17 by a sputtering method or the like so as to cover the inner wall surface of the contact hole 18a, thereby forming a base film 18b.
Next, a conductive material, for example, tungsten (W) is deposited on the interlayer insulating film 17 by a CVD method or the like so that the contact hole 18a is embedded via the base film 18b. Then, W and the base film 18b are polished by a chemical-mechanical polishing (CMP) method until the surface of the interlayer insulating film 17 is exposed, and the contact hole 18a is filled with W through the base film 18b. Contact plug 18 is formed.

Subsequently, as shown in FIG. 4F, a wiring 19 electrically connected to the contact plug 18 is formed.
Specifically, first, a base material such as Ti, TiN, or a laminated film of Ti and TiN is deposited on the interlayer insulating film 17 including the contact plug 23 by sputtering or the like.
Next, a wiring material such as aluminum (Al) or an Al alloy is formed on the base material by sputtering or the like.
Then, the wiring material and the base material are processed into an electrode shape by lithography and dry etching so as to be electrically connected to the contact plug 18, and the wiring 19 electrically connected to the contact plug 18 through the base film 19a. Form.
Thereafter, a further interlayer insulating film, an upper layer wiring and the like are formed to form a semiconductor device.

In the present embodiment, when the gate electrode 13 is formed in FIG. 4B, the method described in the basic outline is applied.
FIG. 5 is a flowchart showing the steps of lithography and dry etching according to the present embodiment. FIG. 6 is a block diagram showing a schematic configuration of the etching condition setting apparatus according to the present embodiment. FIG. 7 is a schematic plan view for explaining a method for measuring a film thickness and a taper angle of a resist pattern. FIG. 8 is a schematic sectional view showing the process of FIG. 4B in more detail.

  As shown in FIG. 6, the etching condition setting apparatus according to the present embodiment includes a size prediction unit 41, a difference value calculation unit 42, an adjustment value calculation unit 43, a storage unit 44, a condition adjustment unit 45, a flow rate calculation unit 46, The flow rate ratio calculation unit 47, the dimensional change calculation unit 48, the standard condition conversion unit 49, and the correction value calculation unit 50 are configured.

The dimension predicting unit 41 predicts the substantial dimension of the resist pattern corresponding to the desired dimension of the object to be processed based on the dimension and shape of the resist pattern (the shape is the film thickness and taper angle of the resist pattern). The substantial dimension of the resist pattern is calculated based on, for example, the above equation (1).
The difference value calculation unit 42 calculates a difference value between a desired dimension (target dimension) of the resist pattern and a substantial dimension of the resist pattern.
The adjustment value calculation unit 43 calculates an adjustment value obtained by adding a correction value for a dimensional change amount based on the actually measured dimension of another etched object to be processed to the difference value calculated by the difference value calculation unit 42.
Adjustment value = (difference value between the target dimension of the resist pattern and the actual dimension of the resist pattern) + (correction value of the dimensional change based on the actual measured dimension of the other etched object)

The storage unit 44 stores the resist pattern actual dimension calculated by the dimension predicting unit 41 and the correction value calculated by the correction value calculating unit 50.
The condition adjustment unit 45 adjusts the etching condition of the processing target based on the adjustment value calculated by the adjustment value calculation unit 43.

Based on the substantial dimension of the resist pattern calculated by the dimension predicting unit 41, the flow rate ratio calculating unit 46 calculates a flow rate ratio of a predetermined gas among the mixed gas that is an etching gas.
The flow rate calculation unit 47 calculates the flow rate of each gas constituting the etching gas based on the flow rate ratio of the predetermined gas calculated by the flow rate ratio calculation unit 46.

The dimension change amount calculation unit 48 calculates a difference value between the actually measured dimension of the etched object to be processed and the actual dimension of the resist pattern calculated by the dimension prediction unit 41 as the dimension change amount.
The standard condition conversion unit 49 uses a difference value between the dimensional change amount calculated by the dimensional change amount calculation unit 48 and the adjustment value calculated by the adjustment value calculation unit 43 as a dimensional change amount (standard change amount) based on the standard conditions. calculate.
The correction value calculation unit 50 calculates the average value of the standard change amounts for several lots of the semiconductor substrates that have already been calculated, and the difference between the change amount of the resist pattern dimension relative to the target width dimension to be processed and the average value The value is calculated as a correction value.
Correction value = (Change amount of resist pattern dimension relative to target width dimension of gate electrode) − (Average value of standard change amount)
The calculated correction value is stored in the storage unit 44 and used for calculation of the adjustment value by the adjustment value calculation unit 43.

When forming the gate electrode 13, first, as shown in FIG. 8A, a polycrystalline silicon film 21 and a resist film 22 are formed.
Specifically, a polycrystalline silicon film to be processed is deposited on the gate insulating film 12 by a CVD method or the like. Then, a predetermined resist is applied on the polycrystalline silicon film 21 to form a resist film 22.

Subsequently, as shown in FIG. 8B, a resist pattern 23 is formed (step S1 in FIG. 5).
More specifically, the resist film 22 is exposed and patterned by lithography to form an electrode-shaped resist pattern 23.

  Subsequently, the width dimension, film thickness, and taper angle of the resist pattern 23 are measured (step S2 in FIG. 5). Here, as shown in FIG. 10A, the width dimension and the taper angle are measured in the resist pattern 23 having a trapezoidal longitudinal section, with the width MCD at the center portion being the width dimension and the base angle of the trapezoid being the taper angle. Measure as

As a method for measuring the width dimension, film thickness, and taper angle of the resist pattern 23, for example, OCD measurement using a spectroscopic ellipsometry method is employed.
By analyzing the spectrum after reflection of light incident from a direction perpendicular to the periodically arranged resist patterns, it is possible to measure the width dimension, film thickness, and taper angle of the resist pattern at once. . However, for that purpose, it is necessary to perform measurement by fitting with a library of spectral data formed in advance from a model. At this time, when there are multiple measurement targets, it is necessary that the spectrum change due to the variation of each parameter is unique. However, when the measurement target is a resist pattern, the spectrum changes depending on the film thickness and taper angle, etc. May occur. In this case, although the thickness of the resist pattern actually fluctuates, the taper angle may be measured in some cases, which causes a reduction in measurement accuracy.
In order to solve this problem, in this embodiment, a film thickness measurement pattern having a certain area is arranged in the vicinity of the resist pattern, and first, after measuring the film thickness of the film thickness measurement pattern. Then, the spectrum of the resist pattern dimension measurement pattern is measured.

  Specifically, first, as shown in FIG. 7A, a film thickness measurement pattern 31 formed in the scribe region of the semiconductor substrate 10 and being a part of the polycrystalline silicon film 21 deposited as a gate material is used. . The spectrum of the reflected light reflected by the film thickness measurement pattern 31 is measured for the incident light, and the film thickness of the film thickness measurement pattern 31 (that is, the polycrystalline silicon film 21) is measured.

  Next, as shown in FIG. 7B, a film thickness measurement pattern 32 that is a part of the resist film 22 formed on the film thickness measurement pattern 31 is used. The spectrum of the reflected light reflected by the film thickness measurement patterns 31 and 32 is measured for the incident light, and the film thickness of the film thickness measurement pattern 31 + the film thickness measurement pattern 32 (that is, the polycrystalline silicon film 21 + the resist film 22) is determined. taking measurement. Here, the measured value of the film thickness of the film thickness measurement pattern 31 is given as a constant. Thereby, the measurement accuracy of the film thickness of the film thickness measurement pattern 32 can be improved. The film thickness of the measured film thickness measurement pattern 32 is regarded as the film thickness of the resist pattern 23.

Then, as shown in FIG. 7C, a dimension measurement pattern of the resist pattern 23, which is a part of the resist film 22 and formed together with the film thickness measurement pattern 32, here for OCD (Optical Critical Dimension) measurement. Pattern 33 is used. The spectrum of the reflected light reflected by the OCD measurement pattern 33 is measured for the incident light, and the width dimension and taper angle of the OCD measurement pattern 33 are measured. The measured width dimension and taper angle of the OCD measurement pattern 33 are regarded as the width dimension and taper angle of the resist pattern 23. Here, the measurement values of the film thickness measurement patterns 31 and 32 are given as constants, and only the width dimension and taper angle of the OCD measurement pattern 33 are calculated by fitting. Thereby, the measurement accuracy of the width dimension and the taper angle of the OCD measurement pattern 33 can be improved.

Subsequently, the substantial dimension of the resist pattern 23 is predicted (step S3 in FIG. 5).
Specifically, the dimension predicting unit 41 determines the gate electrode 13 based on the measured width dimension, film thickness, and taper angle of the resist pattern 23 (the film thickness measurement pattern 32 and the OPC correction OCD measurement pattern 33). The substantial dimension of the resist pattern 23 corresponding to the desired width dimension is calculated. The substantial dimension of the resist pattern 23 is calculated based on, for example, the above equation (1).

Subsequently, the difference value calculation unit 42 calculates a difference value between the desired width dimension (target width dimension) of the resist pattern 23 and the actual dimension of the resist pattern (step S4 in FIG. 5).
Subsequently, the adjustment value calculation unit 43 adds the correction value of the dimensional change amount based on the actually measured dimension of the other gate electrode 13 already formed to the difference value calculated by the difference value calculation unit 42 (difference). Value + correction value) (step S5 in FIG. 5). The correction value is stored in the storage unit 44.
The dimension of the object to be processed may change depending on the change in the condition of the etching apparatus or the like. As will be described later, this amount of change can be adjusted by a correction value obtained by measuring the dimension of the object to be processed after etching each time the etching process is performed, and using the actually measured dimension.

Subsequently, the flow rate calculation unit 46 calculates a flow rate ratio of a predetermined gas, that is, SO ₂ in the mixed gas, which is an etching gas, based on the substantial dimension of the resist pattern 23 calculated by the dimension prediction unit 41. (Step S6 in FIG. 5).
Subsequently, the flow rate calculation unit 47 calculates the flow rate of each gas constituting the etching gas based on the SO ₂ flow rate ratio calculated by the flow rate ratio calculation unit 46 (step S7 in FIG. 5).

Hereinafter, steps S6 and S7 will be described in detail.
When the gate electrode is formed with a width narrower than that of the resist pattern, the width of the resist pattern is reduced during etching. By adjusting the reduction amount of the width dimension of the resist pattern, it is possible to adjust the difference between the width dimension of the resist pattern and the width dimension of the gate electrode after etching.
As a specific method for adjusting the difference, there are a method of adjusting the processing time of the processing for reducing the width dimension of the resist pattern during the etching processing, a method of changing the etching gas conditions used for this processing, and the like. In the present embodiment, a method for changing the etching gas condition is exemplified.

  In this embodiment, for example, an etching apparatus provided with an ICP plasma source is used. The semiconductor substrate 10 is transferred into the etching chamber and fixed to the electrostatic chuck, and the temperature of the electrostatic chuck (chuck temperature) is adjusted to control the temperature of the semiconductor substrate. The dimensional change amount of the workpiece can be adjusted by controlling the chuck temperature, and the chuck temperature can be adjusted according to the situation. In this embodiment, the case where the chuck temperature is 20 ° C. is illustrated.

In this embodiment, an antireflection film (BARC) (not shown) is formed under the resist pattern 23, and the width of the resist pattern is reduced during the BARC etching performed together with the polycrystalline silicon film 21. As an etching gas at the time of this reduction process, for example, a mixed gas containing He, O ₂ and SO ₂ is used. The reduction amount of the width dimension of the resist pattern can be adjusted by adjusting the flow rate of each gas to 60 sccm, the total gas flow rate of O ₂ , and SO ₂ to 30 sccm, and adjusting the flow rate ratio of each gas.

The pressure of the etching gas is automatically adjusted by a conductance valve and is maintained at 5 mTorr, for example. RF power with ICP power adjusted to 330 W and bias power adjusted to 100 V is introduced into the etching chamber. The etching state of BARC is determined by analyzing the light emission state of plasma. The end point of the BARC etching is detected by, for example, an EPD (End Point Detector), and overetching of, for example, about 30% is performed from the time when the etching end point is detected. Thus, it is possible to adjust the amount of reduction of the width of the resist pattern by controlling SO ₂ flow rate ratio (SO ₂ flow rate / (SO ₂ flow rate + O ₂ flow rate)).
FIG. 6 shows the results of examining the relationship between the value of the SO ₂ flow rate ratio (SO ₂ flow rate ratio × 100 in%) and the width size of the gate electrode 13 when the target width size of the resist pattern 23 is 55 nm. 9 shows. It can be seen that a substantially linear control of the width dimension of the gate electrode 13 is possible by changing the SO ₂ flow rate ratio.

Etching conditions when the SO ₂ flow rate is 6 sccm, the O ₂ flow rate is 24 sccm, and the SO ₂ flow rate ratio is 20% are the etching standard conditions. Etching BARC under this etching standard condition means that the etching is performed with a target width of 40 nm as the target width of the gate electrode.

The flow rate ratio calculation unit 46 calculates the SO ₂ flow rate ratio during the BARC etching based on the etching standard conditions. For example, it is assumed that the adjustment value (difference value + correction value) calculated by the adjustment value calculation unit 43 is 2 nm. In this case, as the etching conditions, it is necessary to select an etching condition in which the width dimension of the gate electrode is formed wider by 2 nm than in the case of the etching standard condition. From FIG. 9, it can be seen that by increasing the SO ₂ flow rate ratio by 1%, the width dimension of the gate electrode is formed wider by about 1.07 nm. Accordingly, the flow rate calculation unit 46 calculates the SO ₂ flow rate ratio in this case as follows.
SO ₂ flow rate ratio = SO ₂ flow rate ratio of etching standard conditions (20%) + adjusted value (2 nm) /1.07
≒ 21.87%

Subsequently, the flow rate calculation unit 47, based on the SO ₂ flow rate ratio calculated, calculates the SO ₂ flow rate and O ₂ flow rate as follows.
SO ₂ flow rate = SO ₂ flow rate ratio × total flow rate under standard etching conditions (SO ₂ flow rate + O ₂ flow rate: 30 sccm) / 100
≒ 6.6sccm
O ₂ flow rate = total flow rate under standard etching conditions (30 sccm) −SO ₂ flow rate (6.6 sccm)
≒ 23.4sccm
By determining the etching conditions as described above, the width dimension of the gate electrode 13 can be made as close as possible to the target width dimension.

  As described above, after performing Steps S6 and S7, the BARC and the polycrystalline silicon film 21 are dry-etched using the resist pattern 23 as a mask under the above etching conditions as shown in FIG. 8C (FIG. 5). Step S8). Then, by removing the resist pattern 23 by ashing or the like, the gate electrode 13 shown in FIG. 4B is formed.

In the present embodiment, after the gate electrode 13 is formed, a correction value used when the gate electrode 13 is subsequently formed is calculated.
First, the width dimension of the formed gate electrode 13 is measured (step S9 in FIG. 5). A specific example of the width dimension of the gate electrode 13 is shown as a width dimension gw in FIG.
Subsequently, the dimensional change calculation unit 48 calculates a difference value between the measured width dimension (actual measurement dimension) of the gate electrode 13 and the actual dimension of the resist pattern 23 calculated by the dimension prediction unit 41 as a dimensional change amount. (Step S10 in FIG. 5).

Subsequently, the standard condition conversion unit 49 calculates a difference value between the dimensional change amount calculated by the dimensional change amount calculation unit 48 and the adjustment value calculated by the adjustment value calculation unit 43 as a standard change amount (FIG. 5). Step S11).
Subsequently, the correction value calculation unit 50 calculates the average value of the standard change amounts for the last several lots of the already calculated semiconductor substrate, including the standard change amount calculated in step S <b> 11, and aims for the gate electrode 13. A difference value between the amount of change in the width dimension of the resist pattern 23 with respect to the width dimension (here, 15 nm) and the above average value is calculated as a correction value (step S12 in FIG. 5). The calculated correction value is stored in the storage unit 44 and is used for calculation of the adjustment value by the adjustment value calculation unit 43 in the next step S5.

  In this way, by correcting the adjustment amount of the etching condition using the short-term average value of the standard change amount, the width dimension of the gate electrode 13 with less variation and extremely close to the target width dimension can be obtained. .

  As described above, according to the present embodiment, even if the semiconductor device is further miniaturized and highly integrated, the dimensional accuracy of the object to be processed is achieved by lithography and etching, and the semiconductor device has high reliability. Is realized.

-Other embodiments-
Each component of the etching condition setting apparatus according to the present embodiment described above (dimension prediction unit 41, difference value calculation unit 42, adjustment value calculation unit 43, condition adjustment unit 45, flow rate calculation unit 46, flow rate calculation of FIG. The functions of the unit 47, the dimensional change calculation unit 48, the standard condition conversion unit 49, the correction value calculation unit 50, etc.) can be realized by operating programs stored in a RAM, a ROM, etc. of the computer. Similarly, each step (steps S3 to S7, S10 to S12, etc. in FIG. 5) of the aberration correction method of the STEM apparatus can be realized by operating a program stored in a RAM or ROM of a computer. This program and a computer-readable storage medium storing the program are included in this embodiment.

  Specifically, the program is recorded on a recording medium such as a CD-ROM or provided to a computer via various transmission media. As a recording medium for recording the program, besides a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used. On the other hand, as the program transmission medium, a communication medium in a computer network system for propagating and supplying program information as a carrier wave can be used. Here, the computer network is a WAN such as a LAN or the Internet, a wireless communication network, or the like, and the communication medium is a wired line such as an optical fiber or a wireless line.

  Further, the program included in the present embodiment is not limited to the one in which the functions of the above-described embodiments are realized by the computer executing the supplied program. For example, when the function of the above-described embodiment is realized in cooperation with an OS (operating system) running on a computer or other application software, the program is included in this embodiment. Further, when all or part of the processing of the supplied program is performed by the function expansion board or function expansion unit of the computer and the functions of the above-described embodiment are realized, such a program is included in this embodiment. .

  For example, FIG. 11 is a schematic diagram illustrating an internal configuration of a personal user terminal device. In FIG. 11, reference numeral 1200 denotes a personal computer (PC) having a CPU 1201. The PC 1200 executes device control software stored in the ROM 1202 or the hard disk (HD) 1211 or supplied from the flexible disk drive (FD) 1212. The PC 1200 generally controls each device connected to the system bus 1204.

  By the program stored in the CPU 1201, the ROM 1202, or the hard disk (HD) 1211 of the PC 1200, the procedures of steps S3 to S7 and S10 to S12 in FIG.

  Reference numeral 1203 denotes a RAM which functions as a main memory, work area, and the like for the CPU 1201. A keyboard controller (KBC) 1205 controls instruction input from a keyboard (KB) 1209, a device (not shown), or the like.

  Reference numeral 1206 denotes a CRT controller (CRTC), which controls display on a CRT display (CRT) 1210. Reference numeral 1207 denotes a disk controller (DKC). The DKC 1207 controls access to a hard disk (HD) 1211 and a flexible disk (FD) 1212 that store a boot program, a plurality of applications, an editing file, a user file, a network management program, and the like. Here, the boot program is a startup program: a program for starting execution (operation) of hardware and software of a personal computer.

Reference numeral 1208 denotes a network interface card (NIC) that exchanges data bidirectionally with a network printer, another network device, or another PC via the LAN 1220.
Instead of using a personal user terminal device, a predetermined computer specialized for an etching condition setting device may be used.

    Hereinafter, various aspects of the present case will be collectively described as additional notes.

(Appendix 1) A step of exposing a resist film formed on an object to be processed to form a resist pattern;
Etching the workpiece under predetermined etching conditions using the resist pattern as a mask, and
A method of manufacturing an electronic device, comprising: measuring a size and a shape of the formed resist pattern, and adjusting the etching condition based on the measured size and shape of the resist pattern.

(Appendix 2) A step of predicting a substantial dimension of the resist pattern corresponding to a desired dimension of the workpiece based on the measured dimension and shape of the resist pattern;
Calculating a difference value between a desired dimension of the resist pattern and the substantial dimension;
The method of manufacturing an electronic device according to claim 1, further comprising: adjusting the etching conditions based on the difference value.

  (Supplementary Note 3) In the step of adjusting the etching conditions, based on the relationship between the flow rate of the etching gas used for the etching and the dimensional change of the resist pattern, the dimension of the resist pattern is set to the desired dimension. The method of manufacturing an electronic device according to appendix 2, wherein the flow rate of the etching gas corresponding to the difference value is determined.

(Additional remark 4) Calculate the adjustment value which added the correction value of the amount of dimensional change based on the actual measurement size of the other above-mentioned processed object etched to the difference value,
4. The method of manufacturing an electronic device according to appendix 2 or 3, wherein the etching condition is adjusted based on the adjustment value.

  (Additional remark 5) The shape of the said resist pattern contains the taper angle of the said resist pattern, The manufacturing method of the electronic device of any one of Additional remark 1-4 characterized by the above-mentioned.

  (Supplementary note 6) The method of manufacturing an electronic device according to supplementary note 5, wherein the shape of the resist pattern includes a film thickness of the resist pattern.

(Appendix 7) A device for setting etching conditions when etching the workpiece using a resist pattern formed on the workpiece as a mask,
A dimension predicting unit that predicts a substantial dimension of the resist pattern corresponding to a desired dimension of the workpiece based on the measured dimension and shape of the resist pattern;
A difference value calculation unit for calculating a difference value between a desired dimension of the resist pattern and the substantial dimension;
And a condition adjusting unit that adjusts the etching condition based on the difference value.

  (Supplementary Note 8) The condition adjustment unit sets the difference value so that the dimension of the resist pattern becomes the desired dimension based on the relationship between the flow rate of the etching gas used for the etching and the dimensional change of the resist pattern. The setting apparatus according to appendix 7, wherein the flow rate of the corresponding etching gas is determined.

(Additional remark 9) The adjustment value calculation part which further calculates the adjustment value which added the correction value of the dimensional change based on the actual measurement size of the other above-mentioned processed object etched to the difference value,
The setting apparatus according to appendix 7 or 8, wherein the condition adjusting unit adjusts the etching condition based on the adjustment value.

  (Supplementary note 10) The setting device according to any one of supplementary notes 7 to 9, wherein the shape of the resist pattern includes a taper angle of the resist pattern.

  (Additional remark 11) The setting apparatus of Additional remark 10 characterized by the shape of the said resist pattern including the film thickness of the said resist pattern.

It is a characteristic view which shows the relationship between the width dimension of the formed gate electrode, and the dimension of a resist mask. It is a characteristic view showing the relationship between the taper angle of the resist pattern and the width dimension of the gate electrode. It is a characteristic view showing the relationship between the substantial dimension of the resist pattern and the width dimension of the gate electrode after etching. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by this embodiment in order of a process. It is a flowchart which shows the process of the lithography and dry etching by this embodiment. It is a block diagram which shows schematic structure of the setting apparatus of the etching conditions by this embodiment. It is a schematic plan view for demonstrating the method to measure the film thickness and taper angle of a resist pattern. It is a schematic sectional drawing which shows the process of FIG.4 (b) in detail. It is a characteristic view showing the relationship between the SO ₂ flow rate ratio and the width dimension of the gate electrode. It is a schematic sectional drawing which shows each dimension measurement site | part of a resist pattern and a gate electrode. It is a schematic diagram which shows the internal structure of a personal user terminal device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon semiconductor substrate 11 Element isolation structure 12 Gate insulating film 13 Gate electrode 14 Extension region 15 Side wall insulating film 16 Source / drain region 17 Interlayer insulating film 18 Contact plug 18a Contact hole 18b, 19a Base film 19 Wiring 21 Polycrystalline silicon film 22 resist film 23 resist pattern

Claims (3)

Exposing the resist film formed on the workpiece to form a resist pattern;
Etching the workpiece under predetermined etching conditions using the resist pattern as a mask, and
Measuring the width dimension, film thickness, and taper angle of the formed resist pattern;
Predicting the substantial width dimension of the resist pattern from the measured width dimension of the resist pattern, the film thickness, and the taper angle;
A step of calculating a desired width dimension of the resist pattern for aiming at a width dimension of the etched object to be processed when performing the etching step;
Calculating a first difference value between the desired width dimension and the substantial width dimension of the resist pattern;
And adjusting the etching conditions based on the difference value so that the width dimension of the object to be processed when the etching step is performed becomes the target width dimension. Manufacturing method. An apparatus for setting etching conditions when etching a workpiece using a mixed gas containing an etching gas using a resist pattern formed on the workpiece as a mask,
Dimension prediction for predicting the actual width dimension of the resist pattern adjusted with the parameters for setting the target processing target width dimension with the measured width dimension , film thickness, and taper angle of the resist pattern as parameters. And
A difference value calculation unit for calculating a difference value between the desired width dimension of the resist pattern and the substantial width dimension;
A condition adjusting unit that adjusts the etching conditions based on the difference value so that the width dimension of the object to be processed after etching becomes a target width dimension;
The desired width dimension of the resist pattern is a width dimension of the resist pattern when the etched width dimension of the object to be processed is a target width dimension. A dimensional change amount calculation unit for calculating a dimensional change amount from a difference between the actually measured width dimension of the etched object to be processed and the substantial width dimension of the resist pattern;
A correction value calculation unit that calculates a correction value from an average value of a plurality of dimensional change amounts calculated for each of the plurality of workpieces, and a target width dimension of the workpiece;
An adjustment value calculating unit for calculating an adjustment value for adjusting the etching condition from the difference value and the correction value;
The setting device according to claim 2, further comprising: a flow rate ratio calculation unit that calculates a value for changing the flow rate ratio of the etching gas from the adjustment value.

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