CN110504214A - 半导体组件制造方法和半导体组件 - Google Patents

半导体组件制造方法和半导体组件 Download PDF

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CN110504214A
CN110504214A CN201910410709.1A CN201910410709A CN110504214A CN 110504214 A CN110504214 A CN 110504214A CN 201910410709 A CN201910410709 A CN 201910410709A CN 110504214 A CN110504214 A CN 110504214A
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V·杜德克
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35 Power Electronics GmbH
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Abstract

半导体组件制造方法，其中提供具有上侧和下侧的半导体半成品，其包括多个彼此相邻的堆叠状构造的半导体组件，半导体组件分别具有具有III‑V族材料或锗的衬底层，衬底层布置在下侧处或附近；在衬底层上分别布置有一个第一导电能力类型的第一半导体层且在第一半导体层上布置有第二导电能力类型的至少一个第二半导体层，两个半导体层具有III‑V族材料或由III‑V族材料组成且两种导电能力类型不同；在两个直接相邻的半导体组件之间在半导体半成品的上侧上构造具有宽度L1的划刻框；沿划刻框将半导体组件分离；在分离前在半导体半成品的上侧上施加覆盖半导体组件且空出划刻框的至少一部分的掩模层；在施加掩模层后实施离子注入以进行至少部分非晶化和/或绝缘。

Description

半导体组件制造方法和半导体组件
技术领域
本发明涉及一种半导体组件制造方法以及一种半导体组件。
背景技术
为了制造半导体组件，通常地对完整的半导体晶片(也称为晶圆)进行处理并且接下来将其分离成各个芯片。
分离尤其通过锯、划刻(Ritzen)、破碎(Brechen)、借助激光或等离子蚀刻或借助所提及的方法的组合实现。
通常，沿划刻框(Ritzrahmen)由晶圆的上侧蚀刻直到衬底上。蚀刻过程也称为MESA蚀刻。接下来，将衬底锯穿。通常，蚀刻沟槽比锯更宽，并且这构成环绕的边缘。
发明内容
在这种背景下，本发明的任务在于，提出扩展现有技术的一种方法和一种设备。
该任务通过一种具有权利要求1的特征的半导体组件制造方法以及通过一种具有权利要求14的特征的堆叠状的半导体组件来解决。本发明有利的构型分别是从属权利要求的主题。
本发明的主题是一种半导体组件制造方法，其中，提供具有上侧和下侧的半导体半成品。
半导体半成品包括多个彼此相邻的堆叠状构造的半导体组件，其中，半导体组件分别具有一个衬底层，该衬底层具有III-V族材料或锗。
衬底层布置在下侧处或者在下侧附近。在衬底层上布置有第一导电能力类型的第一半导体层。
在第一半导体层上布置有第二导电能力类型的至少一个第二半导体层，其中，两个半导体层分别包括III-V族材料或由III-V族材料组成，并且两种导电能力类型是不同的。
在两个直接相邻的半导体组件之间在半导体半成品的上侧上构造有具有宽度L1的划刻框。
沿划刻框将半导体组件分离。
在分离前，在半导体半成品的上侧上施加掩模层，所述掩模层覆盖半导体组件并且空出(freilassen)划刻框的至少一部分。
在施加掩模层后，实施离子注入以进行绝缘和/或进行至少部分地非晶化(Amorphisierung)。
离子注入包括以至少500千电子伏特能量的至少一个注入步骤。
在离子注入后，将掩模层移除。在移除掩模层后，将半导体组件分离。
作为本发明的另一主题，提供一种堆叠状的半导体组件。
堆叠状的半导体组件具有上侧和下侧。此外，半导体组件具有将上侧与下侧连接的侧面。
下侧由衬底层和/或布置在衬底层以下的背侧接通层构成。
在衬底层上分别布置有一个第一导电能力类型的第一半导体层。在第一半导体层上布置有第二导电能力类型的至少一个第二半导体层。
两个半导体层包括III-V族材料或由III-V族材料组成。两种导电能力类型是不同的，即具有不同的极性。
沿侧面构造有延伸直至深度的非晶化和/或绝缘的区域。该深度的方向构造成垂直于层堆叠。
半导体半成品的或晶圆的表面的如下区域称为划刻框：应沿该区域将半导体半成品分开或分离。
借助划刻框将多个构造在半导体晶片上的分离的组件结构彼此分离。
掩模层空出划刻框，也就是说，掩模层具有相应的开口。在直接相邻的组件之间的区域通过开口保持可触及的。
优选地，除了注入区域外，借助掩模层或者通过掩模层中开口的宽度也预给定划刻框的位置和尤其划刻框的宽度。
借助离子注入至少部分地破坏划刻框的区域中的晶体结构和导电能力。可以理解：在半导体半成品的所有必要时后续的处理步骤中温度不允许如此高，使得通过在划刻框的注入区域中的注入产生的晶体缺陷(Kristalldefekt)再次恢复(ausheilen)。
换句话说，如果在离子注入后不实施退火步骤，那么划刻框的区域直至在通过离子的渗透深度预给定的深度中部分地或完全地保持绝缘。可以理解：在尤其通过锯进行分离的情况下所需要的宽度小于以离子注入所照射的区域的宽度。
在分离时产生的侧面和侧向的区域或边缘电绝缘地构造。
如果不实施MESA蚀刻，那么在例如通过锯进行分离的情况下构成优选垂直的侧面。最优选地，侧面完全垂直。
一个优点是如下：尤其在具有100V以上或1000V以上的截止电压(Sperrspannung)的高截止组件的情况下有效地抑制越过边缘的漏电流或分流。
根据本发明的方法的另一优点是：划刻框的区域直至分离是近似平坦的或完全平坦的，并且不实施MESA蚀刻或在替代的实施方案中仅仅在分离前实施短的MESA蚀刻。另一优点在于，在没有昂贵的和有问题的MESA蚀刻的情况下也可以将具有50μm以上的堆叠高度的半导体组件简单且可靠地彼此分离。
另一优点在于，借助非晶化可以抑制通过分离而到半导体组件上的应力(Spannung)。
根据第一实施方式，第一半导体层和第二半导体层分别包括GaAs(砷化镓)化合物或由GaAs化合物组成。
在另一实施方式中，借助离子注入将半导体半成品的上侧直至第一半导体层之间的深度区域、或半导体半成品的上侧至第二半导体层之间(包括第二半导体层)的深度区域、或半导体半成品的上侧直至衬底层之间的深度区域进行非晶化和/或绝缘。
在一种扩展方案中，注入氢离子或氦离子。
在另一扩展方案中，在注入期间在最小值至最大值之间改变离子的加速能量，其中，最小值是至少50千电子伏特并且最大值是最大300兆电子伏特。
可以理解：最大值和最小值确定离子的最大渗透深度或最小渗透深度。优选连续地实现改变能量，但是也可以阶梯状地或以任意其他的方式来实施改变能量。
优选地，在注入期间的注入计量是1010N/cm-2至1016N/cm-2之间。
根据另一扩展方案，在锯前或在锯后通过蚀刻方法将掩模层移除，尤其可以应用湿式化学方法。
可以理解：蚀刻方法取决于掩模层的材料。因此，可以例如借助盐酸或氯化氢(HCl)将由铝组成的掩模层移除，例如借助硫酸(H2SO4)将由钛组成的掩模层移除。
在另一实施方式中，在施加掩模层前，半导体半成品在上侧上和/或在下侧上具有金属接通面。优选地，接通面在上侧上和/或在下侧上包括金和/或钯。
替代地也能够实现，在注入和移除掩模层后才实施金属化——即施加接通面，例如焊盘和/或印制导线。在此，掩模层也覆盖在上侧处的接通面。
在另一扩展方案中，在施加掩模层前，借助化学气相沉积给半导体半成品的上侧涂覆具有至少100nm层厚的钝化层。
可以理解：在这种情况下，半导体半成品的上侧也通过钝化层构造或者完全通过钝化层构造，并且掩模层相应地布置在钝化层上。
由于钝化层和蚀刻停止层都用于随后移除掩模层，所以在注入前施加钝化层使制造简化。
半导体晶片几乎完成处理，并且可以在注入后以简单的方式例如借助干式蚀刻过程或湿式化学蚀刻过程将掩模层移除。
优选地，等离子支持地施加钝化层(PECVD)。优选地，钝化层包括SiO2或Si3N4。
根据另一扩展方案，在施加掩模层前，借助干式蚀刻将钝化层从布置在半导体半成品的表面上的至少一个接通面移除。
在另一实施方式中，通过离子注入在至少30μm和最大300μm的宽度上非晶化地和/或绝缘地构造划刻框。
在一种替代的实施方式中，通过掩模层中的开口的宽度确定划刻框的宽度。可以理解：由此划刻框在整个宽度上是非晶化的。
在一种扩展方案中，对于掩模层使用金属，尤其钛或铝。使用金属掩模的优点在于相比于半导体层较小的离子渗透深度。由此，在高能量的情况下也可靠地保护构造在掩模层以下的半导体区域免受损坏或非晶化。
在另一扩展方案中，第一半导体层和第二半导体层分别包括GaAs化合物或由GaAs化合物组成。
在一种实施方式中，部分地或完全地非晶化/绝缘的深度是至少0.5μm或至少5μm或至少30μm，或者替代地在上侧直至第一半导体层之间构造深度区域、或在上侧至第二半导体层之间(包括第二半导体层)构造深度区域、或在上侧直至衬底层之间构造深度区域。划刻框的全部的部分地或完全地非晶化/绝缘的区域以下也称为中间区域。
在一种实施方式中，掩模层直接布置在露出的金属接通面上。优选地，接通面的金属是在化学上选择性地抵抗用以例如借助HCl移除金属掩模层的湿式化学蚀刻步骤。由此简化制造且降低制造成本。
在另一实施方式中，半导体组件具有至少100μm和最大1000μm的高度H1。优选地，组件包括包括600伏特以上的截止电压的高截止GaAs功率二极管或具有500V以上的截止电压的IGBT。
附图说明
以下参照附图详细阐述本发明。在此，同类的部分以同样的标志来标记。所示出的实施方式是极其示意的，也就是说，间距以及横向和纵向的延伸不是按照比例的并且——只要未另外说明——也不具有彼此能推导的的几何关系。附图示出：
图1示出片状的半导体半成品的根据本发明的第一实施方式的截面；
图2示出堆叠状的半导体组件的根据本发明的第一实施方式的视图；
图3示出根据本发明的半导体组件制造方法的第一实施方式的离子的加速能量的图。
具体实施方式
图1的示图示出片状的半导体半成品100的第一实施方式的截面，所述半导体半成品具有上侧102和下侧104。半导体半成品100具有从下侧104直至上侧102的总高度H1。
下侧104通过衬底层SUB构成。在衬底层SUB上堆叠状地布置有三个半导体层HA1、HA2、HA3。半导体层HA1、HA2和HA3共计具有高度H2。在最上面的半导体层HA3的表面上布置有多个接通面K1。接通面K1包括焊盘以及印制导线。最上面的半导体层HA3的表面的未由接通面K1覆盖的部分和接通面的一部分(即印制导线)以具有厚度D1的钝化层P覆盖，从而半导体半成品100的上侧102由钝化层P和接通面K1的露出部分(即焊盘)构成。
在半导体半成品的上侧102上布置有结构化的掩模层M。掩模层M在上侧102上空出具有线宽度L1的多个划刻框。因此掩模层未覆盖划刻框并且仅仅覆盖上侧102的剩余部分或具有相应的窗口。
沿划刻框邻接中间区域106，该中间区域延伸到半导体半成品中并且通过虚线示出。中间区域106具有高度H3，其中，高度H3大于或等于由半导体层HA1、HA2和HA3的高度H2与钝化层P的厚度D1构成的总和。中间层的宽度B1相应于划刻框的宽度B1或掩模层M的窗口的宽度。中间区域106中的半导体材料是通过离子注入而非晶化的和/或绝缘的。
在例如通过沿划刻框锯来分离半导体半成品100并且例如通过干式蚀刻移除掩模层100后，存在根据本发明的具有非晶化的和/或绝缘的侧面的堆叠状的半导体组件。
在图2的示图中示出根据本发明的堆叠状的半导体组件10的第一实施方式。半导体组件10具有上侧12、下侧14以及四个侧面16，所述侧面将上侧12与下侧14连接。
半导体组件10包括由衬底层、紧跟第一半导体层HA1、第二半导体层HA2和第三半导体层HA3构成的堆叠。在第三半导体层HA3的上侧上布置有接通焊盘作为接通面K1。第三半导体层HA3的上侧的未由接通面K1覆盖的区域涂覆有钝化层P。钝化层P和接通面K1构成半导体组件10的上侧12。衬底层SUB的下侧完全涂覆有接通层作为背侧接通部K2。背侧接通部K2构成半导体组件10的下侧14。
半导体组件10的区域18是通过注入而非晶化的和/或绝缘的，所述区域从上侧12沿四个侧面14延伸直至第二接通面K2并且从每个侧面16延伸直至深度T1，其中，深度T1分别垂直于相应的侧面地延伸。
在图3的示图中对于根据所述根据本发明的半导体组件制造方法的第一实施方式的注入作为时间的函数示出离子的加速能量。注入离子以沿晶圆的划刻框产生非晶化的中间区域在时刻t1开始并且在时刻t2结束。在开始时离子具有加速能量Emax，接下来加速能量连续地降低，直至加速能量在时刻t2仅还具有值Emin。

Claims (17)

1.一种半导体组件制造方法，其中：
提供具有上侧(102)和下侧(104)的半导体半成品(100)，所述半导体半成品具有多个彼此相邻的堆叠状构造的半导体组件(BST)，其中，所述半导体组件(BST)分别具有一个衬底层(SUB)，所述衬底层具有III-V族材料或锗，并且所述衬底层(SUB)布置在所述下侧(104)处或者在所述下侧(104)附近；
在所述衬底层(SUB)上分别布置有一个第一导电能力类型的第一半导体层(HA1)并且在所述第一半导体层(HA1)上布置有第二导电能力类型的至少一个第二半导体层(HA2)，其中，所述两个半导体层(HA1，HA2)具有III-V族材料或由III-V族材料组成，并且两种导电能力类型是不同的；
在两个直接相邻的半导体组件(BST)之间在所述半导体半成品(100)的所述上侧(102)上构造有具有宽度L1的划刻框；
沿所述划刻框将所述半导体组件(BST)分离；
在所述分离前，在所述半导体半成品(100)的所述上侧(102)上施加掩模层(M)，所述掩模层覆盖所述半导体组件(BST)并且空出所述划刻框的至少一部分；
在施加所述掩模层(M)后，实施离子注入以进行至少部分地非晶化和/或进行绝缘，并且所述离子注入具有以至少500千电子伏特能量的至少一个注入步骤；
在所述离子注入后，将所述掩模层(M)移除；
并且在移除所述掩模层(M)后，将所述半导体组件(BST)分离；
在施加所述掩模层(M)前，借助化学气相沉积给所述半导体半成品(100)的所述上侧(102)涂覆具有至少100nm层厚的钝化层(P)。
2.根据权利要求1所述的半导体组件制造方法，其特征在于，所述第一半导体层(HA1)和所述第二半导体层(HA2)分别具有GaAs化合物或由GaAs化合物组成。
3.根据权利要求1或2所述的半导体组件制造方法，其特征在于，借助所述离子注入将所述上侧(102)直至所述第一半导体层(HA1)之间的深度区域、或所述上侧(102)与所述第二半导体层(HA2)之间——包括所述第二半导体层(HA2)的深度区域、或所述上侧(102)至衬底层(SUB)之间的深度区域进行非晶化和/或绝缘。
4.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，注入氢离子和/或氦离子。
5.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，在所述注入期间在最小值(Emin)至最大值(Emax)之间改变所述离子的加速能量(E)，其中，所述最小值(Emin)是至少50千电子伏特并且所述最大值(Emax)是最大300兆电子伏特。
6.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，在所述注入期间的注入计量是1010N/cm-2至1016N/cm-2之间。
7.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，在所述分离前，通过湿式化学蚀刻方法将所述掩模层(M)移除。
8.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，在构造所述掩模层(M)前，在所述上侧(102)上和/或在所述下侧(104)上构造金属接通面。
9.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，在施加所述掩模层(M)后，实施MESA蚀刻过程。
10.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，在至少30μm和最大300μm的宽度(B1)上对所述划刻框进行非晶化和/或进行绝缘。
11.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，对于所述掩模层(M)使用金属。
12.根据上述权利要求中任一项所述的半导体组件制造方法，其特征在于，对于所述掩模层(M)使用钛或铝。
13.一种堆叠状的半导体组件(10)，所述半导体组件具有上侧(12)、下侧(14)和至少一个侧面(16)，所述侧面将所述上侧(12)与所述下侧(14)连接，
所述下侧(14)由衬底层(SUB)或布置在所述衬底层(SUB)以下的背侧接通层(K2)构成；
在所述衬底层(SUB)上分别布置有一个第一导电能力类型的第一半导体层(HA1)并且在所述第一半导体层(HA1)上布置有第二导电能力类型的至少一个第二半导体层(HA2)，其中，所述两个半导体层(HA1，HA2)具有III-V族材料或由III-V族材料组成，并且两种导电能力类型是不同的；
所述上侧(12)至少部分地由钝化层构成；
沿所述侧面(16)构造延伸直至一深度(T1)的非晶化的和/或绝缘的区域(18)，其中，所述深度(T1)垂直于所述层堆叠地构造。
14.根据权利要求14所述的堆叠状的半导体组件(10)，其特征在于，所述第一半导体层(HA1)和所述第二半导体层(HA2)分别具有GaAs化合物或由GaAs化合物组成。
15.根据权利要求14或15所述的堆叠状的半导体组件(10)，其特征在于，所述深度(T1)是至少0.5μm或至少5μm或至少30μm，或者在所述上侧(102)直至所述第一半导体层(HA1)之间构造深度区域、或在所述上侧(102)与所述第二半导体层(HA2)之间——包括所述第二半导体层(HA2)构造深度区域、或在所述上侧(102)至所述衬底层(SUB)之间构造深度区域。
16.根据权利要求14至17中任一项所述的堆叠状的半导体组件(10)，其特征在于，在上侧(12)上的接通面(K1)和/或所述背侧接通层(K2)具有金、银和/或钯。
17.根据权利要求12至15中任一项所述的堆叠状的半导体组件(10)，其特征在于，所述半导体组件(10)具有至少10μm和最大1000μm的总高度(H1)。
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