CN110459594B - Embedded isolation ring silicon controlled rectifier capable of being used for electrostatic discharge protection - Google Patents
Embedded isolation ring silicon controlled rectifier capable of being used for electrostatic discharge protection Download PDFInfo
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- CN110459594B CN110459594B CN201910805721.2A CN201910805721A CN110459594B CN 110459594 B CN110459594 B CN 110459594B CN 201910805721 A CN201910805721 A CN 201910805721A CN 110459594 B CN110459594 B CN 110459594B
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- 238000002955 isolation Methods 0.000 title claims abstract description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 25
- 239000010703 silicon Substances 0.000 title claims abstract description 25
- 238000002347 injection Methods 0.000 claims abstract description 48
- 239000007924 injection Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000007943 implant Substances 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000003068 static effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 113
- 230000005684 electric field Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
Abstract
The utility model provides an embedded isolating ring silicon controlled rectifier that can be used to static and release protection, includes P type substrate, N well district and the P well district that P type substrate upper surface both sides set up, the positive pole that N well district internal surface set up, the negative pole that P well district internal surface set up, the third N+ district that sets up at P type substrate upper surface and both ends set up in N well district and P well district inside, N type isolating ring and/or P type isolating ring. The N-type isolation ring comprises an N buried layer arranged below the N well region, a first N-type deep injection layer arranged on one side of the N well region far away from the P well region and contacted with the N well region and the N buried layer, and a second N-type deep injection layer arranged on one side of the N well region near the P well region and contacted with the N well region and the N buried layer; the P-type isolation ring comprises a P buried layer arranged below the P well region, a first P-type deep injection layer arranged on one side of the P well region far away from the N well region and contacted with the P well region and the P buried layer, and a second P-type deep injection layer arranged on one side of the P well region near the N well region and contacted with the P well region and the P buried layer.
Description
Technical Field
The invention belongs to the field of electronic science and technology, and relates to a high-maintenance-voltage embedded isolation ring silicon controlled rectifier which can be used for electrostatic discharge (Electro Static Discharge, abbreviated as ESD) protection technology.
Background
Electrostatic discharge (ESD) is one of the most important killers of Integrated Circuits (ICs), and as the integrated level of the integrated circuits increases, the performance of various ICs is greatly improved and the tolerance to ESD is greatly reduced. In high voltage applications, ESD devices are required to have small area, latch-up resistance, and the like, in addition to high robustness. To prevent latch-up, silicon Controlled Rectifier (SCR) structures are prohibited. However, the SCR structure has the strongest electrostatic discharge efficiency and the smallest area occupation, so in recent years, ESD protection using the SCR to a high voltage circuit has become one of the hot researches in the ESD field.
The SCR structure consists of four layers of PNPN semiconductors. The embedded PNP and NPN structures are mutually amplified to form positive feedback after being triggered, and finally an almost short-circuited channel is formed. If the minimum hold voltage (Vh) after the device turns on is less than the maximum voltage of the protected port, the device will not self-turn off after an ESD event, causing latch-up.
Disclosure of Invention
Aiming at the defect that the traditional silicon controlled rectifier usually causes latch-up effect, the isolation ring is introduced into the silicon controlled rectifier device, the silicon controlled rectifier embedded with the isolation ring is provided, and the lowest point maintenance voltage Vh of the SCR structure of the silicon controlled rectifier can be improved, so that the latch-up effect is avoided, and the silicon controlled rectifier can be used for electrostatic discharge protection.
The technical scheme of the invention is as follows:
an embedded isolation ring thyristor for electrostatic discharge protection, comprising:
a P-type substrate;
the N well region and the P well region are arranged on two sides of the upper surface of the P type substrate;
the anode is arranged on the inner surface of the N well region;
the cathode is arranged on the inner surface of the P well region;
the third N+ region is arranged on the upper surface of the P-type substrate, and two ends of the third N+ region are respectively arranged in the N well region and the P well region;
the silicon controlled rectifier also comprises an N-type isolation ring and/or a P-type isolation ring;
the N-type isolation ring comprises:
an N buried layer arranged below the N well region;
the first N-type deep injection layer is arranged on one side, far away from the P-well region, of the N-well region and is in contact with the N-well region and the N buried layer, and the first N-type deep injection layer is positioned on the upper surface of the P-type substrate;
the second N-type deep injection layer is arranged on one side, close to the P well region, of the N well region and is in contact with the N well region and the N buried layer, and the upper surface of the second N-type deep injection layer is in contact with the lower surface of the third N+ region;
the P-type spacer ring includes:
a P buried layer arranged below the P well region;
the first P-type deep injection layer is arranged on one side, far away from the N-well region, of the P-well region and is in contact with the P-well region and the P buried layer, and the first P-type deep injection layer is positioned on the upper surface of the P-type substrate;
the second P-type deep injection layer is arranged on one side of the P well region, close to the N well region, and is in contact with the P well region and the P buried layer, and the upper surface of the second P-type deep injection layer is in contact with the lower surface of the third N+ region.
Specifically, the region in the N-well region and located between the anode and the third n+ region further includes a plurality of third N-type deep injection layers, where the third N-type deep injection layers are used for separating the N-well region and the N-buried layer at two sides of the third N-type deep injection layers.
Specifically, the region located between the cathode and the third n+ region in the P-well region further includes a plurality of third P-type deep injection layers, where the third P-type deep injection layers are used for separating the P-well region and the P-buried layer at two sides of the third P-type deep injection layers.
Specifically, the anode comprises a first N+ region and a first P+ region which are arranged on the upper surface of the N well region and are connected through metal, and the cathode comprises a second N+ region and a second P+ region which are arranged on the upper surface of the P well region and are connected through metal.
The working principle of the invention is as follows:
since latch-up is caused when the minimum point holding voltage (Vh) after device turn-on is less than the maximum voltage of the protected port, the latch-up resistance problem can be converted into a problem of raising Vh of the SCR. In principle, vh is the integral of the electric field, and the electric field has a large relationship with the carrier distribution. Studies have shown that the dual large implant effect of PNP and NPN causes the kirk effect (kirk effect) of both transistors. So that the electric field distribution will be determined by the unbalanced carrier concentration. Therefore, optimizing the doping concentration of regions within the device can change the distribution of the electric field, thereby changing the magnitude of Vh. Based on the theory, the invention provides a novel silicon controlled rectifier SCR structure which adopts the isolating ring to change the electric field distribution, and the isolating ring is introduced into the silicon controlled rectifier device for improving the lowest point maintaining voltage of the silicon controlled rectifier. In the following description, an N-type spacer is taken as an example, and since the N-well region 11 of the SCR device is doped with medium and low concentrations, when the current density reaches a certain value, the unbalanced carrier concentration (J/qv) will easily exceed the intrinsic doping concentration of the N-well region 11, so that the electric field distribution will be determined by the current density and the extrinsic doping concentration. As can be seen from poisson's equation, the electric field peaks will be transferred from the junction of the N-well region 11 and the P-type substrate 21 to the junction of the first p+ region 02 and the N-well region 11. Therefore, the holding voltage of the SCR corresponds to the integral of the electric field at the junction of the first p+ region 02 and the N well region 11 and the electric field at the junction of the cathode P well region 12 and the second n+ region 03. However, by isolation of the N-type isolation ring, the first N-type deep injection layer 071, the second N-type deep injection layer 072 and the N buried layer are all layers with higher concentration, and the electric field is not transferred at the position, so in the silicon controlled device with embedded isolation ring provided by the invention, vh is equivalent to the electric field between the second N-type deep injection layer 072 and the P-well region 12 added on the basis of the integral of the original silicon controlled rectifier SCR electric field, and therefore the lowest point maintaining voltage Vh is improved. The P-type isolation ring is similar to the multi-layer isolation ring in principle, and can improve the lowest point maintaining voltage Vh of the silicon controlled rectifier.
The beneficial effects of the invention are as follows: the isolation ring is introduced into the silicon controlled device, and high maintenance voltage and acceptable trigger voltage values are realized through the blocking of the isolation ring formed by the high-concentration buried layer and the deep injection layer, so that the latch-up effect is avoided; the number of the isolation rings is adjusted to realize the adjustment of the lowest point maintaining voltage, and the latch-up effect caused by electrostatic discharge ESD is well inhibited.
Drawings
Fig. 1 is a schematic structural diagram of an embedded isolation ring thyristor for electrostatic discharge protection according to the present invention, in which an N-type isolation ring is disposed in the first embodiment.
Fig. 2 is a schematic structural diagram of an embedded isolation ring thyristor for electrostatic discharge protection according to the present invention, in which three N-type isolation rings are provided in the second embodiment.
Fig. 3 is a schematic structural diagram of an embedded isolation ring thyristor for electrostatic discharge protection according to the third embodiment of the present invention, in which a P-type isolation ring is disposed.
Fig. 4 is a schematic structural diagram of an embedded isolation ring thyristor for electrostatic discharge protection according to the present invention, in which three layers of P-type isolation rings are disposed in the fourth embodiment.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings and specific embodiments.
The invention provides a scheme for embedding a spacer ring into a silicon controlled rectifier, wherein the spacer ring is usually used for isolating an integrated circuit rather than for the inside of a device. The isolation ring used in the silicon controlled rectifier provided by the invention can only comprise an N-type isolation ring, can only comprise a P-type isolation ring, and can also comprise an N-type isolation ring and a P-type isolation ring, and in addition, in the silicon controlled rectifier comprising the N-type isolation ring and/or the P-type isolation ring, the N-type isolation ring and/or the P-type isolation ring can only comprise one layer of isolation ring, and can also comprise a plurality of layers of isolation rings, and the following description is made by combining five specific embodiments.
The specific embodiment I is as follows:
in this embodiment, an N-type spacer structure is used, and only one spacer is included. As shown in fig. 1, the thyristor with embedded N-type isolation ring in this embodiment includes: the P-type substrate 21, the N-well region 11, the P-well region 12, the anode, the cathode, the third n+ region 05, the first N-type deep implanted layer (N-sink layer) 071, the second N-type deep implanted layer (N-sink layer) 072 and the N buried layer (NBL layer) 09, the N-well region 11 and the P-well region 12 are respectively disposed on the left side and the right side of the upper surface of the P-type substrate. In this embodiment, the anode includes a first n+ region 01 and a first p+ region 02, the cathode includes a second n+ region 03 and a second p+ region 04, and the first n+ region 01 and the first p+ region 02 are designed on the inner surface of the N well region 11, and the positional relationship is tangential or separated. The second n+ region 03 and the second p+ region 04 are designed on the inner surface of the P-well region 12, and the positional relationship is tangential or separated. The first n+ region 01 and the first p+ region 02 are connected through metal to form the anode of the whole device. The second n+ region 03 is connected to the second p+ region 04 through metal, and forms the cathode of the whole device. The third n+ region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third n+ region 05 are disposed in the N-well region and the P-well region, that is, the left edge of the third n+ region 05 is located in the N-well region 11, and the right edge is located in the P-well region 12, so as to form a crossover. The first N-type deep implant 071 is located on the left side of the N-well 11 with its right edge tangential to the left edge of the N-well 11. The second N-type deep implant 072 is located to the right of the N-well 11 with its left edge tangential to the right edge of the N-well 11. Below the N-well region 11, there is an N-buried layer (NBL layer) 09, and the N-buried layer 09 may be provided to be the same length as the N-well region 11 and to have a certain longitudinal thickness. The upper edge of the N buried layer 09 is tangent to the lower edge of the N well 11, the left edge is tangent to the first N-type deep implant 071, and the right edge is tangent to the second N-type deep implant 072. The above structures are all fabricated on the P-type substrate 21.
And a specific embodiment II:
for the N-type isolation ring, if the power supply voltage to be protected is higher, the single-layer isolation ring cannot meet the Vh requirement, and then a mode of multiple isolation rings can be adopted. In this embodiment, two third N-type deep implanted layers 0721 and 0722 are further disposed in the region between the anode and the third n+ region 05, so as to form a three-layer N-type isolation ring. As shown in fig. 2, the thyristor with three N-type isolation rings embedded therein in this embodiment includes: the P-type substrate 21, the N-well region 11, the P-well region 12, the anode, the cathode, the third n+ region 05, the first N-type deep implanted layer (N-sink layer) 071, the second N-type deep implanted layer (N-sink layer) 072, the two third N-type deep implanted layers 0721 and 0722, the N buried layer (NBL layer) 09, the anode in this embodiment also includes the first n+ region 01 and the first p+ region 02, and the cathode also includes the second n+ region 03 and the second p+ region 04. The N-well region 11 and the P-well region 12 are disposed on the left and right sides of the upper surface of the P-type substrate, respectively. The first n+ region 01 and the first p+ region 02 are designed on the inner surface of the N well region 11, and the positional relationship is tangential or separated. The second n+ region 03 and the second p+ region 04 are designed on the inner surface of the P-well region 12, and the positional relationship is tangential or separated. The first n+ region 01 and the first p+ region 02 are connected through metal to form the anode of the whole device. The second n+ region 03 is connected to the second p+ region 04 through metal, and forms the cathode of the whole device. The third n+ region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third n+ region 05 are disposed in the N-well region and the P-well region, that is, the left edge of the third n+ region 05 is located in the N-well region 11, and the right edge is located in the P-well region 12, so as to form a crossover.
The specific structure of the three-layer N-type isolation ring in this embodiment is: the first N-type deep implant 071 is located on the left side of the N-well 11 with its right edge tangential to the left edge of the N-well 11. The second N-type deep implant 072 is located to the right of the N-well 11 with its left edge tangential to the right edge of the N-well 11. Two third N-type deep implants 0721 and 0722 are arranged in the N-well region 11 and in the region between the anode and the third n+ region 05, the third N-type deep implant 0722 is located inside the N-well region 11 on the left side of the second N-type deep implant 072, the third N-type deep implant 0721 is located inside the N-well region 11 on the left side of the third N-type deep implant 0722, the third N-type deep implant 0721 separates the N-well region 11 and the N-buried layer 09 on the left and right sides thereof, and the third N-type deep implant 0722 separates the N-well region 11 and the N-buried layer 09 on the left and right sides thereof. Below the N-well region 11 there is an N-buried layer 09, which N-buried layer 09 may be provided with the same length as the N-well region 11 and with a certain longitudinal thickness. The upper edge of the N buried layer 09 is tangent to the lower edge of the N well region 11, the left edge is tangent to the right edge of the first N-type deep implanted layer 071, the right edge is tangent to the second N-type deep implanted layer 072, the middle of the N buried layer 09 is separated by two third N-type deep implanted layers 0721 and 0722, and all the above structures are fabricated on the P-type substrate 21.
In this embodiment, the first N-type deep implanted layer 071, the N-buried layer 09, and the third N-type deep implanted layer 0721 form a first N-type isolation ring, the first N-type deep implanted layer 071, the N-buried layer 09, and the third N-type deep implanted layer 0722 form a second N-type isolation ring, and the first N-type deep implanted layer 071, the N-buried layer 09, and the second N-type deep implanted layer 072 form a third N-type isolation ring.
And a third specific embodiment:
because the lowest point maintaining voltage Vh of the device strongly depends on the concentration of the internal NW region and PW region, and for some processes, the P-type isolation ring has higher concentration and smaller layout rule, so that the improvement of the structure Vh can be further improved by optimizing and changing the PNP electric field by the P-type isolation ring and the PBL layer.
As shown in fig. 3, a silicon controlled structure with a P-type isolation ring is adopted, and this embodiment uses a P-type isolation ring as an example to illustrate the embodiment, including: the anode in this embodiment also includes a first n+ region 01 and a first p+ region 02, and the cathode also includes a second n+ region 03 and a second p+ region 04. The N well region 11 and the P well region 12 are respectively disposed on the left side and the right side of the upper surface of the P-type substrate, and the first n+ region 01 and the first p+ region 02 are designed on the inner surface of the N well region 11, and the positional relationship is tangential or separated. The second n+ region 03 and the second p+ region 04 are designed on the inner surface of the P-well region 12, and the positional relationship is tangential or separated. The first n+ region 01 and the first p+ region 02 are connected through metal to form the anode of the whole device. The second n+ region 03 is connected to the second p+ region 04 through metal, and forms the cathode of the whole device. The third n+ region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third n+ region 05 are disposed in the N-well region and the P-well region, that is, the left edge of the third n+ region 05 is located in the N-well region 11, and the right edge is located in the P-well region 12, so as to form a crossover. The first P-type deep implant 081 is located to the left of the P-well region 12 with its right edge tangential to the left edge of the P-well region 12. The second P-type deep implant 082 is located on the right side of the P-well region 12, and its left edge is tangential to the right edge of the P-well region 12. Below the P-well region 12 there is a P-buried layer 10, which P-buried layer 10 may be provided to be the same length as the P-well region 12 and to have a certain longitudinal thickness. The upper edge of the P buried layer 10 is tangent to the lower edge of the P well region 12, the left edge is tangent to the first P-type deep implanted layer 081, and the right edge is tangent to the second P-type deep implanted layer 082. The above structures are all fabricated on the P-type substrate 21.
And a specific embodiment IV:
for the P-type isolation ring, if the power supply voltage to be protected is higher, the single-layer P-type isolation ring cannot meet the Vh requirement, and then a multiple isolation ring mode can be adopted. In this embodiment, two third P-type deep injection layers 0811 and 0812 are further disposed in the region between the cathode and the third n+ region 05, and a three-layer P-type isolation ring is formed. As shown in fig. 4, the thyristor with three layers of P-type isolation rings embedded therein in this embodiment includes: the anode comprises a first n+ region 01 and a first p+ region 02, and the cathode comprises a second n+ region 03 and a second p+ region 04. The N well region 11 and the P well region 12 are respectively disposed on the left side and the right side of the upper surface of the P-type substrate, and the first n+ region 01 and the first p+ region 02 are designed on the inner surface of the N well region 11, and the positional relationship is tangential or separated. The second n+ region 03 and the second p+ region 04 are designed on the inner surface of the P-well region 12, and the positional relationship is tangential or separated. The first n+ region 01 and the first p+ region 02 are connected through metal to form the anode of the whole device. The second n+ region 03 is connected to the second p+ region 04 through metal, and forms the cathode of the whole device. The third n+ region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third n+ region 05 are disposed in the N-well region and the P-well region, that is, the left edge of the third n+ region 05 is located in the N-well region 11, and the right edge is located in the P-well region 12, so as to form a crossover.
The specific structure of the three-layer P-type isolation ring in this embodiment is: the second P-type deep implant 081 is located to the left of the P-well region 12, with its right edge tangential to the left edge of the P-well region 12. First P-type deep implant 082 is located on the right side of P-well region 12 with its left edge tangential to the right edge of P-well region 12. Two third P-type deep implants 0811 and 0812 are provided in the region of the P-well region 12 between the cathode and the third N + region 05, and the third P-type deep implant 0811 is located inside the P-well region 12 to the right of the second P-type deep implant 081. The third P-type deep implant 0812 is located inside the P-well region 12 to the right of the third P-type deep implant 0811. The third P-type deep implantation layer 0811 separates the P-well region 12 and the P-buried layer 10 on the left and right sides thereof, and the third P-type deep implantation layer 0812 separates the P-well region 12 and the P-buried layer 10 on the left and right sides thereof. Below the P-well region 12 there is a P-buried layer 10, which P-buried layer 10 may be provided to be the same length as the P-well region 12 and to have a certain longitudinal thickness. The upper edge of the P buried layer 10 is tangent to the lower edge of the P well region 12, the left edge is tangent to the second P type deep injection layer 081, the right edge is tangent to the first P type deep injection layer 082, and the middle portion two third P type deep injection layers 0811 and 0812 are separated. The above structures are all fabricated on the P-type substrate 21.
Similarly, in this embodiment, the first P-type deep injection layer 082, the P-buried layer 10, and the third P-type deep injection layer 0812 form a first P-type isolation ring, the first P-type deep injection layer 082, the P-buried layer 10, and the third P-type deep injection layer 0811 form a second P-type isolation ring, and the first P-type deep injection layer 082, the P-buried layer 10, and the second P-type deep injection layer 081 form a third P-type isolation ring.
Fifth embodiment:
in combination with the above four embodiments, the silicon controlled rectifier with embedded isolation ring according to the present invention may further simultaneously provide one or more layers of N-type isolation ring and P-type isolation ring in the same device, where the silicon controlled rectifier device including N-type isolation ring and P-type isolation ring includes a P-type substrate 21, an N-well region 11, a P-well region 12, an anode, a cathode, a third n+ region 05, a first P-type deep injection layer 082, a second P-type deep injection layer 081, a P-buried layer 10, a first N-type deep injection layer 071, a second N-type deep injection layer 072, and an N-buried layer 09, and if the multi-layer isolation ring structure further includes a plurality of third P-type deep injection layers disposed in the P-well region 12 and located in a region between the cathode and the third n+ region 05, and a plurality of third N-type deep injection layers disposed in the N-well region 11 and located in a region between the anode and the third n+ region 05.
In summary, the invention provides a SCR device with embedded isolation ring structure for ESD protection, which realizes latch-up free ESD protection with high Vh by the influence of isolation ring composed of high concentration buried layer and deep injection layer on electric field under large injection. Meanwhile, the number of the isolation rings can be adjusted to adjust the Vh voltage, and the latch-up effect caused by ESD is well inhibited. The invention realizes the process compatibility of the device in the integrated circuit on one hand and the controllability of the maintenance voltage on the other hand, thereby being particularly suitable for the ESD protection engineering of the high-voltage integrated circuit.
Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (4)
1. An embedded isolation ring thyristor for electrostatic discharge protection, comprising:
a P-type substrate;
the N well region and the P well region are arranged on two sides of the upper surface of the P type substrate;
the anode is arranged on the inner surface of the N well region;
the cathode is arranged on the inner surface of the P well region;
the third N+ region is arranged on the upper surface of the P-type substrate, and two ends of the third N+ region are respectively arranged in the N well region and the P well region;
the silicon controlled rectifier is characterized by further comprising an N-type isolation ring and/or a P-type isolation ring;
the N-type isolation ring comprises:
an N buried layer arranged below the N well region;
the first N-type deep injection layer is arranged on one side, far away from the P-well region, of the N-well region and is in contact with the N-well region and the N buried layer, and the first N-type deep injection layer is positioned on the upper surface of the P-type substrate;
the second N-type deep injection layer is arranged on one side, close to the P well region, of the N well region and is in contact with the N well region and the N buried layer, and the upper surface of the second N-type deep injection layer is in contact with the lower surface of the third N+ region;
the P-type spacer ring includes:
a P buried layer arranged below the P well region;
the first P-type deep injection layer is arranged on one side, far away from the N-well region, of the P-well region and is in contact with the P-well region and the P buried layer, and the first P-type deep injection layer is positioned on the upper surface of the P-type substrate;
the second P-type deep injection layer is arranged on one side of the P well region, close to the N well region, and is in contact with the P well region and the P buried layer, and the upper surface of the second P-type deep injection layer is in contact with the lower surface of the third N+ region.
2. The embedded spacer-ring thyristor for electrostatic discharge protection according to claim 1, wherein said N-well region and said region between said anode and said third n+ region further comprises a plurality of third N-type deep implants for separating said N-well region and said buried N-layer on both sides thereof.
3. The embedded spacer-ring thyristor for electrostatic discharge protection according to claim 1 or 2, wherein the region between the cathode and the third n+ region in the P-well region further comprises a plurality of third P-type deep implants for separating the P-well region and the P-buried layer on both sides thereof.
4. The embedded spacer ring thyristor for electrostatic discharge protection according to claim 1, wherein said anode comprises a first n+ region and a first p+ region disposed on an upper surface of said N well region and connected by metal, and said cathode comprises a second n+ region and a second p+ region disposed on an upper surface of said P well region and connected by metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910805721.2A CN110459594B (en) | 2019-08-29 | 2019-08-29 | Embedded isolation ring silicon controlled rectifier capable of being used for electrostatic discharge protection |
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| CN210092089U (en) * | 2019-08-29 | 2020-02-18 | 成都矽能科技有限公司 | High-maintenance-voltage silicon controlled rectifier with embedded isolating ring |
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