CN210092089U - High-maintenance-voltage silicon controlled rectifier with embedded isolating ring - Google Patents
High-maintenance-voltage silicon controlled rectifier with embedded isolating ring Download PDFInfo
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- CN210092089U CN210092089U CN201921418257.3U CN201921418257U CN210092089U CN 210092089 U CN210092089 U CN 210092089U CN 201921418257 U CN201921418257 U CN 201921418257U CN 210092089 U CN210092089 U CN 210092089U
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 26
- 239000010703 silicon Substances 0.000 title claims abstract description 26
- 238000002347 injection Methods 0.000 claims abstract description 57
- 239000007924 injection Substances 0.000 claims abstract description 57
- 238000002955 isolation Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000007943 implant Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 12
- 238000012423 maintenance Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 151
- 238000002513 implantation Methods 0.000 description 17
- 230000005684 electric field Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000005374 Kerr effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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Abstract
The utility model provides a high maintenance voltage silicon controlled rectifier with embedded isolating ring, includes P type substrate, the well region of N and the well region of P that the upper surface both sides set up on the P type substrate, the positive pole that well region of N internal surface set up, the negative pole that well region of P internal surface set up sets up, sets up on P type substrate upper surface and both ends set up in the well region of N and the inside third N + district of well region of P, N type isolating ring and/or P type isolating ring. The N-type isolation ring comprises an N buried layer arranged below the N well region, a first N-type deep injection layer arranged on one side, far away from the P well region, of the N well region and in contact with the N well region and the N buried layer, and a second N-type deep injection layer arranged on one side, close to the P well region, of the N well region and in contact with the N well region and the N buried layer; the P-type isolation ring comprises a P buried layer arranged below the P well region, a first P-type deep injection layer arranged on one side, far away from the N well region, of the P well region and in contact with the P well region and the P buried layer, and a second P-type deep injection layer arranged on one side, close to the N well region, of the P well region and in contact with the P well region and the P buried layer.
Description
Technical Field
The utility model belongs to the technical field of electronic science and, a high maintenance voltage silicon controlled rectifier with embedded isolating ring is related to, can be used for electrostatic Discharge (Electro Static Discharge, ESD for short) protection technique.
Background
Electrostatic discharge (ESD) is one of the most important killers of Integrated Circuits (ICs), and with the increase of the integration level of the ICs, the tolerance of various ICs to ESD is greatly reduced while the performance is greatly increased. In high voltage applications, besides high robustness, ESD devices are also required to have small area and latch-up resistance. To prevent latch-up, Silicon Controlled Rectifier (SCR) structures are prohibited. However, the SCR structure has the strongest ESD efficiency and the smallest area occupation, so in recent years, the use of SCR for ESD protection of high voltage circuit has become one of the hot researches in the ESD field.
The SCR structurally consists of four layers of PNPN semiconductors. The embedded PNP and NPN structures are mutually amplified to form positive feedback after being triggered, and finally, a channel which is nearly short-circuited is presented. If the lowest point holding voltage (Vh) after the device turns on is less than the maximum voltage of the protected port, the device will not self-turn off after an ESD event, causing latch-up.
SUMMERY OF THE UTILITY MODEL
Can lead to latch-up's weak point usually to above-mentioned traditional silicon controlled rectifier, the utility model discloses inside introducing the silicon controlled rectifier device with the isolating ring, provided the silicon controlled rectifier of an embedded isolating ring, can improve the minimum holding voltage Vh of silicon controlled rectifier SCR structure to avoid latch-up's emergence, can be used for the static protection of releasing.
The technical scheme of the utility model is that:
a high-sustain voltage thyristor with an embedded isolation ring, comprising:
a P-type substrate;
the N well region and the P well region are arranged on two sides of the upper surface of the P type substrate;
the anode is arranged on the inner surface of the N well region;
the cathode is arranged on the inner surface of the P well region;
the third N + region is arranged on the upper surface of the P-type substrate, and two ends of the third N + region are respectively arranged in the N well region and the P well region;
the silicon controlled rectifier also comprises an N-type isolating ring and/or a P-type isolating ring;
the N-type isolating ring comprises:
an N buried layer disposed below the N well region;
the first N-type deep injection layer is arranged on one side, far away from the P well region, of the N well region and is in contact with the N well region and the N buried layer, and the first N-type deep injection layer is located on the upper surface of the P-type substrate;
the second N-type deep injection layer is arranged on one side, close to the P well region, of the N well region and is in contact with the N well region and the N buried layer, and the upper surface of the second N-type deep injection layer is in contact with the lower surface of the third N + region;
the P-type isolating ring comprises:
a P buried layer disposed below the P well region;
the first P-type deep injection layer is arranged on one side, far away from the N-well region, of the P-well region and is in contact with the P-well region and the P buried layer, and the first P-type deep injection layer is located on the upper surface of the P-type substrate;
and the second P-type deep injection layer is arranged on one side of the P well region close to the N well region and is in contact with the P well region and the P buried layer, and the upper surface of the second P-type deep injection layer is in contact with the lower surface of the third N + region.
Specifically, the region in the N-well region and located between the anode and the third N + region further includes a plurality of third N-type deep injection layers, and the third N-type deep injection layers are used for separating the N-well region and the N buried layer on both sides of the third N-type deep injection layers.
Specifically, the region in the P-well region and located between the cathode and the third N + region further includes a plurality of third P-type deep injection layers, and the third P-type deep injection layers are used for separating the P-well region and the P buried layer on both sides of the third P-type deep injection layers.
Specifically, the anode includes a first N + region and a first P + region disposed on the upper surface of the N-well region and connected to each other through metal, and the cathode includes a second N + region and a second P + region disposed on the upper surface of the P-well region and connected to each other through metal.
The utility model discloses a theory of operation does:
since latch-up is caused when the lowest point sustain voltage (Vh) after the device is turned on is less than the maximum voltage of the protected port, the problem of latch-up resistance can be transformed into the problem of increasing Vh of the SCR. In principle, Vh is the integral of the electric field, and the distribution of the electric field and carriers is strongly related. Research has shown that the double large injection effect of PNP and NPN can cause Kerr effect (kirk effect) of two transistors. So that the electric field distribution will be determined by the non-equilibrium carrier concentration. Therefore, optimizing the doping concentration in each region in the device can change the distribution of the electric field, thereby changing the size of Vh. Based on this theory, the utility model provides an adopt the isolating ring to change the novel silicon controlled rectifier SCR structure of electric field distribution, introduce the silicon controlled rectifier device with the isolating ring inside for improve the minimum holding voltage of silicon controlled rectifier. Taking an N-type isolation ring as an example, since the N-well region 11 of the SCR device is usually doped with medium-low concentration, when the current density reaches a certain value, the non-equilibrium carrier concentration (J/qv) will easily exceed the intrinsic doping concentration of the N-well region 11, so the electric field distribution will be determined by the current density rather than the extrinsic doping concentration. According to poisson's equation, the electric field peak is transferred from the boundary of the N-well region 11 and the P-type substrate 21 to the boundary of the first P + region 02 and the N-well region 11. Therefore, the holding voltage of the SCR is equivalent to the integral of the electric field at the boundary of the first P + region 02 and the N well region 11 and the electric field at the boundary of the cathode P well region 12 and the second N + region 03. But through the isolation of N type isolating ring, because first N type deep injection layer 071, second N type deep injection layer 072 and N buried layer are the higher level of concentration, the electric field can not take place to shift here, consequently in the utility model provides an embedded isolating ring's silicon controlled rectifier device, Vh has increased the electric field between second N type deep injection layer 072 and the well region 12 of P on being equivalent to the basis of original silicon controlled rectifier SCR electric field integral, therefore minimum holding voltage Vh will improve. The principle of the P-type isolating ring is similar to that of a multilayer isolating ring, and the lowest point maintaining voltage Vh of the controllable silicon can be improved.
The utility model has the advantages that: the utility model introduces the isolating ring into the silicon controlled rectifier, and realizes high maintaining voltage and acceptable trigger voltage value through the blocking of the isolating ring formed by the high-concentration buried layer and the deep injection layer, thereby avoiding the latch-up effect; the adjustment of the lowest point maintaining voltage can be realized by adjusting the number of the isolation rings, and the latch-up effect caused by electrostatic discharge ESD is well inhibited.
Drawings
Fig. 1 is a schematic structural diagram of a high-sustain voltage thyristor with an embedded isolation ring according to the present invention, in which an N-type isolation ring is disposed in the first embodiment.
Fig. 2 is a schematic structural diagram of the high-sustain voltage scr with an embedded isolation ring according to the present invention, in which three layers of N-type isolation rings are provided in the second embodiment.
Fig. 3 is a schematic structural diagram of the high-sustain voltage scr with an embedded isolation ring according to the present invention, in which a one-layer P-type isolation ring is disposed in the third embodiment.
Fig. 4 is a schematic structural diagram of the high-sustain voltage thyristor with an embedded isolation ring according to the present invention, in which three P-type isolation rings are provided in the fourth embodiment.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
The utility model provides a with the scheme of the interior embedding of cage in the silicon controlled rectifier, the cage is used for integrated circuit's isolation usually rather than being used for inside the device, the utility model provides an inside introducing the silicon controlled rectifier device with the cage, be used for improving the minimum holding voltage of silicon controlled rectifier to prevent latch-up's production. The utility model provides an isolator that uses in the silicon controlled rectifier can only include N type isolator, can only include P type isolator, also can both include N type isolator and include P type isolator, in addition in a silicon controlled rectifier that contains N type isolator and/or P type isolator, N type isolator and/or P type isolator can only contain one deck isolator, also can contain multilayer isolator, explains in combination with five concrete embodiment below.
The first specific embodiment is as follows:
in this embodiment, an N-type isolation ring structure is adopted, and only one isolation ring layer is included. As shown in fig. 1, the thyristor with an embedded N-type isolation ring in this embodiment includes: the P-type substrate 21, the N-type well region 11, the P-type well region 12, an anode, a cathode, a third N + region 05, a first N-type deep injection layer (N-sink layer) 071, a second N-type deep injection layer (N-sink layer) 072 and an N buried layer (NBL layer) 09, wherein the N-type well region 11 and the P-type well region 12 are respectively arranged on the left side and the right side of the upper surface of the P-type substrate. In the present embodiment, the anode includes a first N + region 01 and a first P + region 02, the cathode includes a second N + region 03 and a second P + region 04, and the first N + region 01 and the first P + region 02 are disposed on the inner surface of the nwell region 11 in a tangential or separated relationship. The second N + region 03 and the second P + region 04 are disposed on the inner surface of the P well region 12 in a tangential or separated relationship. The first N + region 01 and the first P + region 02 are connected by a metal to form an anode of the entire device. The second N + region 03 and the second P + region 04 are connected through a metal to form a cathode of the entire device. The third N + region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third N + region are disposed inside the N-well region and the P-well region, respectively, that is, the left edge of the third N + region 05 is disposed inside the N-well region 11, and the right edge is disposed inside the P-well region 12, thereby forming a crossing. The first N-type deep implant layer 071 is located on the left side of the N-well region 11, and its right edge is tangent to the left edge of the N-well region 11. The second N-type deep implant layer 072 is located on the right side of the N-well region 11, and the left edge thereof is tangent to the right edge of the N-well region 11. Under the N well region 11, there is a buried N layer (NBL layer) 09, and the buried N layer 09 may be set to have the same length as the N well region 11 and a certain longitudinal thickness. The upper edge of the buried N layer 09 is tangent to the lower edge of the N well region 11, the left edge is tangent to the first N-type deep implant layer 071, and the right edge is tangent to the second N-type deep implant layer 072. All the above structures are made on a P-type substrate 21.
The second specific embodiment:
for an N-type isolation ring, if the power supply voltage to be protected is high and a single-layer isolation ring cannot meet the Vh requirement, a multiple isolation ring mode may be adopted. In this embodiment, two third N-type deep implanted layers 0721 and 0722 are further disposed in the region between the anode and the third N + region 05 to form a three-layer N-type isolation ring. As shown in fig. 2, the thyristor with three layers of embedded N-type isolation rings in this embodiment includes: the buried layer structure comprises a P-type substrate 21, an N-well region 11, a P-well region 12, an anode, a cathode, a third N + region 05, a first N-type deep injection layer (N-sink layer) 071, a second N-type deep injection layer (N-sink layer) 072, two third N-type deep injection layers 0721 and 0722 and an N buried layer (NBL layer) 09, wherein the anode also comprises a first N + region 01 and a first P + region 02 in the embodiment, and the cathode also comprises a second N + region 03 and a second P + region 04. The N-well region 11 and the P-well region 12 are disposed on the left and right sides of the upper surface of the P-type substrate, respectively. The first N + region 01 and the first P + region 02 are designed on the inner surface of the N-well 11 in a tangential or separated relationship. The second N + region 03 and the second P + region 04 are disposed on the inner surface of the P well region 12 in a tangential or separated relationship. The first N + region 01 and the first P + region 02 are connected by a metal to form an anode of the entire device. The second N + region 03 and the second P + region 04 are connected through a metal to form a cathode of the entire device. The third N + region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third N + region are disposed inside the N-well region and the P-well region, respectively, that is, the left edge of the third N + region 05 is disposed inside the N-well region 11, and the right edge is disposed inside the P-well region 12, thereby forming a crossing.
The specific structure of the three layers of N-type isolation rings in this embodiment is: the first N-type deep implant layer 071 is located on the left side of the N-well region 11, and its right edge is tangent to the left edge of the N-well region 11. The second N-type deep implant layer 072 is located on the right side of the N-well region 11, and the left edge thereof is tangent to the right edge of the N-well region 11. Two third N-type deep injection layers 0721 and 0722 are arranged in the N well region 11 and in a region between the anode and the third N + region 05, the third N-type deep injection layer 0722 is positioned inside the N well region 11 on the left side of the second N-type deep injection layer 072, the third N-type deep injection layer 0721 is positioned inside the N well region 11 on the left side of the third N-type deep injection layer 0722, the third N-type deep injection layer 0721 separates the N well regions 11 on the left side and the right side from the N buried layer 09, and the third N-type deep injection layer 0722 separates the N well regions 11 on the left side and the right side from the N buried layer 09. An N buried layer 09 exists under the N well region 11, and the N buried layer 09 may be provided to have the same length as the N well region 11 and have a certain longitudinal thickness. The upper edge of the N buried layer 09 is tangent to the lower edge of the N well region 11, the left edge of the N buried layer is tangent to the right edge of the first N-type deep injection layer 071, the right edge of the N buried layer is tangent to the second N-type deep injection layer 072, the middle of the N buried layer 09 is separated by two third N-type deep injection layers 0721 and 0722, and all the structures are manufactured on the P-type substrate 21.
In this embodiment, the first N-type deep implanted layer 071, the N buried layer 09, and the third N-type deep implanted layer 0721 form a first N-type isolation ring, the first N-type deep implanted layer 071, the N buried layer 09, and the third N-type deep implanted layer 0722 form a second N-type isolation ring, and the first N-type deep implanted layer 071, the N buried layer 09, and the second N-type deep implanted layer 072 form a third N-type isolation ring.
The third concrete implementation scheme is as follows:
since the lowest point sustain voltage Vh of the device strongly depends on the concentration of the inner NW and PW regions, and for some processes, the P-type isolation ring has higher concentration and smaller layout rule, the improvement of the structure Vh can also be improved by the optimized change of the P-type isolation ring and PBL layer to the PNP electric field.
As shown in fig. 3, a thyristor structure using a P-type isolation ring is illustrated, and this embodiment takes a layer of P-type isolation ring as an example, and includes: the P-type substrate 21, the N-well region 11, the P-well region 12, the anode, the cathode, the third N + region 05, the first P-type deep implantation layer (P-sink layer) 081, the second P-type deep implantation layer (P-sink layer) 082, and the P buried layer (PBL layer) 10, in this embodiment, the anode also includes the first N + region 01 and the first P + region 02, and the cathode also includes the second N + region 03 and the second P + region 04. The N well region 11 and the P well region 12 are respectively arranged on the left side and the right side of the upper surface of the P type substrate, and the first N + region 01 and the first P + region 02 are designed on the inner surface of the N well region 11 and are in a tangential or separated position relation. The second N + region 03 and the second P + region 04 are disposed on the inner surface of the P well region 12 in a tangential or separated relationship. The first N + region 01 and the first P + region 02 are connected by a metal to form an anode of the entire device. The second N + region 03 and the second P + region 04 are connected through a metal to form a cathode of the entire device. The third N + region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third N + region are disposed inside the N-well region and the P-well region, respectively, that is, the left edge of the third N + region 05 is disposed inside the N-well region 11, and the right edge is disposed inside the P-well region 12, thereby forming a crossing. The first P-type deep implant layer 081 is located on the left side of the P-well region 12, and the right edge of the first P-type deep implant layer is tangent to the left edge of the P-well region 12. The second P-type deep implant layer 082 is located on the right side of the P-well region 12, and has a left edge tangent to a right edge of the P-well region 12. Below P-well region 12, P buried layer 10 is present, and P buried layer 10 may be set to have the same length as P-well region 12 and a certain longitudinal thickness. The upper edge of the P buried layer 10 is tangent to the lower edge of the P well region 12, the left edge is tangent to the first P-type deep implant layer 081, and the right edge is tangent to the second P-type deep implant layer 082. All the above structures are made on a P-type substrate 21.
The fourth specific embodiment:
for the P-type isolation ring, if the power supply voltage to be protected is high and the single-layer P isolation ring cannot meet the Vh requirement, a multiple isolation ring mode may be adopted. In this embodiment, two third P-type deep implantation layers 0811 and 0812 are further disposed in the region between the cathode and the third N + region 05 to form a three-layer P-type isolation ring. As shown in fig. 4, the thyristor with three layers of P-type isolation rings embedded therein in this embodiment includes: the P-type substrate 21, the N-well region 11, the P-well region 12, the anode, the cathode, the third N + region 05, the first P-type deep implantation layer (P-sink layer) 082, the second P-type deep implantation layer (P-sink layer) 081, the two third P-type deep implantation layers 0811 and 0812, and the P buried layer (PBL layer) 10, in this embodiment, the anode also includes the first N + region 01 and the first P + region 02, and the cathode also includes the second N + region 03 and the second P + region 04. The N well region 11 and the P well region 12 are respectively arranged on the left side and the right side of the upper surface of the P type substrate, and the first N + region 01 and the first P + region 02 are designed on the inner surface of the N well region 11 and are in a tangential or separated position relation. The second N + region 03 and the second P + region 04 are disposed on the inner surface of the P well region 12 in a tangential or separated relationship. The first N + region 01 and the first P + region 02 are connected by a metal to form an anode of the entire device. The second N + region 03 and the second P + region 04 are connected through a metal to form a cathode of the entire device. The third N + region 05 is disposed on the upper surface of the P-type substrate 21, and two ends of the third N + region are disposed inside the N-well region and the P-well region, respectively, that is, the left edge of the third N + region 05 is disposed inside the N-well region 11, and the right edge is disposed inside the P-well region 12, thereby forming a crossing.
The specific structure of the three layers of P-type isolating rings in this embodiment is as follows: the second P-type deep implant layer 081 is located at the left side of the P-well region 12, and the right edge of the second P-type deep implant layer is tangent to the left edge of the P-well region 12. The first P-type deep implant layer 082 is located on the right side of the P-well region 12, and has a left edge tangent to a right edge of the P-well region 12. Two third P-type deep injection layers 0811 and 0812 are disposed in the P-well region 12 between the cathode and the third N + region 05, and the third P-type deep injection layer 0811 is located inside the P-well region 12 on the right side of the second P-type deep injection layer 081. The third P-type deep implant layer 0812 is located inside the P-well region 12 on the right side of the third P-type deep implant layer 0811. The third P-type deep implantation layer 0811 separates the P-well region 12 and the P buried layer 10 on the left and right sides thereof, and the third P-type deep implantation layer 0812 separates the P-well region 12 and the P buried layer 10 on the left and right sides thereof. Below P-well region 12, P buried layer 10 is present, and P buried layer 10 may be set to have the same length as P-well region 12 and a certain longitudinal thickness. The upper edge of the P buried layer 10 is tangent to the lower edge of the P well region 12, the left edge is tangent to the second P-type deep implantation layer 081, the right edge is tangent to the first P-type deep implantation layer 082, and the middle part is separated by two third P-type deep implantation layers 0811 and 0812. All the above structures are made on a P-type substrate 21.
Similarly, in this embodiment, the first P-type deep implantation layer 082, the P buried layer 10 and the third P-type deep implantation layer 0812 form a first P-type isolation ring, the first P-type deep implantation layer 082, the P buried layer 10 and the third P-type deep implantation layer 0811 form a second P-type isolation ring, and the first P-type deep implantation layer 082, the P buried layer 10 and the second P-type deep implantation layer 081 form a third P-type isolation ring.
The fifth concrete embodiment:
in combination with four above embodiments, the utility model provides a silicon controlled rectifier of embedded isolating ring can also set up one deck or multilayer N type isolating ring and P type isolating ring simultaneously in same device, the silicon controlled rectifier device that contains N type isolating ring and P type isolating ring simultaneously includes P type substrate 21, N well region 11, P well region 12, the anode, the cathode, third N + district 05, first P type deep injection layer 082, second P type deep injection layer 081, P buried layer 10, first N type deep injection layer 071, second N type deep injection layer 072, N buried layer 09, if for multilayer isolating ring structure still including set up in P well region 12 and be located a plurality of third P type deep injection layers of negative pole and third N + district 05 between regional and set up in N well region 11 and be located a plurality of third N type deep injection layers of region between anode and the third N + district 05.
To sum up, the utility model provides a silicon controlled rectifier SCR device that has embedded isolating ring structure for ESD protection, the isolating ring that constitutes through high concentration buried layer and deep injection layer is to the influence of big injection into electric field down, has realized the latch-up ESD protection of high Vh. Meanwhile, the Vh voltage can be adjusted by adjusting the number of the isolation rings, and the latch-up effect caused by ESD is well inhibited. The utility model discloses an aspect has realized that the technology of device in integrated circuit is compatible, and on the other hand has realized holding voltage's controllability, consequently, the specially adapted high voltage integrated circuit ESD protection engineering.
Those skilled in the art can make various other specific modifications and combinations based on the teachings of the present invention without departing from the spirit of the invention, and such modifications and combinations are still within the scope of the invention.
Claims (4)
1. A high-sustain voltage thyristor with an embedded isolation ring, comprising:
a P-type substrate;
the N well region and the P well region are arranged on two sides of the upper surface of the P type substrate;
the anode is arranged on the inner surface of the N well region;
the cathode is arranged on the inner surface of the P well region;
the third N + region is arranged on the upper surface of the P-type substrate, and two ends of the third N + region are respectively arranged in the N well region and the P well region;
the silicon controlled rectifier is characterized by further comprising an N-type isolating ring and/or a P-type isolating ring;
the N-type isolating ring comprises:
an N buried layer disposed below the N well region;
the first N-type deep injection layer is arranged on one side, far away from the P well region, of the N well region and is in contact with the N well region and the N buried layer, and the first N-type deep injection layer is located on the upper surface of the P-type substrate;
the second N-type deep injection layer is arranged on one side, close to the P well region, of the N well region and is in contact with the N well region and the N buried layer, and the upper surface of the second N-type deep injection layer is in contact with the lower surface of the third N + region;
the P-type isolating ring comprises:
a P buried layer disposed below the P well region;
the first P-type deep injection layer is arranged on one side, far away from the N-well region, of the P-well region and is in contact with the P-well region and the P buried layer, and the first P-type deep injection layer is located on the upper surface of the P-type substrate;
and the second P-type deep injection layer is arranged on one side of the P well region close to the N well region and is in contact with the P well region and the P buried layer, and the upper surface of the second P-type deep injection layer is in contact with the lower surface of the third N + region.
2. The high-sustain voltage thyristor with embedded isolation ring according to claim 1, wherein the region between the anode and the third N + region in the N-well region further comprises a plurality of third N-type deep implants for separating the N-well region and the N-buried layer on both sides thereof.
3. The high-sustain voltage thyristor with embedded isolation ring according to claim 1 or 2, wherein the region in the P-well region between the cathode and the third N + region further comprises a plurality of third P-type deep implants for separating the P-well region and the P buried layer on both sides thereof.
4. The high-sustain voltage thyristor with an embedded isolation ring according to claim 1, wherein the anode comprises a first N + region and a first P + region disposed on an upper surface of the nwell region and connected by a metal, and the cathode comprises a second N + region and a second P + region disposed on an upper surface of the P well region and connected by a metal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459594A (en) * | 2019-08-29 | 2019-11-15 | 成都矽能科技有限公司 | A kind of embedded isolation ring can be used for electrostatic leakage protection is silicon-controlled |
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2019
- 2019-08-29 CN CN201921418257.3U patent/CN210092089U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459594A (en) * | 2019-08-29 | 2019-11-15 | 成都矽能科技有限公司 | A kind of embedded isolation ring can be used for electrostatic leakage protection is silicon-controlled |
| CN110459594B (en) * | 2019-08-29 | 2024-04-12 | 成都矽能科技有限公司 | Embedded isolation ring silicon controlled rectifier capable of being used for electrostatic discharge protection |
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