JP5022013B2 - Semiconductor device for electrostatic protection and compound IC for automobile - Google Patents

Description

  The present invention relates to a semiconductor device for electrostatic protection for protecting an integrated circuit or the like from static electricity, and more particularly to a device having an SCR structure.

  Automotive ICs are being integrated with analog and digital control circuits, power MOS for drivers, etc., and the operating voltage is configured to support multiple voltages such as battery voltage system and several V voltage system. ing. Such an automobile IC is called a composite IC, and has a structure in which a bipolar element, a CMOS element, a lateral power MOS, and the like are formed in the same IC substrate.

  A composite IC for an automobile is required to operate normally under a severe on-vehicle environment to which a surge or noise is applied. For this reason, the tendency to manufacture using an SOI substrate in which circuit elements are completely dielectrically separated is increasing. In addition, automotive ICs have strict withstand voltage standards against electrostatic breakdown, and usually require a guarantee against a very high electrostatic withstand voltage of 15 kV to 25 kV.

  Generally, a diode is used for ESD (electrostatic discharge) protection of an input terminal as described in Patent Documents 1 and 2 and the like. FIG. 9 is a diagram showing a surface type diode as an ESD protection element formed on a conventional SOI substrate. This is a structure in which a plurality of p-type diffusion regions and n-type diffusion regions are alternately arranged at regular intervals on the surface of the semiconductor substrate. The formation of the p-type diffusion region and the n-type diffusion region often uses a process for forming a p-well diffusion layer and an n-well diffusion layer having a CMOS structure.

  On the other hand, an ESD protection element having an SCR (thyristor) structure can also be formed by using the p-type diffusion region and the n-type diffusion region, and Patent Documents 3 to 5 show examples of the structure. When a latch-up operation occurs, the SCR element has a very low internal resistance and can drive a large current, so that an element with excellent ESD withstand voltage performance can be realized. Such an ESD protection element having an SCR structure has a holding voltage of several volts at the time of latch-up, and is mainly applied to a fine MOS integrated circuit.

In addition, the operating voltage design range of the ESD protection element in the IC for automobiles is that the battery power supply system circuit generally operates within the range of the lower limit voltage of 20V or more in consideration of the voltage fluctuation margin of the input signal in the 16V battery voltage value. Is required. Although the upper limit voltage depends on the input resistance to the internal circuit and the withstand voltage at the internal circuit input portion, it is generally desirable that the upper limit voltage be as low as possible, and operation is required in a voltage range of 100 V or less at the highest. Regarding the operating voltage of the ESD protection element, in the surface type diode of FIG. 9, the operation start voltage value is determined by setting the interval between the p-type diffusion region and the n-type diffusion region within an appropriate range.
JP 2003-224133 A JP 2005-203738 A JP 2002-94001 A JP-A-2005-79287 JP 2006-74012 A

  However, in the diode element having the structure as shown in FIG. 9, since the distance between the p-type diffusion region and the n-type diffusion region is the shortest at the outermost surface portion of the semiconductor substrate, the electric field is most concentrated at the opposite outermost surface end portions. In addition, since the surge current during the ESD protection operation concentrates and flows near the outermost surfaces of the p-type diffusion region and the n-type diffusion region, a hot spot due to current concentration occurs. For this reason, it is difficult to obtain a high ESD withstand voltage. Therefore, in order to achieve the ESD withstand voltage standard required for automotive ICs, an element having a diode junction having an overall length of several tens of mm is required. For example, when a p-type diffusion region and an n-type diffusion region are formed in a strip-shaped pattern with a side length of 500 μm, about 50 sets of diode patterns need to be connected in parallel. In such a large-scale diode element, the wiring resistance cannot be ignored, and it is not easy to design the wiring so that the entire device operates uniformly during ESD. As a result, it becomes difficult to obtain the ESD withstand voltage as designed. Further, such a surface type diode element has a relatively large operating resistance, which is also a factor that makes it difficult to obtain a high ESD withstand voltage.

  As described above, in the diode element having the structure in which the p-type diffusion region and the n-type diffusion region are opposed to each other as shown in FIG. 9, only the end portion of the diffusion region functions as an ESD operation portion, and thus has an essentially high ESD withstand voltage. Therefore, it is difficult to obtain a large-scale diode element having a total length of several tens of millimeters.

  In addition, the SCR element is ideal as an ESD protection element because it has a very high ESD withstand voltage performance compared to the surface diode, but the holding voltage at the time of latch-up is several volts, which is higher than the power supply voltage in the automotive IC. It is low and difficult to apply as an ESD protection element for automotive ICs.

  SUMMARY OF THE INVENTION An object of the present invention is to realize a novel SCR type electrostatic protection semiconductor device having a high holding voltage and a high ESD withstand voltage performance, and to realize an electrostatic protection semiconductor device applicable as an ESD protection element for an automotive IC. That is.

According to a first aspect of the present invention, there is provided an electrostatic protection semiconductor device that is electrically isolated from other elements and prevents electrostatic breakdown of the other elements. A first conductive type main semiconductor region having a lower carrier concentration than the buried region, a first conductive type first diffusion region formed on the surface of the main semiconductor region, and a first diffusion region formed on the region; A first conductivity type first electrode formation region, a second conductivity type second electrode formation region, a first electrode formation region and a second electrode formation region formed on the surface of the diffusion region; a first electrode to be connected, and the first diffusion region formed in the distant region, and a second diffusion region of the second conductivity type, formed on the surface of the second diffusion region, a first conductivity A third electrode forming region of the mold, and a fourth electrode forming region of the second conductivity type; 3 and the second electrode connected to the fourth electrode formation region, the first diffusion region and the second diffusion region include the first diffusion region, the second diffusion region, and the second diffusion region. When the voltage is applied so that the first electrode has a positive operating voltage with respect to the second electrode, a depletion layer extending from the second diffusion region to the buried region is formed. When a voltage is applied so that the second electrode has a positive operating voltage with respect to the first electrode, a depletion layer extending from the first diffusion region to the buried region is formed. This is a semiconductor device for electrostatic protection.

According to a second aspect of the present invention, there is provided an electrostatic protection semiconductor device that is electrically isolated from other elements and prevents electrostatic breakdown of the other elements. A first conductive type main semiconductor region having a lower carrier concentration than the buried region, a first conductive type first diffusion region formed on the surface of the main semiconductor region, and a first diffusion region formed on the region; A first conductivity type first electrode formation region, a second conductivity type second electrode formation region, a first electrode formation region and a second electrode formation region formed on the surface of the diffusion region; The first conductive layer formed on the surface of the second diffusion region and the second diffusion region of the second conductivity type formed in a region away from the first electrode to be connected and the first diffusion region. A third electrode forming region of the mold, and a fourth electrode forming region of the second conductivity type; 3, and a second electrode connected to the fourth electrode formation region, and the first diffusion region and the second diffusion region are the first diffusion region and the second diffusion region, respectively. And an extension region in a direction opposite to the first diffusion region and a length of the extension region in a direction opposite to the second diffusion region, and from the buried region to the first diffusion region and the second diffusion region. The electrostatic protection semiconductor device is characterized in that a holding withstand voltage is determined by a distance in a vertical direction.

According to a third aspect of the present invention, there is provided an electrostatic protection semiconductor device that is electrically isolated from other elements and prevents electrostatic breakdown of the other elements. A first conductive type main semiconductor region having a lower carrier concentration than the buried region, a first conductive type first diffusion region formed on the surface of the main semiconductor region, and a first diffusion region formed on the region; A first conductivity type first electrode formation region, a second conductivity type second electrode formation region, a first electrode formation region and a second electrode formation region formed on the surface of the diffusion region; The first conductive layer formed on the surface of the second diffusion region and the second diffusion region of the second conductivity type formed in a region away from the first electrode to be connected and the first diffusion region. A third electrode forming region of the mold, and a fourth electrode forming region of the second conductivity type; 3, and a second electrode connected to the fourth electrode formation region, and the first diffusion region and the second diffusion region are the first diffusion region and the second diffusion region, respectively. The extension region in the opposing direction of the first diffusion region and the second diffusion region has a length from the buried region to the first diffusion region and the second diffusion region. It is a semiconductor device for electrostatic protection, characterized in that it is longer than the distance in the vertical direction by 4 μm or more.

  According to the configuration of the first to third inventions, a transistor is formed in the vertical direction by the first electrode formation region, the first diffusion region, and the main semiconductor region, and the third electrode formation region and the second diffusion region are formed. A transistor is formed in the vertical direction by the main semiconductor region, and a transistor is formed in the horizontal direction by the first diffusion region, the main semiconductor region, and the second diffusion region. Therefore, the semiconductor device for electrostatic protection according to the first invention has a bidirectional SCR structure. Since there is no polarity, if one is the anode side, the other is the cathode side.

  The first electrode formation region and the second electrode formation region may be separated or in contact with each other through the first diffusion region or the insulating film. However, if they overlap each other, the holding withstand voltage decreases, which is not desirable. The same applies to the third electrode formation region and the fourth electrode formation region. In particular, as in the third aspect of the invention, the first electrode formation region and the third electrode formation region are disposed on the inner side facing each other, and the second electrode formation region and the fourth electrode formation region are disposed on the outer side. When arranged, the first electrode formation region, the first diffusion region, the vertical transistor by the main semiconductor region, and the third electrode formation region, the second diffusion region, the vertical transistor by the main semiconductor region, Since it is formed inside, resistance is further reduced, which is desirable.

  The extension region is a part of the region of the first or second diffusion region, and the first electrode formation region and the second electrode formation region, or the third electrode formation region and the fourth electrode on the surface thereof. The electrode forming region is a region extending in the lateral direction where no electrode forming region is formed. The length in the opposing direction of the extension region of the first diffusion region and the length in the opposing direction of the extension region of the second diffusion region need not be equal, but if they are equal, the electrostatic protection semiconductor device of the present invention is symmetrical. It is possible to make the structure, and the same one is desirable from the viewpoint of the ease of layout of the planar pattern.

The semiconductor device for electrostatic protection and other elements may be separated by a bottom insulating film and a side insulating film, or pn isolation. In the case of isolation by an insulating film, the buried region is formed on the bottom insulating film.

  When an electrostatic surge is applied to the first electrode or the second electrode of the semiconductor device for electrostatic protection according to the present invention, either the first or second diffusion region corresponding to the base of the transistor is in a reverse bias state. Then, the depletion layer spreads mainly under the extension region and reaches the interface between the buried region and the main semiconductor region. Electrically, the first or second diffusion region acting as the base layer has a structure extending to the interface between the buried region and the main semiconductor region. This electrically spread base layer holds the voltage. In addition, a strong electric field concentration occurs at this interface, and a large amount of electrons and holes are generated, so that an electrically spread base layer is maintained. For the above reasons, the electrostatic protection semiconductor device of the present invention has high holding voltage characteristics.

  By adjusting the length of the extension region and the longitudinal distance, an electrostatic protection semiconductor device having desired holding withstand voltage characteristics can be obtained.

In particular, as in the third and fourth inventions , if the extension region is a semiconductor device for electrostatic protection whose length is 4 μm or more longer than the longitudinal distance, the DC breakdown voltage (operation start when a voltage is applied to the electrostatic protection semiconductor device) High voltage holding voltage characteristics can be obtained.

  The longitudinal distance is preferably in the range of 2 μm to 10 μm. If the thickness is 2 μm or less, the first and second diffusion regions and the buried region are close to each other, and the withstand voltage of the electrostatic protection semiconductor device is lowered, which is not desirable. Further, when it is 10 μm or more, when the present invention is applied to an electrostatic protection circuit of an automotive IC, it is necessary for forming other vertical bipolar elements included in the automotive IC formed on the same substrate. The collector sink region reaching the buried region is required to be 10 μm or more, and the impurity diffusion time for forming the region is significantly increased, which is not desirable. More desirably, it is in the range of 4 μm to 8 μm.

  The relationship between the length of the extension region and the longitudinal distance is preferably as follows. The length of the extension region is preferably in the range of (vertical distance +4) μm to (vertical distance +14) μm. (Vertical distance +4) μm or less is not desirable because a high holding voltage cannot be obtained. In addition, when (vertical distance +14) μm or more, a high holding breakdown voltage can be obtained, but it is desirable because the operation of the transistor in the vertical direction becomes strong, the ESD breakdown voltage performance is lowered, and the element size becomes large. Absent. More desirably, it is in the range of (vertical direction distance + 6) μm to (vertical direction distance + 10) μm.

According to a fifth invention, in the first invention to the fourth invention, the first electrode formation region and the third electrode formation region are arranged inside each other, and the second electrode formation region and the fourth electrode are arranged. A semiconductor device for electrostatic protection, characterized in that a formation region is arranged outside thereof.
According to a sixth invention, in the first to fifth inventions, the operation start voltage is determined by a separation distance between the first diffusion region and the second diffusion region. Device.

  When the separation distance is 4 μm or less, the leakage current due to punch-through between the first diffusion region and the second diffusion region increases, and when the separation distance is 10 μm or more, the operating voltage becomes 100 V or more, which is not desirable. Therefore, when the electrostatic protection semiconductor device of the present invention is applied to an automotive IC, the separation distance is desirably in the range of 4 μm to 10 μm. Most desirable is 5 μm.

  In a seventh aspect based on the first to sixth aspects, the planar pattern of the first diffusion region and the second diffusion region is a strip shape, a track shape, a ring shape, or a composite shape thereof. A semiconductor device for electrostatic protection characterized by the following.

  In an eighth aspect based on the first aspect to the seventh aspect, the first diffusion region and the second diffusion region are divided into a plurality of sets, and the plurality of first diffusion regions are arranged via the first electrode. And a plurality of second diffusion regions are electrically connected to each other through a second electrode.

  A ninth invention is characterized in that, in the first to eighth inventions, one of the first electrode and the second electrode is connected to an input terminal, and the other is connected to a ground electrode. This is a semiconductor device for electrostatic protection. According to this configuration, since the surge current flows to the ground electrode through the semiconductor device for electrostatic protection according to the present invention, other semiconductor devices can be protected from ESD.

  A tenth invention is characterized in that, in the first to ninth inventions, the bottom surface and the side surface are partitioned by the bottom surface insulating film and the side surface insulating film, and are electrically insulated from other elements. This is a semiconductor device for electrostatic protection.

  An eleventh invention is the semiconductor device for electrostatic protection according to any one of the first to tenth inventions, wherein the main semiconductor region is an SOI substrate.

A twelfth aspect of the invention is a composite IC for automobiles including the electrostatic protection semiconductor device according to the first to eleventh aspects of the invention.

  In the structure of the electrostatic protection semiconductor device according to any one of the first to third inventions, the first and second diffusion regions acting as the base layer of the transistor are provided with extension regions, and a bidirectional SCR having a high carrier concentration buried region. It has a structure. Therefore, the semiconductor device for electrostatic protection has high holding voltage characteristics. Moreover, since it is a SCR structure, it has high ESD pressure | voltage resistant performance.

Further, as in the second invention , by adjusting the length of the extension region and the longitudinal distance, an electrostatic protection semiconductor device having desired holding withstand voltage characteristics can be realized. In particular, as in the third and fourth inventions , when the length of the extension region is set to a value longer than the longitudinal distance by 4 μm or more, a holding voltage characteristic as high as a DC breakdown voltage can be obtained, which is suitable for an automotive IC. A semiconductor device for electrostatic protection having a holding withstand voltage characteristic is obtained.

  Further, as in the sixth aspect of the invention, an electrostatic protection semiconductor device having a desired operation start voltage value can be realized by adjusting the separation distance between the first diffusion region and the second diffusion region.

  Further, by adopting a planar layout pattern as in the seventh invention, an efficient and small electrostatic protection semiconductor device can be formed. As in the eighth invention, the first diffusion region and the second diffusion region are formed. By dividing, the degree of freedom of the planar layout pattern is increased, which can be made more efficient.

  Further, as in the tenth aspect, partitioning the element region with an insulating film can suppress the leakage current and improve the withstand voltage performance. Furthermore, as in the eleventh aspect of the present invention, when an SOI substrate is used, the electrostatic protection semiconductor device of the present invention can be easily formed.

  As described above, according to the present invention, an electrostatic protection semiconductor device suitable for use in an automotive IC can be realized. Since the structure of the present invention can be used for forming the p-well diffusion layer and the n-well diffusion layer of the CMOS structure of the composite IC for automobiles, manufacturing by incorporating the semiconductor device for electrostatic protection of the present invention into the composite IC for automobiles. There is no increase in cost.

  Hereinafter, specific examples of the present invention will be described with reference to the drawings. However, the present invention is not limited to the examples.

  FIG. 1 is a diagram showing a structure of a bidirectional SCR type electrostatic protection semiconductor device formed on an SOI substrate of Example 1, and FIG. 2 is a diagram showing a planar layout pattern thereof. The structure of this electrostatic protection semiconductor device will be described below.

The element region has a buried insulating film 11 (corresponding to the bottom insulating film of the present invention) formed on the p-type support substrate 10 on the bottom surface, and a trench insulating film 14 (corresponding to the side insulating film of the present invention) on the side surface. It is partitioned by a silicon film 15 (corresponding to the side insulating film of the present invention), and is isolated from other elements to be protected from static electricity. The element region includes a buried n ⁺ type region 12 (corresponding to the buried region of the present invention) on the buried insulating film 11 and an n ⁻ type semiconductor substrate 13 (corresponding to the main semiconductor region of the present invention) formed on the upper surface thereof. ). The impurity concentration in the vicinity of the buried insulating film 11 in the buried n ⁺ -type region 12 is 3 × 10 ¹⁹ / cm ³ , and the impurity concentration of the n ⁻ -type semiconductor substrate 13 is 1 × 10 ¹⁵ / cm ³ . A buried n ⁺ -type region 12 n ^- interface type semiconductor substrate 13, the impurity concentration of the buried n ⁺ -type region 12, n ^- impurity concentration type semiconductor substrate 13 is defined as the plane at equal positions. The desirable impurity concentration range of the buried n ⁺ -type region 12 is 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²⁰ / cm ³ , and the desirable impurity concentration range of the n ⁻ -type semiconductor substrate 13 is 1 × 10 ¹⁴ / cm ^3. cm ³ to 1 × 10 ¹⁶ / cm ³ .

The buried n ⁺ type region 12 was formed by diffusing impurities from the surface of the n ⁻ type semiconductor substrate 13. Thereafter, the surface of the p-type support substrate 10 is oxidized to form a buried insulating film 11, and the buried n ⁺ -type region 12 and the buried insulating film 11 are bonded and bonded. Next, a trench groove was formed in order to partition the element region, the trench groove side surface was oxidized to form a trench insulating film 14, and a polysilicon film 15 was formed inside the trench groove.

An anode p-type region 20 (corresponding to the first diffusion region of the present invention) is formed on the surface portion of the n ⁻ -type semiconductor substrate 13, and an anode p ⁺ -type region 16 (of the present invention on the left side) is formed on the surface. An anode n ⁺ -type region 17 (corresponding to the first electrode formation region of the present invention) is formed on the right side and is close to each other. In addition, a cathode p-type region 21 (corresponding to the second diffusion region of the present invention) is formed on the surface of the n ⁻ -type semiconductor substrate 13 and in a region away from the anode p-type region 20. Has a cathode p ⁺ -type region 18 (corresponding to a fourth electrode formation region of the present invention) on the right side and a cathode n ⁺ -type region 19 (third electrode formation region of the present invention) on the left side, which are close to each other. ing. The anode n ⁺ -type region 17 and the cathode n ⁺ -type region 19 face each other on the inner side (close side), and the anode p ⁺ -type region 16 and the cathode p ⁺ -type region 18 face each other on the outer side (the far side). Yes. The anode p-type region 20 and the cathode p-type region 21 were formed by diffusing impurities from the surface of the n ⁻ type semiconductor substrate 13.

The anode p-type region 20 and the cathode p-type region 21 have an opposing side 20b (where the anode p-type region 20 is closest to the cathode p-type region 21) and an opposing side 21b (of the cathode p-type region 21). , Where the distance from the anode p-type region 20 is the shortest). The anode p-type region 20 and the cathode p-type region 21 include extension regions 20 a and 21 a having a length Lp in the opposing direction, and the extension region 20 a includes the anode p ⁺ -type region 16 and the anode n ⁺ -type region 17. The extension region 21 a does not include the cathode p ⁺ type region 18 and the cathode n ⁺ type region 19. In addition, the vertical distance from the lower surfaces 20c and 21c of the anode p-type region 20 and the cathode p-type region 21 to the interface between the buried n ⁺ -type region 12 and the n ⁻ -type semiconductor substrate 13 is Ly. Here, the length of the extended region 20a is defined by the length from the end 17a (the side end close to the cathode p-type region 21) in the inner direction of the anode n ⁺ -type region 17 to the opposite side 20b. Similarly, the length of the extension region 21a is defined by the length from the end 19a in the inner direction of the cathode n ⁺ -type region 19 (side end side close to the anode p-type region 20) to the opposing side 21b.

The depth from the surface of the anode p ⁺ type region 16, the anode n ⁺ type region 17, the cathode p ⁺ type region 18, and the cathode n ⁺ type region 19 is 0.5 μm, and the anode p type region 20 and the cathode p type region 21. The depth from the surface is 1.5 μm. The impurity concentration of the anode p-type region 20 and the cathode p-type region 21 is 3 × 10 ¹⁷ / cm ³ .

A LOCOS insulating film 22 is formed outside the electrode formation region on the surface portion of the n ⁻ type semiconductor substrate 13, and an interlayer insulating film 23 is formed on the LOCOS insulating film 22. Contact holes are formed in the interlayer insulating film 23 above the anode p ⁺ -type region 16 and the anode n ⁺ -type region 17, and above the cathode p ⁺ -type region 18 and the cathode n ⁺ -type region 19. An anode electrode 24 connected to the anode p ⁺ -type region 16 and the anode n ⁺ -type region 17 (corresponding to the first electrode of the present invention), a cathode electrode connected to the cathode p ⁺ -type region 18 and the cathode n ⁺ -type region 19 25 (corresponding to the second electrode of the present invention) is formed.

With the above configuration, the npn transistor 1 is formed in the vertical direction by the anode n ⁺ type region 17, the anode p type region 20, and the n ⁻ type semiconductor substrate 13 on the anode side, and the cathode n ⁺ on the cathode side. The npn-type transistor 2 is formed in the vertical direction by the type region 19, the cathode p-type region 21, and the n ⁻ -type semiconductor substrate 13, and the anode p-type region 20, the n ⁻ -type semiconductor substrate 13, and the cathode p-type region 21 by the horizontal direction. A pnp transistor 3 is formed in the direction. Therefore, as a whole, a bidirectional SCR structure is formed.

  When a positive ESD surge is applied to the anode electrode 24 of the electrostatic protection semiconductor device according to the first embodiment, the pnp type transistor 3 operates and a current flows through the cathode p type region 21, so that the npn type transistor 1 Operate. Even when a positive ESD surge is applied to the cathode electrode 25, the pnp transistor 3 operates, and a current flows through the anode p-type region 20, whereby the npn transistor 1 operates. Therefore, the trigger voltage is determined by the operation start voltage of the pnp transistor 3, that is, the distance L. Since the present invention is bipolar, the terms “anode” and “cathode” are used as a reference when a positive voltage is applied to the first electrode 24 with respect to the second electrode 25. Accordingly, even when the cathode electrode 25 is set to a positive potential with respect to the anode electrode 24, the pnp transistor 3 is naturally conducted and performs an electrostatic protection operation.

Next, a planar layout pattern of the electrostatic protection semiconductor device of Example 1 will be described with reference to FIG. The element region is doubled in a rectangular shape by the side surface insulating films 30 and 31 formed of the trench insulating film 14 and the polysilicon film 15, and is isolated from other elements. In the element region, an anode p-type region 20 and a cathode p-type region 21 are formed apart from each other in a rectangular shape. In the region of the anode p-type region 20, a strip-shaped anode p ⁺ -type region 16 and an anode n ⁺ -type region 17 are formed on the opposite side of the anode p-type region 20 and the cathode p-type region 21 from the opposite side 20 b side. An extension region 20a is formed on the opposite side 20b side. Similarly, a cathode p ⁺ type region 18, a cathode n ⁺ type region 19, and an extension region 21 a are formed in the region of the cathode p type region 21 to form a symmetrical layout pattern.

  In order to use the semiconductor device for electrostatic protection of Example 1 for an automotive IC, the lower limit of the operating voltage is required to be 20V or more. This is to prevent current from continuing to flow into the electrostatic protection semiconductor device due to the power supply voltage when the electrostatic protection semiconductor device is operated by mistake due to unforeseen noise. That is, in the SCR structure as in the first embodiment, the DC withstand voltage and the holding voltage need to be 20V or more. In addition, the ESD withstand voltage is required to be 15 kV to 25 kV or more. However, when the total length of the electrostatic protection semiconductor device is increased, it is difficult to operate uniformly due to the influence of wiring resistance, and the operating resistance is increased. It is desirable to be within a few mm. Therefore, the ESD withstand voltage of the semiconductor device for electrostatic protection needs to be 20 V / μm or more per unit anode length (width in the direction perpendicular to the paper surface of FIG. 1).

  The DC breakdown voltage is determined by the distance L between the anode p-type region 20 and the cathode p-type region 21. When L was 5 μm, the DC breakdown voltage was 65V. When L is 4 μm or less, the leakage current due to punch-through between the anode p-type region 20 and the cathode p-type region 21 increases, and when it is 10 μm or more, the DC withstand voltage becomes too high. Therefore, L is preferably in the range of 4 μm to 10 μm. Most desirable is 5 μm.

Next, the holding voltage will be considered. FIG. 3 shows an implementation in which L is 5 μm, Lp is 15 μm, Ly is 6 μm, and depth (width of the long sides of the rectangular anode p-type region 20 and cathode p-type region 21 in the planar layout pattern of FIG. 2) is 250 μm. The voltage-current characteristics of the electrostatic protection semiconductor device of Example 1 and the voltage-current characteristics of the electrostatic protection semiconductor device having a structure in which the embedded n ⁺ -type region 12 is eliminated from the electrostatic protection semiconductor device of Example 1 are shown. FIG. The structure of the first embodiment shows a high holding voltage characteristic even in a high current region. On the other hand, in the structure in which the buried n ⁺ -type region 12 is eliminated, the voltage is greatly reduced by the latch-up operation, and several V The holding voltage is. From the above, it can be seen that the buried n ⁺ -type region 12 is essential in order to obtain high holding voltage characteristics.

  Next, the relationship between Ly, Lp and the holding voltage will be considered. FIG. 4 shows the result of examining the relationship between the length of Lp and the holding voltage at the operating current 4A, with L being 5 μm and Ly being 6 μm. When the length of Lp is 10 μm or less, only a low holding voltage can be obtained. However, when the length is 10 μm or more, the holding voltage is almost constant, and a high holding voltage comparable to the DC withstand voltage can be obtained. Similarly, when the Ly was 4 μm and 2 μm, the Lp length was 8 μm or more when the Ly was 4 μm, and when the Ly was 2 μm, the Lp length was 6 μm or more and a high holding voltage could be obtained. all right. From the above results, it became clear that high holding voltage characteristics can be obtained when the length of Lp is (Ly + 4) μm or more. In addition, when the length of Lp is set to (Ly + 4) μm or more, it is also clear that the holding voltage decreases by 2 to 3 V every time Ly decreases by 1 μm.

Ly is preferably in the range of 2 μm to 10 μm. When the thickness is 2 μm or less, the anode p-type region 20 and the cathode p-type region 21 and the buried n ⁺ -type region 12 are close to each other, and the withstand voltage of the electrostatic protection semiconductor device is lowered. Further, when it is 10 μm or more, when the present invention is applied to an electrostatic protection circuit of an automotive IC, a buried region necessary for forming a vertical bipolar element included in the automotive IC formed on the same substrate A collector sink region that reaches 10 μm or more is required, and the impurity diffusion time for forming the region is significantly increased, which is not desirable.

  Lp is desirably in the range of (Ly + 4) μm to (Ly + 14) μm. If (Ly + 4) μm or less, a high holding voltage cannot be obtained, which is not desirable. In addition, a high holding voltage can be obtained at (Ly + 14) μm or more, but the operation of the npn transistors 1 and 2 in the vertical direction is strengthened, the ESD withstand voltage performance is lowered, and the element size is increased, which is desirable. Absent.

  FIG. 5 shows a simulation analysis result after ESD is applied to the electrostatic protection semiconductor device of the first embodiment. FIG. 5A shows the structure of the semiconductor device for electrostatic protection of Example 1 used for the simulation. L is 5 μm, Lp is 15 μm, and Ly is 6 μm. 5B and 5C show the potential distribution and space charge distribution after 50 nsec after the cathode electrode side is grounded and a positive ESD surge is applied to the anode electrode side.

From FIGS. 5B and 5C, it was found that the electrostatic protection semiconductor device of Example 1 had high holding voltage characteristics for the following reason. The cathode p-type region 21 is reverse-biased by the application of the ESD surge, and a depletion layer spreads mainly under the extension region 21 a of the cathode p-type region 21, and the interface between the buried n ⁺ -type region 12 and the n ⁻ -type semiconductor substrate 13. Reach up to. Electrically, the cathode p-type region 21 acting as a base layer has a structure extending to the interface between the buried n ⁺ -type region 12 and the n ⁻ -type semiconductor substrate 13. This electrically spread base layer holds the voltage. In addition, a strong electric field concentration occurs at this interface, and a large amount of electrons and holes are generated, so that an electrically spread base layer is maintained. As a result, high holding voltage characteristics can be obtained even in a large current region.

For the above reasons, the results of FIG. 3 can be explained as follows. Without the buried n ⁺ -type region 12, a region causing strong electric field concentration does not occur below the cathode p-type region 21, and the effect of generating a large amount of electrons and holes cannot be obtained. For this reason, it is not possible to maintain an electrically spread base layer. This is the reason why high holding voltage characteristics cannot be obtained without the embedded n ⁺ -type region 12. In addition, the longer the length Lp of the extension region 21a of the cathode p-type region 21 and the shorter the vertical distance Ly between the cathode p-type region 21 and the buried n ⁺ -type region 12, the greater the effect. As you can imagine, this is consistent with the results in FIG.

  Next, when the ESD withstand voltage of the semiconductor device for electrostatic protection of Example 1 in which L was 5 μm, Lp was 15 μm, and Ly was 6 μm was evaluated, it was 53 V / μm per unit anode length. This satisfies the condition of 20 V / μm or more required to be applied to an automotive IC, and has an ESD withstand voltage performance about 15 times higher than that of a conventional surface diode as shown in FIG. is there.

  As described above, the semiconductor device for electrostatic protection of the present invention has both high holding voltage characteristics and high ESD withstand voltage performance, and is a high-performance bidirectional type that can be applied as an ESD protection element for automotive ICs. It is a semiconductor device for electrostatic protection having an SCR structure.

  FIG. 6 is a diagram illustrating an example of a protection circuit configured using the electrostatic protection semiconductor device according to the first embodiment. The electrostatic protection semiconductor devices 100a and 100b according to the first embodiment are arranged between the input and VDD and between the input and VSS. VSS is grounded. With this configuration, the internal circuit is protected from ESD.

FIG. 7 is an example of another planar layout pattern of the electrostatic protection semiconductor device according to the first embodiment. The anode p-type region 20 and the cathode p-type region 21 are divided into a plurality of strip shapes and are arranged alternately. The plurality of anode p-type regions 20 and cathode p-type regions 21 are each provided with an extension region in the opposing direction, and have a strip-shaped anode p ⁺ -type region 16 and anode n ⁺ -type region 17 or cathode p ⁺ -type region 18. A cathode n ⁺ -type region 19 is formed in the region.

FIG. 8 is an example of another planar layout pattern of the semiconductor device for electrostatic protection according to the first embodiment. The anode p-type region 20 and the cathode p-type region 21 are formed in a square track shape with rounded corners. A square pad is formed inside the anode p-type region 20. In the region of the anode p-type region 20, an anode p ⁺ -type region 16 and an anode n ⁺ -type region 17 are formed in a square track shape with rounded corners, and an extension region is provided in the direction of the cathode p-type region 21. Similarly, the cathode p-type region 21 includes a cathode p ⁺ -type region 18 and a cathode n ⁺ -type region 19, and has an extended region in the direction of the anode p-type region 20. The anode p ⁺ type region 16, the anode n ⁺ type region 17, and the pad are connected to the anode electrode 24, and the cathode p ⁺ type region 18 and the cathode n ⁺ type region 19 are connected to the cathode electrode 25.

The present invention is not limited to an SOI substrate, but can also be applied to an epitaxial substrate. Instead of the trench insulating film 14 and the polysilicon film 15, the side surface may be separated by a p ⁺ type region, and the p type support A buried n ⁺ -type region 12 may be formed on the substrate 10. In this case, the buried n ⁺ -type region 12 also serves as an element isolation layer. Alternatively, an electrostatic protection semiconductor device having a structure in which n-type and p-type are interchanged may be used. In the embodiment, the lengths of the extension region 20a and the extension region 21a are both equal to Lp, but may be different. Further, the anode p ⁺ -type region 16 and the anode n ⁺ -type region 17 may overlap each other or may be separated from each other. However, if they overlap, the holding withstand voltage decreases, which is not desirable. The same applies to the cathode p ⁺ type region 18 and the cathode n ⁺ type region 19. In addition to the planar layout patterns shown in the first, third, and fourth embodiments, various planar layout patterns such as a ring shape and a lattice shape can be used.

  The present invention is effective as a semiconductor device for protecting an integrated circuit or the like from electrostatic breakdown. In particular, it is suitable as an ESD protection element for automotive ICs.

1 is a cross-sectional view illustrating a configuration of a semiconductor device for electrostatic protection according to a first embodiment. FIG. 3 is a diagram showing a planar layout pattern of the electrostatic protection semiconductor device of Example 1; The figure which shows a voltage-current characteristic. The figure which shows the relationship between the length of Lp, and holding voltage. The figure which shows the simulation analysis result after ESD application. FIG. 3 is a diagram illustrating a protection circuit configured using the electrostatic protection semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating another planar layout pattern of the electrostatic protection semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating another planar layout pattern of the electrostatic protection semiconductor device according to the first embodiment. Sectional drawing which showed the structure of the conventional surface type diode.

10: p-type support substrate 11: buried insulating film 12: buried n ⁺ type region 13: n ⁻ type semiconductor substrate 14: trench insulating film 15: polysilicon film 16: anode p ⁺ type region 17: anode n ⁺ type region 18 : Cathode p ⁺ type region 19: Cathode n ⁺ type region 20: Anode p type region 21: Cathode p type region 24: Anode electrode 25: Cathode electrode

Claims (12)

In an electrostatic protection semiconductor device that is electrically isolated from other elements and prevents electrostatic breakdown of other elements,
A buried region of a first conductivity type and a high carrier concentration;
A main semiconductor region of a first conductivity type formed on the buried region and having a lower carrier concentration than the buried region;
A first diffusion region of a second conductivity type formed on the surface of the main semiconductor region;
A first conductivity type first electrode formation region and a second conductivity type second electrode formation region formed on the surface of the first diffusion region;
A first electrode connected to the first electrode formation region and the second electrode formation region;
A second diffusion region of a second conductivity type formed in a region away from the first diffusion region;
Said second formed on the surface of the diffusion region, the third electrode formation region of the first conductivity type, and the fourth electrode formation region of the second conductivity type,
A second electrode connected to the third electrode formation region and the fourth electrode formation region;
Have
The first diffusion region and the second diffusion region include an extension region in a direction opposite to the first diffusion region and the second diffusion region ,
When a voltage is applied so that the first electrode has a positive operating voltage with respect to the second electrode, a depletion layer is formed from the second diffusion region to the buried region,
When a voltage is applied so that the second electrode has a positive operating voltage with respect to the first electrode, a depletion layer extending from the first diffusion region to the buried region is formed.
A semiconductor device for electrostatic protection characterized by the above. In an electrostatic protection semiconductor device that is electrically isolated from other elements and prevents electrostatic breakdown of other elements,
  A buried region of a first conductivity type and a high carrier concentration;
  A main semiconductor region of a first conductivity type formed on the buried region and having a lower carrier concentration than the buried region;
  A first diffusion region of a second conductivity type formed on the surface of the main semiconductor region;
A first conductivity type first electrode formation region and a second conductivity type second electrode formation region formed on the surface of the first diffusion region;
  A first electrode connected to the first electrode formation region and the second electrode formation region;
  A second diffusion region of a second conductivity type formed in a region away from the first diffusion region;
  A first conductivity type third electrode formation region and a second conductivity type fourth electrode formation region formed on the surface of the second diffusion region;
  A second electrode connected to the third electrode formation region and the fourth electrode formation region;
  Have
  The first diffusion region and the second diffusion region include an extension region in a direction opposite to the first diffusion region and the second diffusion region,
  A length of the extension region in a facing direction of the first diffusion region and the second diffusion region, and a vertical distance from the buried region to the first diffusion region and the second diffusion region. The holding pressure resistance is determined by
  A semiconductor device for electrostatic protection.   In an electrostatic protection semiconductor device that is electrically isolated from other elements and prevents electrostatic breakdown of other elements,
  A buried region of a first conductivity type and a high carrier concentration;
  A main semiconductor region of a first conductivity type formed on the buried region and having a lower carrier concentration than the buried region;
  A first diffusion region of a second conductivity type formed on the surface of the main semiconductor region;
A first conductivity type first electrode formation region and a second conductivity type second electrode formation region formed on the surface of the first diffusion region;
  A first electrode connected to the first electrode formation region and the second electrode formation region;
  A second diffusion region of a second conductivity type formed in a region away from the first diffusion region;
  A first conductivity type third electrode formation region and a second conductivity type fourth electrode formation region formed on the surface of the second diffusion region;
  A second electrode connected to the third electrode formation region and the fourth electrode formation region;
  Have
  The first diffusion region and the second diffusion region include an extension region in a direction opposite to the first diffusion region and the second diffusion region,
The length of the extension region in the facing direction of the first diffusion region and the second diffusion region is a lengthwise direction from the buried region to the first diffusion region and the second diffusion region. 4 μm or longer than the distance,
A semiconductor layer value for electrostatic protection, characterized by that. The length of the extension region in the opposing direction of the first diffusion region and the second diffusion region is a vertical distance from the buried region to the first diffusion region and the second diffusion region. The semiconductor device for electrostatic protection according to claim 1 , wherein the semiconductor device is longer by 4 μm or more. The first electrode formation region and the third electrode formation region are disposed inside each other, and the second electrode formation region and the fourth electrode formation region are disposed outside the first electrode formation region and the third electrode formation region. ESD protection for a semiconductor device according to any one of claims 1 to 4, characterized.   6. The electrostatic protection semiconductor according to claim 1, wherein an operation start voltage is determined by a separation distance between the first diffusion region and the second diffusion region. apparatus.   7. The planar pattern of the first diffusion region and the second diffusion region is a strip shape, a track shape, a ring shape, or a composite shape thereof, according to claim 1. The semiconductor device for electrostatic protection as described in the item. The first diffusion region and the second diffusion region are divided into a plurality of sets,
The plurality of first diffusion regions are electrically connected via the first electrode, and the plurality of second diffusion regions are electrically connected via the second electrode. The semiconductor device for electrostatic protection according to any one of claims 1 to 7.   9. The device according to claim 1, wherein one of the first electrode and the second electrode is connected to an input terminal, and the other is connected to a ground electrode. 10. Semiconductor devices for electrostatic protection.   2. The electrostatic protection semiconductor device according to claim 1, wherein a bottom surface and a side surface are partitioned by a bottom surface insulating film and a side surface insulating film, and are electrically insulated from the other elements. 10. The semiconductor device for electrostatic protection according to any one of 9 above.   11. The semiconductor device for electrostatic protection according to claim 1, wherein the main semiconductor region is an SOI substrate. 12. An automotive integrated IC comprising the electrostatic protection semiconductor device according to claim 1.