CN210272355U - Surge protection array based on thyristor structure - Google Patents
Surge protection array based on thyristor structure Download PDFInfo
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- CN210272355U CN210272355U CN201921235539.XU CN201921235539U CN210272355U CN 210272355 U CN210272355 U CN 210272355U CN 201921235539 U CN201921235539 U CN 201921235539U CN 210272355 U CN210272355 U CN 210272355U
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- 238000009792 diffusion process Methods 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- NUHSROFQTUXZQQ-UHFFFAOYSA-N isopentenyl diphosphate Chemical compound CC(=C)CCO[P@](O)(=O)OP(O)(O)=O NUHSROFQTUXZQQ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 34
- 229910052710 silicon Inorganic materials 0.000 description 34
- 239000010703 silicon Substances 0.000 description 34
- 238000001259 photo etching Methods 0.000 description 30
- 238000005468 ion implantation Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 229910052698 phosphorus Inorganic materials 0.000 description 12
- 239000011574 phosphorus Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 8
- 238000001459 lithography Methods 0.000 description 6
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- 230000005611 electricity Effects 0.000 description 5
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
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- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
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- 238000005457 optimization Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 description 2
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Abstract
The utility model discloses a surge protection array based on thyristor structure, including P type substrate, N type diffusion region and voltage modulation district, the left side of P type substrate is equipped with first N type isolation region, the right side of P type substrate is equipped with second N type isolation region; the utility model discloses a surge protection array is in the same place low-capacity diode array and thyristor integration, adopts the thyristor as main surge bleeder device, for adopting the same encapsulation with traditional TVS as the 65A of ESD array of surge bleeder device, the utility model discloses a surge current IPP's value is realized reaching 100A, has for adopting TVS as the stronger surge ability of surge bleeder device, has satisfied the application requirement of electrostatic protection and surge protection to make electrostatic protection device in use can switch on the reposition of redundant personnel in the time of the utmost point weak point, avoid the damage of surge to other equipment in the return circuit.
Description
Technical Field
The utility model belongs to the semiconductor protection device field, it is specific, relate to a surge protection array based on thyristor structure.
Background
An electrostatic protection array is an important electrostatic protection device, and is composed of four switching diodes D1-D4 and a TVS diode T1, as shown in fig. 1, when IO1 has positive static electricity with respect to GND, the static electricity is discharged to GND through D1 and T1, or is discharged to IO2 through D1, T1 and D4; when IO1 has negative static electricity with respect to GND, the static electricity is discharged from GND through D2.
The electrostatic discharge path of the IO2 is similar to that of the IO1 port, so the electrostatic protection array can discharge common-mode and differential-mode static electricity at the same time, and can realize multi-port electrostatic protection. The switch diode in the ESD protection array generally has a lower capacitance, so the capacitance of the whole ESD leakage path is also lower, and some ESD array capacitances can be as low as 0.1pF, so that the ESD array has a higher response speed, which is a significant advantage of the ESD array. However, the existing ESD array also has its disadvantages, the value of the surge current IPP of the existing ESD array cannot meet the application requirement, and does not reach the higher surge capability compared with the TVS adopted as the surge discharge device, and cannot meet the application requirements of electrostatic protection and surge protection, and the electrostatic protection device cannot be turned on and shunted within a very short time in use, thereby possibly causing damage of the surge to other devices in the loop.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the value of the surge current IPP of current ESD array and can not reach the application requirement, do not reach and regard as the higher surge ability of surge bleeder device for adopting TVS, can not satisfy the application requirement of electrostatic protection and surge protection, can not make electrostatic protection device in use switch on the reposition of redundant personnel in the time of the utmost point short to probably lead to the technical problem of the damage of surge other equipment in to the return circuit, and provide a surge protection array based on thyristor structure.
The utility model discloses a following technical scheme realizes:
a surge protection array based on a thyristor structure comprises a P-type substrate, an N-type diffusion area and a voltage modulation area;
a first N-type isolation region is arranged on the left side of the P-type substrate, and a second N-type isolation region is arranged on the right side of the P-type substrate;
an N-type diffusion region is arranged in the center of the bottom of the P-type substrate, a first P-type diffusion region is arranged on the left side of the bottom of the P-type substrate, and a second P-type diffusion region is arranged on the right side of the bottom of the P-type substrate;
a first N-type region is arranged in the center of the upper portion of the P-type substrate, a second N-type region is arranged on the left side of the upper portion of the P-type substrate, and a third N-type region is arranged on the right side of the upper portion of the P-type substrate;
the voltage modulation region is arranged on the right side of the upper part of the P-type substrate, the voltage modulation region is in contact connection with the right side of the first N-type region, the first P-type region and the fifth N-type region are arranged in the second N-type region, the second P-type region and the fourth N-type region are arranged in the third N-type region, and the third P-type region is arranged in the first N-type region;
a sixth N-type region is arranged on the left side of the upper surface inside the P-type substrate, and a seventh N-type region is arranged on the right side of the upper surface inside the P-type substrate;
a first metal layer is arranged on the left side of the upper surface of the P-type substrate, a second metal layer is arranged on the right side of the upper surface of the P-type substrate, a third metal layer is arranged in the middle of the upper surface of the P-type substrate, and a first insulating layer is arranged in the gap among the first metal layer, the second metal layer and the third metal layer;
a fourth metal layer is arranged in the middle of the lower surface of the P-type substrate, and second insulating layers are arranged on two sides of the fourth metal layer;
the first metal layer is connected with the first electrode, the second metal layer is connected with the second electrode, the third metal layer is connected with the third electrode, and the fourth metal layer is connected with the fourth electrode.
Furthermore, the width of the first N-type isolation region and the width of the second N-type isolation region are both 50-100 μm.
Further, the third P-type region on the upper surface, the first N-type region, the P-type substrate and the N-type diffusion region form a pnpn thyristor structure for discharging surge current.
Further, the breakdown voltage of the thyristor can be adjusted by the concentration of the voltage modulation region.
The technical principle of the utility model is as follows:
as shown in fig. 3, the utility model discloses a surge protection array based on thyristor structure is in the same place low-capacitance diode array D1-D4 and surge bleed thyristor are integrated, form low-capacitance diode D1, D3 in two N traps of upper surface, the P district of lower surface constitutes low-capacitance diode D2, D4 with the N district of upper surface, the P district of upper surface constitutes the pnpn thyristor structure with N base region, P substrate, back N district, its breakdown voltage is adjusted by the P type voltage modulation district that links to each other with the N base region, diode D1-D4 and thyristor connect into the structure as shown in fig. 4. As shown in fig. 5, when a forward surge occurs at the IO1 terminal to Gnd (ground) or IO2 terminal, the surge is discharged to Gnd by D1, a thyristor, or to the IO2 port by D1, a thyristor, D4; when a surge negative for Gnd occurs at the IO1 port, the surge is discharged through D2. The situation for IO2 is similar to IO 1. The utility model discloses an action voltage of surge protection array based on thyristor structure can adjust through the ion implantation concentration in regulation voltage modulation district, therefore can realize carrying out surge protection to the electronic circuit of different operating voltage sections such as 3.3V, 5V, 7V, 9V, 12V, 15V, 18V, 24V.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model discloses a surge protection array is in the same place low-capacity diode array and thyristor integration, adopts the thyristor as main surge bleeder device, for adopting the same encapsulation with traditional TVS as the 65A of ESD array of surge bleeder device, the utility model discloses a surge current IPP's value is realized reaching 100A, has for adopting TVS as the stronger surge ability of surge bleeder device, has satisfied the application requirement of electrostatic protection and surge protection to make electrostatic protection device in use can switch on the reposition of redundant personnel in the time of the utmost point weak point, avoid the damage of surge to other equipment in the return circuit.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of a conventional ESD protection array structure based on TVS devices;
fig. 2 is a schematic diagram of a surge protection array structure based on a thyristor structure provided by the present invention;
fig. 3 is a schematic diagram of an equivalent structure of a surge protection array based on a thyristor structure provided by the present invention;
fig. 4 is a schematic diagram of a surge protection array device based on a thyristor structure according to the present invention;
fig. 5 is a schematic diagram illustrating a surge flow direction of a surge protection array based on a thyristor structure according to the present invention;
fig. 6 is a schematic structural diagram of the thyristor-based structure after punch-through diffusion is completed;
fig. 7 is a schematic structural diagram of the thyristor-based structure after the back N + region diffusion is completed;
fig. 8 is a schematic structural diagram of the thyristor-based structure after the front N well region doping is completed;
fig. 9 is a schematic structural diagram of the thyristor-based structure after front N base region doping is completed;
fig. 10 is a schematic structural diagram of the thyristor-based structure after the voltage modulation region is doped;
fig. 11 is a schematic structural diagram of the thyristor-based double-sided P-region doping;
fig. 12 is a schematic structural diagram of the thyristor-based structure after the front N + region doping is completed;
fig. 13 is a schematic structural diagram after forming a metal ohmic contact window based on a thyristor according to the present invention;
fig. 14 is a schematic structural view of the metal aluminum electrode region formed based on the thyristor after the aluminum back etching is completed;
in the figure: 1. a P-type substrate; 2. a first N-type isolation region; 3. a second N-type isolation region; 4. an N-type diffusion region; 5. a first P-type diffusion region; 6. a second P-type diffusion region; 7. a first N-type region; 8. a second N-type region; 9. a third N-type region; 10. a voltage modulation region; 11. a first P-type region; 12. a second P-type region; 13. a third P-type region; 14. a fourth N-type region; 15. a fifth N-type region; 16. a sixth N-type region; 17. a seventh N-type region; 18. a first insulating layer; 19. a first metal layer; 20. a second metal layer; 21. a third metal layer; 22. a second insulating layer; 23. a fourth metal layer; 24. a fourth electrode; 25. a first electrode; 26. a third electrode; 27. a second electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
A surge protection array based on a thyristor structure as shown in fig. 2 comprises a P-type substrate 1, an N-type diffusion region 4 and a voltage modulation region 10;
a first N-type isolation region 2 is arranged on the left side of the P-type substrate 1, and a second N-type isolation region 3 is arranged on the right side of the P-type substrate 1;
an N-type diffusion region 4 is arranged at the center of the bottom of the P-type substrate 1, a first P-type diffusion region 5 is arranged on the left side of the bottom of the P-type substrate 1, and a second P-type diffusion region 6 is arranged on the right side of the bottom of the P-type substrate 1;
a first N-type region 7 is arranged at the center of the upper part of the P-type substrate 1, a second N-type region 8 is arranged on the left side of the upper part of the P-type substrate 1, and a third N-type region 9 is arranged on the right side of the upper part of the P-type substrate 1;
a voltage modulation region 10 is arranged on the right side of the upper part of the P-type substrate 1, the voltage modulation region 10 is in contact connection with the right side of the first N-type region 7, a first P-type region 11 and a fifth N-type region 15 are arranged inside the second N-type region 8, a second P-type region 12 and a fourth N-type region 14 are arranged inside the third N-type region 9, and a third P-type region 13 is arranged inside the first N-type region 7;
a sixth N-type region 16 is arranged on the left side of the upper surface in the P-type substrate 1, and a seventh N-type region 17 is arranged on the right side of the upper surface in the P-type substrate 1;
a first metal layer 19 is arranged on the left side of the upper surface of the P-type substrate 1, a second metal layer 20 is arranged on the right side of the upper surface of the P-type substrate 1, a third metal layer 21 is arranged in the middle of the upper surface of the P-type substrate 1, and a first insulating layer 18 is arranged in the gap part among the first metal layer 19, the second metal layer 20 and the third metal layer 21;
a fourth metal layer 23 is arranged in the middle of the lower surface of the P-type substrate 1, and second insulating layers 22 are arranged on two sides of the fourth metal layer 23;
the first metal layer 19 is connected to the first electrode 25, the second metal layer 20 is connected to the second electrode 27, the third metal layer 21 is connected to the third electrode 26, and the fourth metal layer 23 is connected to the fourth electrode 24.
As a technical optimization scheme of the present invention, the width of the first N-type isolation region 2 and the width of the second N-type isolation region 3 are both 50-100 μm.
As a technical optimization scheme of the utility model, the third P type district 13 and first N type district 7, P type substrate 1 and the N type diffusion zone 4 of upper surface constitute the pnpn thyristor structure and are used for the surge current of releasing.
As a technical optimization scheme of the utility model, thyristor breakdown voltage can be adjusted by the concentration in voltage modulation district 10.
Example 1
A method for manufacturing a surge protection array based on a thyristor structure comprises the following steps:
step S1, substrate preparation
Selecting a P-type silicon single crystal wafer with the thickness of 260 +/-5 mu m;
step S2, polishing
Polishing the silicon single crystal wafer to the thickness of 200 +/-5 microns by adopting a chemical mechanical polishing method;
step S3, oxidizing
By hydrogenGrowing a first insulating layer 18 on the upper surface of the silicon wafer and a second insulating layer 22 on the lower surface of the silicon wafer by an oxygen synthesis method, wherein a dry-wet-dry oxidation mode is adopted, the oxidation temperature is 1150 +/-5 ℃, the dry oxygen is 30min, the wet oxygen is 4h, the dry oxygen is 30min, the oxygen flow is 4L/min, the hydrogen flow is 7.5L/min, and the thickness T of an oxide layer is 4L/minOX＝1.5-1.8μm；
Step S4, N-type isolation region photoetching
Simultaneously photoetching the upper surface and the lower surface of the silicon wafer by using an isolation region photoetching plate and a double-sided photoetching machine to form an isolation region window;
step S5, N-type isolation region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, synchronously carrying out phosphorus predeposition diffusion doping on windows of an isolation region on two sides of a silicon wafer, wherein the predeposition temperature is 1170 +/-5 ℃, the predeposition time is 4h, the diffusion sheet resistance is 0.2-0.3 omega/□, the phosphorus diffusion regions on the two sides are connected together to form a first N-type isolation region 2 and a second N-type isolation region 3 through long-time re-diffusion and knot pushing, the re-diffusion temperature is 1270 +/-5 ℃, the re-diffusion time is 120h, and the structure is shown in figure 6 after the through diffusion is completed;
step S6, back side N + region photoetching
Forming an N + region diffusion window on the lower surface of the silicon wafer by using a back N + region photoetching plate;
step S7, back N + region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method to perform phosphorus diffusion doping on an anode N + region diffusion window on the lower surface of the silicon wafer, wherein the pre-deposition temperature is 1130 +/-5 ℃, the pre-deposition time is 2 hours, the diffusion sheet resistance is 0.5-0.6 omega/□, the re-diffusion temperature is 1250 +/-5 ℃, the time is 10 hours, the junction depth is 20-25 mu m, and the structure is shown in figure 7 after the back N + region diffusion is completed;
step S8, front N well region photoetching
Forming an N-region diffusion window on the upper surface of the silicon wafer by using a front N-well region photoetching plate;
step S9, front N well doping
Performing N well region doping by ion implantation with phosphorus energy of 100keV and dosage of 1e13cm-2After ion implantation, re-expansion propulsion is carried out,the propulsion temperature is 1250 +/-5 ℃, the time is 15 hours, the junction depth is 15-20 mu m, and the structure of the front N well region after doping is finished is shown in figure 8;
step S10, front N-type base region photoetching
Forming an N-region diffusion window on the upper surface of the silicon wafer by using a front base region photoetching plate;
step S11, front N base region doping
Adopting ion implantation process to dope N base region and implant phosphorus with energy of 80keV and dosage of 1e14-1e15cm-2Carrying out re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1250 +/-5 ℃, the propulsion time is 20 hours, the junction depth is 25-30 mu m, and the structure of the doped front N base region is shown in figure 9 after the doping of the front N base region is finished;
step S12, front side voltage modulation zone lithography
Forming a diffusion window on the upper surface of the silicon wafer by using the front voltage modulation area photoetching plate;
step S13, voltage modulation region 10 doping
Doping the voltage modulation region 10 with boron at an energy of 80keV and a dose of 6e14cm by ion implantation-2Performing re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1200 +/-5 ℃, the propulsion time is 2 hours, and the structure of the doped voltage modulation region is shown in figure 10 after the doping is completed;
step S14, double-sided P-type region lithography
Forming P area diffusion windows on the upper surface and the lower surface of the silicon wafer by using a front P area plate and a lower surface back P area plate;
step S15, doping double-sided P region
Adopting ion implantation process to dope P region, implanting boron on both sides, with energy of 60keV and dosage of 3e15cm-2Performing re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1200 +/-5 ℃, the propulsion time is 1h, and the structure of the double-sided P region after doping is shown in FIG. 11;
step S16, front surface N + region photoetching
Forming an N + region diffusion window on the upper surface of the silicon wafer by using a front N + region photoetching plate;
step S17, front N + region doping
By ion implantationThe process comprises doping N + region, implanting phosphorus with energy of 40keV and dosage of 3e15cm-2Performing re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1000 +/-5 ℃, the propulsion time is 1h, and the structure of the doped front N + region is shown in figure 12;
step S18, lead hole lithography
Forming metal ohmic contact windows on the upper and lower surfaces of the silicon wafer by using a photoetching principle, wherein the structure of the metal ohmic contact windows is shown in FIG. 13;
step S19, aluminum steaming
Evaporating a metal aluminum layer with the thickness of 5 +/-2 microns on the upper surface of the silicon wafer;
step S20, aluminum reverse etching
Forming a metal aluminum electrode area on the upper surface of the silicon wafer by utilizing the photoetching principle, wherein the structure of the metal aluminum electrode area is shown in FIG. 14 after aluminum reverse etching is completed;
step S21, back metallization
Evaporating a titanium-nickel-silver composite metal layer on the lower surface of the silicon wafer, wherein the thickness of the titanium layer is respectively titanium layer
Nickel layer
Silver layer
And alloying, wherein the temperature is 420 +/-5 ℃, and the time is 30min, so that a first metal layer 19, a second metal layer 20, a third metal layer 21 and a fourth metal layer 23 are formed, the breakdown voltage of the thyristor is measured to be about 14-16V, the product is packaged into an SOT23-6 packaging form to be subjected to a 8/20 mu s waveform surge test under IEC61000-4-5 standard, the surge current IPP can reach 100A, and is far larger than 65A of an ESD array which adopts the same packaging and takes the traditional TVS as a surge relief device.
Example 2
A method for manufacturing a surge protection array based on a thyristor structure comprises the following steps:
step S1, substrate preparation
Selecting a P-type silicon single crystal wafer with the thickness of 260 +/-5 mu m;
step S2, polishing
Polishing the silicon single crystal wafer to the thickness of 200 +/-5 microns by adopting a chemical mechanical polishing method;
step S3, oxidizing
Growing a first insulating layer 18 on the upper surface of the silicon wafer by adopting an oxyhydrogen synthesis method, growing a second insulating layer 22 on the lower surface of the silicon wafer by adopting a dry-wet-dry oxidation mode, wherein the oxidation temperature is 1150 +/-5 ℃, the dry oxygen is 30min, the wet oxygen is 4h, the dry oxygen is 30min, the oxygen flow is 4L/min, the hydrogen flow is 7.5L/min, and the thickness T of an oxide layer is 4L/minOX＝1.5-1.8μm；
Step S4, N-type isolation region photoetching
Simultaneously photoetching the upper surface and the lower surface of the silicon wafer by using an isolation region photoetching plate and a double-sided photoetching machine to form an isolation region window;
step S5, N-type isolation region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, synchronously carrying out phosphorus predeposition diffusion doping on windows of an isolation region on two sides of a silicon wafer, wherein the predeposition temperature is 1130-1170 ℃, the predeposition time is 2-6 h, the diffusion square resistance is 0.1-0.5 omega/□, and the phosphorus diffusion regions on the two sides are connected together to form a first N-type isolation region 2 and a second N-type isolation region 3 through long-time re-diffusion and junction pushing, wherein the re-diffusion temperature is 1270 +/-5 ℃, and the re-diffusion time is 80-140 h;
step S6, back side N + region photoetching
Forming an N + region diffusion window on the lower surface of the silicon wafer by using a back N + region photoetching plate;
step S7, back N + region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method to perform phosphorus diffusion doping on an anode N + region diffusion window on the lower surface of the silicon wafer, wherein the pre-deposition temperature is 1100-1150 ℃, the pre-deposition time is 2-3 h, the diffusion square resistance is 0.5-0.8 omega/□, the re-diffusion temperature is 1250 +/-5 ℃, the time is 10-12 h, and the junction depth is 20-25 mu m;
step S8, front N well region photoetching
Forming an N-region diffusion window on the upper surface of the silicon wafer by using a front N-well region photoetching plate;
step S9, front N well doping
Performing N well region doping by ion implantation with phosphorus energy of 80-120keV and dosage of 8e12-5e13cm-2Carrying out re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1250 +/-5 ℃, the propulsion time is 10-15 h, and the junction depth is 15-20 mu m;
step S10, front N-type base region photoetching
Forming an N-region diffusion window on the upper surface of the silicon wafer by using a front base region photoetching plate;
step S11, front N base region doping
Adopting ion implantation process to dope N base region and implant phosphorus with energy of 80-100keV and dosage of 1e14-1e15cm-2Carrying out re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1250 +/-5 ℃, the propulsion time is 20-30 h, and the junction depth is 25-30 mu m;
step S12, front side voltage modulation zone lithography
Forming a diffusion window on the upper surface of the silicon wafer by using the front voltage modulation area photoetching plate;
step S13, voltage modulation region 10 doping
Doping the voltage modulation region 10 by ion implantation with boron at an energy of 80-100keV and a dose of 4e14-5e15cm-2Carrying out re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1200 +/-5 ℃, and the propulsion time is 2-4 h;
step S14, double-sided P-type region lithography
Forming P area diffusion windows on the upper surface and the lower surface of the silicon wafer by using a front P area plate and a lower surface back P area plate;
step S15, doping double-sided P region
Adopting ion implantation process to dope P region, implanting boron on both sides, with energy of 50-80keV and dosage of 8e14-3e15cm-2Carrying out re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1200 +/-5 ℃, and the propulsion time is 1h-1.5 h;
step S16, front surface N + region photoetching
Forming an N + region diffusion window on the upper surface of the silicon wafer by using a front N + region photoetching plate;
step S17, front N + region doping
Adopting ion implantation process to dope N + region, implanting phosphorus with energy of 30-60keV and dosage of 1e15-5e15cm-2Carrying out re-expansion propulsion after ion implantation, wherein the propulsion temperature is 1000 +/-5 ℃, and the propulsion time is 1-2 h;
step S18, lead hole lithography
Forming metal ohmic contact windows on the upper surface and the lower surface of the silicon wafer by utilizing a photoetching principle;
step S19, aluminum steaming
Evaporating a metal aluminum layer with the thickness of 5 +/-2 microns on the upper surface of the silicon wafer;
step S20, aluminum reverse etching
Forming a metal aluminum electrode area on the upper surface of the silicon wafer by utilizing the photoetching principle;
step S21, back metallization
Evaporating a titanium-nickel-silver composite metal layer on the lower surface of the silicon wafer, wherein the thickness of the titanium layer is respectively titanium layer
Nickel layer
Silver layer
And alloying at 420 + -5 deg.C for 30-45min to form a first metal layer 19, a second metal layer 20, a third metal layer 21, and a fourth metal layer 23.
Comparative example 1
Comparative example 1 is an ESD array with a conventional TVS as a surge bleed device.
The following performance tests were performed on the surge protection array based on the thyristor structure of examples 1-2 and the conventional TVS of comparative example 1 as the ESD array of the surge relief device: (the product is packaged into a SOT23-6 packaging form to carry out 8/20 mu s current surge waveform test under IEC61000-4-5 standard) test results are as follows:
the utility model discloses a surge protection array is in the same place low-capacity diode array and thyristor integration, adopts the thyristor as main surge bleeder device, for adopting the same encapsulation with traditional TVS as the 65A of ESD array of surge bleeder device, the utility model discloses a surge current IPP's value is realized reaching 100A, has for adopting TVS as the stronger surge ability of surge bleeder device, has satisfied the application requirement of electrostatic protection and surge protection to make electrostatic protection device in use can switch on the reposition of redundant personnel in the time of the utmost point weak point, avoid the damage of surge to other equipment in the return circuit.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention.
Claims (3)
1. A surge protection array based on a thyristor structure is characterized by comprising a P-type substrate (1), an N-type diffusion region (4) and a voltage modulation region (10);
a first N-type isolation region (2) is arranged on the left side of the P-type substrate (1), and a second N-type isolation region (3) is arranged on the right side of the P-type substrate (1);
an N-type diffusion region (4) is arranged at the center of the bottom of the P-type substrate (1), a first P-type diffusion region (5) is arranged on the left side of the bottom of the P-type substrate (1), and a second P-type diffusion region (6) is arranged on the right side of the bottom of the P-type substrate (1);
a first N-type region (7) is arranged in the center of the upper part of the P-type substrate (1), a second N-type region (8) is arranged on the left side of the upper part of the P-type substrate (1), and a third N-type region (9) is arranged on the right side of the upper part of the P-type substrate (1);
a voltage modulation region (10) is arranged on the right side of the upper portion of the P-type substrate (1), the voltage modulation region (10) is in contact connection with the right side of the first N-type region (7), a first P-type region (11) and a fifth N-type region (15) are arranged inside the second N-type region (8), a second P-type region (12) and a fourth N-type region (14) are arranged inside the third N-type region (9), and a third P-type region (13) is arranged inside the first N-type region (7);
a sixth N-type region (16) is arranged on the left side of the inner upper surface of the P-type substrate (1), and a seventh N-type region (17) is arranged on the right side of the inner upper surface of the P-type substrate (1);
a first metal layer (19) is arranged on the left side of the upper surface of the P-type substrate (1), a second metal layer (20) is arranged on the right side of the upper surface of the P-type substrate (1), a third metal layer (21) is arranged in the middle of the upper surface of the P-type substrate (1), and a first insulating layer (18) is arranged in the gap part among the first metal layer (19), the second metal layer (20) and the third metal layer (21);
a fourth metal layer (23) is arranged in the middle of the lower surface of the P-type substrate (1), and second insulating layers (22) are arranged on two sides of the fourth metal layer (23);
the first metal layer (19) is connected to a first electrode (25), the second metal layer (20) is connected to a second electrode (27), the third metal layer (21) is connected to a third electrode (26), and the fourth metal layer (23) is connected to a fourth electrode (24).
2. The surge protection array based on the thyristor structure according to claim 1, wherein the width of each of the first N-type isolation region (2) and the second N-type isolation region (3) is 50-100 μm.
3. The surge protection array based on the thyristor structure of claim 1, wherein the third P-type region (13) on the upper surface forms a pnpn thyristor structure with the first N-type region (7), the P-type substrate (1) and the N-type diffusion region (4).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491873A (en) * | 2019-08-01 | 2019-11-22 | 富芯微电子有限公司 | A kind of surge protection array and manufacturing method based on thyristor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491873A (en) * | 2019-08-01 | 2019-11-22 | 富芯微电子有限公司 | A kind of surge protection array and manufacturing method based on thyristor structure |
| CN110491873B (en) * | 2019-08-01 | 2024-03-01 | 富芯微电子有限公司 | Surge protection array based on thyristor structure and manufacturing method |
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