CN105552074A - Germanium-silicon heterojunction process-based SCR device - Google Patents
Germanium-silicon heterojunction process-based SCR device Download PDFInfo
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- CN105552074A CN105552074A CN201510974257.1A CN201510974257A CN105552074A CN 105552074 A CN105552074 A CN 105552074A CN 201510974257 A CN201510974257 A CN 201510974257A CN 105552074 A CN105552074 A CN 105552074A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
Abstract
The invention belongs to the technical field of electrostatic discharge protection of integrated circuits, and relates to a germanium-silicon heterojunction process-based SCR device. The germanium-silicon heterojunction process-based SCR device comprises a first conductive type silicon substrate, wherein adjacent second conductive type well region and first conductive type well region are formed on the silicon substrate; a second conductive type heavily doped region and a first conductive type heavily doped region are arranged in the two well regions respectively; the other second conductive type heavily doped region is arranged in the second conductive type well region; a second conductive type buried layer region is also formed on the silicon substrate; a second conductive type collector region and two second conductive type heavily doped region adjacent to two sides of the collector region are formed on the second conductive type buried layer region; the second conductive type buried layer region is connected with the other second conductive type heavily doped region in the second conductive type well region; the silicon surface of the collector region is sequentially provided with a first conductive type germanium-silicon layer and a second conductive type heavily doped polysilicon layer; and the heavily doped polysilicon layer is connected with a cathode. According to the germanium-silicon heterojunction process-based SCR device, the trigger voltage of the SCR device can be effectively reduced.
Description
Technical field
The invention belongs to static discharge (ESD) the resist technology field of integrated circuit, relate to a kind of ESD protective device, be specifically related to a kind of SCR device based on Ge-Si heterojunction technique.
Background technology
Static discharge (ElectrostaticDischarge, be called for short ESD) is the very general phenomenon of occurring in nature, is the Charger transfer occurring moment between two electrified bodies.All can make electrostatic charge on object band by friction or electrostatic induction, cause dielectric breakdown when two objects with different electromotive force are close to each other or directly contact, all static discharge phenomenon can occur, often be attended by visible electric spark.Static discharge can produce the voltage up to volt up to ten thousand, and so large electrostatic potential will form huge threat to integrated circuit (IC).In the whole life cycle of integrated circuit (IC) products, from manufacture, encapsulation, test, transport, use in complete IC product, all the moment is faced with the threat that static discharge is formed.In order to head it off; manufacturer arranges a protective circuit usually between internal circuit and I/O pin; this protective circuit must be opened in advance before the pulse of static discharge does not arrive internal circuit, with ESD big current of releasing rapidly, and then the destruction that minimizing ESD phenomenon causes.
Conventional ESD protective device has diode, insulated-gate type field effect transistor (MOSFET), bipolar transistor (BJT), thyristor (SCR); Wherein, SCR device can make full use of trap and substrate as current drain path, and this makes device can bear larger ESD immediate current, compares other ESD protective device, and the unit are esd protection ability of SCR device is the strongest.But the shortcoming that the SCR device of routine is used to ESD protection is cut-in voltage (V
t1) too large, and be greater than the grid oxygen puncture voltage of MOSFET; But along with constantly the reducing of characteristic size of device, the thickness of gate oxide is also constantly thinning; Under this trend, it is the problem that those skilled in the art constantly study that development low pressure triggers SCR device.
At present, as shown in Figure 1, this device architecture comprises for basic SCR device structure and equivalent electric circuit thereof:
P-type silicon substrate 110;
Described substrate 110 forms well region, and described well region comprises a N-shaped well region 120 and a p-type well region 130, and described well region 120 adjoins described well region 130;
Be provided with N-shaped heavily doped region 121 and p-type heavily doped region 122 in described N-shaped well region 120, and described region 121 is connected with anode with region 122;
Be provided with the heavily doped region 131 of N-shaped and the heavily doped region 132 of p-type in described p-type well region 130, and region 131 is connected with negative electrode with region 132.
Can be seen by the equivalent circuit diagram of above-mentioned SCR device, this SCR device is made up of a parasitic pnp transistor and a parasitic npn transistor.Wherein, p-type heavily doped region 122, N-shaped well region 120, p-type well region 130 and p-type heavily doped region 132 form a pnp transistor, N-shaped heavily doped region 131, p-type well region 130, N-shaped well region 120 and N-shaped heavily doped region 121 form a npn transistor, R_nw is N-shaped well region 120 resistance, and R_pw is p-type well region 130 resistance.When esd event comes interim, the collector junction of parasitic npn pipe is reverse-biased.When this reversed bias voltage is greater than the avalanche breakdown voltage of this pn knot, this pn ties and produces a large amount of electron hole pair formation electric currents, wherein, electronic current flows through N-shaped well region 120 and produce pressure drop on R_nw, the pn that p-type heavily doped region 122 and N-shaped well region 120 are formed ties positively biased, the i.e. emitter junction positively biased of parasitic pnp pipe, pnp pipe is opened.Meanwhile, hole current flows through p-type well region 130 resistance R_pw, and the pn that N-shaped heavily doped region 131 and p-type well region 130 are formed ties positively biased, and the emitter junction positively biased namely in npn pipe, makes npn pipe open.Afterwards, the collector current of pnp pipe provides base current for npn pipe, and the collector current of npn pipe provides base current for pnp pipe, between parasitic pnp pipe with npn pipe, produce positive feedback mechanism, SCR conducting.Therefore, the trigger voltage of this basic SCR device is that the avalanche breakdown voltage of the pn knot formed by N-shaped well region 120 and p-type well region 130 determines, and this voltage is often greater than the puncture voltage of the gate oxide of this technique in common process; Therefore this device directly can not be used in the esd protection circuit of integrated circuit, and needs increase safe secondary protection circuit to use, and will increase the chip area of esd protection circuit like this.
Based on this, the invention provides the SCR device that a kind of new E SD protects, reduce the trigger voltage of SCR device further.
Summary of the invention
The object of the present invention is to provide a kind of SCR device based on Ge-Si heterojunction technique, for reducing the trigger voltage of SCR device.The technical solution used in the present invention is:
A kind of SCR device based on Ge-Si heterojunction technique, comprise the first conduction type silicon substrate, silicon substrate is formed adjacent the second conduction type well region and the first conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with anode is provided with in described the second conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with negative electrode is provided with in the first conduction type well region described, it is characterized in that, be positioned at the first conduction type heavily doped region in described the second conduction type well region and be also provided with another the second conduction type heavily doped region near the side of two well region adjoiners, described silicon substrate is also formed with the second conduction type buried regions district, described the second conduction type buried regions district is formed adjacent two the second conduction type heavily doped regions in the second conduction type collector region and both sides, the second conduction type collector region, and adjacent two the second conduction type heavily doped regions, both sides, described the second conduction type collector region be positioned at another the second conduction type heavily doped region near the side of two well region adjoiners, the first conduction type heavily doped region in described the second conduction type well region and be connected, the silicon face of described the second conduction type collector region is arranged the first conduction type germanium silicon layer, the first conduction type germanium silicon layer described forms the second conduction type heavily doped polysilicon layer, described the second conduction type heavily doped polysilicon layer is connected with negative electrode.
Further, the first conduction type germanium silicon layer described is connected by external resistance with the second conduction type heavily doped polysilicon layer.
The invention provides a kind of SCR device based on Ge-Si heterojunction technique, this device architecture is on existing SCR device architecture basics, SCR structure and HBT structure are combined, when esd event arrives, HBT structure is On current first, this electric current is re-used as trigger current and opens to trigger SCR device, effectively can be reduced the trigger voltage of SCR device, and SCR device of the present invention can regulate the trigger voltage of SCR device by HBT structure by Novel SCR provided by the invention.
Accompanying drawing explanation
The existing basic SCR device structure of Fig. 1 and schematic equivalent circuit.
Fig. 2 embodiment 1 is based on the Novel SCR device architecture of Ge-Si heterojunction technique and schematic equivalent circuit.
Fig. 3 embodiment 2 is based on the Novel SCR device architecture of Ge-Si heterojunction technique and schematic equivalent circuit.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment 1
Be illustrated in figure 2 the Novel SCR device architecture schematic diagram based on Ge-Si heterojunction technique and equivalent electric circuit that the present embodiment provides, its structure comprises:
P-type silicon substrate 110;
Described p-type silicon substrate 110 forms well region, and described well region comprises a N-shaped well region 120 and a p-type well region 130, and described N-shaped well region 120 adjoins described p-type well region 130;
Be provided with the first N-shaped heavily doped region 121 and the first p-type heavily doped region 122 in described N-shaped well region 120, and described first p-type heavily doped region 122, N-shaped heavily doped region 121, first is connected with anode; Also be provided with the 3rd N-shaped heavily doped region 123 in described N-shaped well region 120, be positioned at the first p-type heavily doped region 122 near the side of N-shaped well region 120 with p-type well region 130 adjoiner;
Be provided with the second N-shaped heavily doped region 131 and the second p-type heavily doped region 132 in described p-type well region 130, and the heavily doped region 132 of described second N-shaped heavily doped region 131, second p-type is connected with negative electrode;
Described p-type silicon substrate 110 is formed N-shaped buried regions district 150;
Described N-shaped buried regions district 150 forms N-shaped collector region 140, and n-type area 140 both sides are adjacent 4th N-shaped heavily doped region 161 and the 5th N-shaped heavily doped region 162 respectively, and described 4th, the 5th N-shaped heavily doped region is connected with described 3rd N-shaped heavily doped region 123;
The silicon face of described N-shaped collector region 140 is arranged pXing Zhe silicon layer district 170, described pXing Zhe silicon layer district 170 forms N-shaped heavily doped polysilicon layer district 180, and described N-shaped heavily doped polysilicon layer district 180 is connected with negative electrode.
Can see from equivalent electric circuit, above-mentioned Novel SCR device is made up of a parasitic pnp transistor, a parasitic npn transistor and a parasitic HBT; Wherein, the first p-type heavily doped region 122, N-shaped well region 120, p-type well region 130 and the second p-type heavily doped region 132 form a pnp transistor; Second N-shaped heavily doped region 131, p-type well region 130, N-shaped well region 120 and the first N-shaped heavily doped region 121 form a npn transistor; N-shaped collector region 140, p-type germanium silicon area 170 and N-shaped heavily doped polysilicon district 180 form a HBT; R_nw is N-shaped well region 120 resistance, and R_pw is p-type well region 130 resistance.
When esd event comes interim, the anode voltage of SCR device rises, and the voltage rise of N-shaped heavily doped region 123, N-shaped heavily doped region 161 and 162, makes the collector junction of HBT device reverse-biased thereupon; When ESD voltage is greater than the collector junction avalanche breakdown voltage BV of the HBT device of open base
cEOtime, the pn formed in N-shaped collector region 140 and pXing Zhe silicon layer district 170 ties knot face annex and produces a large amount of electron hole pairs; Wherein, hole flows to negative electrode, parasitic HBT conducting by the forward biased pn knot formed by N-shaped heavily doped polysilicon district 180 and pXing Zhe silicon layer district 170.And electronics is successively by N-shaped collector region 140, N-shaped buried regions district 150, N-shaped heavily doped region 161 and 162, N-shaped heavily doped region 123, N-shaped well region 120 and N-shaped heavily doped region 121, finally flow into anode, form current channel.The electric current that this electronic current flows through N-shaped well region 120 produces pressure drop on R_nw, and the pn that p-type heavily doped region 122 and N-shaped well region 120 are formed ties positively biased, makes the conducting of parasitic pnp pipe; Meanwhile, the collector current of pnp pipe flows through p-type well region 130 resistance R_pw, and the pn that N-shaped heavily doped region 131 and p-type well region 130 are formed ties positively biased, and npn pipe is opened; Afterwards, the collector current of pnp pipe provides base current for npn pipe, and the collector current of npn pipe provides base current for pnp pipe, between parasitic pnp pipe with npn pipe, produce positive feedback mechanism, SCR conducting.Therefore, the trigger voltage of this Novel SCR device is by the collector junction avalanche breakdown voltage BV of the HBT device of open base
cEOdetermine, this voltage BV
cEObe be less than single by pXing Zhe silicon layer district 170 and n-type area 140 form the puncture voltage BV that pn ties
cBO, pass is between the two:
Wherein, β is the direct current common-emitter current gain of HBT, and its numerical value is generally from tens to hundreds of; S is a structural constant, and the S that the S for npn pipe should equal 4, pnp pipe should equal 2.
In sum, the Novel SCR device based on Ge-Si heterojunction technique provided by the invention effectively can reduce the trigger voltage of existing SCR device, and in addition, this Novel SCR device also regulates the trigger voltage of SCR device by HBT structure.
Embodiment 2
Be illustrated in figure 3 the Novel SCR device architecture schematic diagram based on Ge-Si heterojunction technique and equivalent electric circuit that the present embodiment provides, its structure is with the difference of embodiment 2: described pXing Zhe silicon layer district 170 is connected by external resistance R with N-shaped heavily doped polysilicon layer district 180.
When esd event comes interim, the anode voltage of SCR device rises, and the voltage rise of N-shaped heavily doped region 123, N-shaped heavily doped region 161 and 162, makes the collector junction of HBT device reverse-biased thereupon.When ESD voltage is greater than BV
cEOtime, the pn formed in N-shaped collector region 140 and pXing Zhe silicon layer district 170 is tied knot face annex and produces a large amount of electron hole pairs; Wherein, hole flows to negative electrode by resistance R, makes the pn formed by N-shaped heavily doped polysilicon district 180 and pXing Zhe silicon layer district 170 tie positively biased, thus makes parasitic HBT conducting.And electronics is successively by n-type area 140, N-shaped buried regions district 150, N-shaped heavily doped region 161 and 162, N-shaped heavily doped region 123, N-shaped well region 120 and N-shaped heavily doped region 121, finally flow into anode, form current channel.This electronic current flows through N-shaped well region 120 and produce pressure drop on R_nw, and the pn that p-type heavily doped region 122 and N-shaped well region 120 are formed ties positively biased, makes the conducting of parasitic pnp pipe.Meanwhile, the collector current of pnp pipe flows through p-type well region 130 resistance R_pw, and the pn that N-shaped heavily doped region 131 and p-type well region 130 are formed ties positively biased, and npn pipe is opened.Afterwards, the collector current of pnp pipe provides base current for npn pipe, and the collector current of npn pipe provides base current for pnp pipe, between parasitic pnp pipe with npn pipe, produce positive feedback mechanism, SCR conducting.Therefore, the trigger voltage of this Novel SCR device is that the collector junction avalanche breakdown voltage of the HBT device be connected by external resistance with emitter by base stage is determined, and can be controlled the trigger voltage of SCR device by the size adjusting outer meeting resistance.
The above, be only the specific embodiment of the present invention, arbitrary feature disclosed in this specification, unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object; Step in disclosed all features or all methods or process, except mutually exclusive feature and/or step, all can be combined in any way.
Claims (2)
1. the SCR device based on Ge-Si heterojunction technique, comprise the first conduction type silicon substrate, silicon substrate is formed adjacent the second conduction type well region and the first conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with anode is provided with in described the second conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with negative electrode is provided with in the first conduction type well region described, it is characterized in that, be positioned at the first conduction type heavily doped region in described the second conduction type well region and be also provided with another the second conduction type heavily doped region near the side of two well region adjoiners, described silicon substrate is also formed with the second conduction type buried regions district, described the second conduction type buried regions district is formed adjacent two the second conduction type heavily doped regions in the second conduction type collector region and both sides, the second conduction type collector region, and adjacent two the second conduction type heavily doped regions, both sides, described the second conduction type collector region be positioned at another the second conduction type heavily doped region near the side of two well region adjoiners, the first conduction type heavily doped region in described the second conduction type well region and be connected, the silicon face of described the second conduction type collector region is arranged the first conduction type germanium silicon layer, the first conduction type germanium silicon layer described forms the second conduction type heavily doped polysilicon layer, described the second conduction type heavily doped polysilicon layer is connected with negative electrode.
2., by the SCR device based on Ge-Si heterojunction technique described in claim 1, it is characterized in that, the first conduction type germanium silicon layer described is connected by external resistance with the second conduction type heavily doped polysilicon layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109065537A (en) * | 2018-08-24 | 2018-12-21 | 电子科技大学 | High maintenance electric current SCR device for ESD protection |
| CN110459594A (en) * | 2019-08-29 | 2019-11-15 | 成都矽能科技有限公司 | A kind of embedded isolation ring can be used for electrostatic leakage protection is silicon-controlled |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7728349B2 (en) * | 2005-10-11 | 2010-06-01 | Texas Instruments Incorporated | Low capacitance SCR with trigger element |
| US7919817B2 (en) * | 2008-05-16 | 2011-04-05 | Alpha & Omega Semiconductor Ltd. | Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies |
| CN101840918B (en) * | 2010-04-14 | 2011-12-21 | 电子科技大学 | Silicon controlled rectifier electro-static discharge protective circuit structure triggered by diode |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109065537A (en) * | 2018-08-24 | 2018-12-21 | 电子科技大学 | High maintenance electric current SCR device for ESD protection |
| CN109065537B (en) * | 2018-08-24 | 2021-01-08 | 电子科技大学 | High-maintenance-current SCR device for ESD protection |
| CN110459594A (en) * | 2019-08-29 | 2019-11-15 | 成都矽能科技有限公司 | A kind of embedded isolation ring can be used for electrostatic leakage protection is silicon-controlled |
| CN110459594B (en) * | 2019-08-29 | 2024-04-12 | 成都矽能科技有限公司 | Embedded isolation ring silicon controlled rectifier capable of being used for electrostatic discharge protection |
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