CN110444587A - 具有埋层的终端结构 - Google Patents

具有埋层的终端结构 Download PDF

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CN110444587A
CN110444587A CN201910773374.XA CN201910773374A CN110444587A CN 110444587 A CN110444587 A CN 110444587A CN 201910773374 A CN201910773374 A CN 201910773374A CN 110444587 A CN110444587 A CN 110444587A
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buried layer
limiting ring
conduction type
semiconductor area
field limiting
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CN110444587B (zh
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伍济
陈钱
许生根
姜梅
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Jiangsu CAS IGBT Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Abstract

本发明涉及一种终端结构，尤其是一种具有埋层的终端结构，属于半导体器件的技术领域。按照本发明提供的技术方案，所述具有埋层的终端结构，包括具有第一导电类型的半导体漂移区以及设置于所述半导体漂移区内的场限环；在所述半导体漂移区内还设置第二导电类型埋层，所述第二导电类型埋层与半导体漂移区正面上的场氧化层间通过半导体漂移区隔离。本发明结构紧凑，利用所述终端结构能提高功率半导体器件在高温下的可靠性。

Description

具有埋层的终端结构
技术领域
本发明涉及一种终端结构，尤其是一种具有埋层的终端结构，属于半导体器件的技术领域。
背景技术
功率器件通常应用于电力电子电路，以控制功率的传输，根据其导通特性及阻断能力，往往采取相应的器件来适应不同应用场合。由于功率器件在反向阻断状态下必须具备一定的电压阻断能力才能正常工作，其终端结构对于提供耐压能力显得尤为重要。
一直以来，功率器件的主流终端结构通过场限环结合场板实现。由于这种结构占用过多的芯片面积且表面电场较高，Stengl与Gosele提出采用结终端扩展(JTE)结构以缩短终端尺寸同时降低表面电场峰值。这种传统的JTE结构受限于工艺线在控制器件终端表面固定电荷的精确度，无法达到理想的击穿电压。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种具有埋层的终端结构，其结构紧凑，利用所述终端结构能提高功率半导体器件在高温下的可靠性。
按照本发明提供的技术方案，所述具有埋层的终端结构，包括具有第一导电类型的半导体漂移区以及设置于所述半导体漂移区内的场限环；在所述半导体漂移区内还设置第二导电类型埋层，所述第二导电类型埋层与半导体漂移区正面上的场氧化层间通过半导体漂移区隔离。
所述场限环包括第二导电类型场限环以及第一导电类型场限环，第二导电类型埋层位于第二导电类型场限环与第一导电类型场限环场之间，第一导电类型场限环位于半导体漂移区的外圈边缘，第二导电类型埋层的掺杂浓度低于第二导电类型场限环的掺杂浓度，第一导电类型场限环的掺杂浓度大于半导体漂移区的掺杂浓度。
所述第二导电类型埋层与第二导电类型场限环接触。
在所述半导体漂移区的背面还设置背面结构，所述背面结构包括与半导体漂移区邻接的半导体衬底以及与所述半导体衬底适配的背面电极，在半导体漂移区的正面设有正面电极。
所述“第一导电类型”和“第二导电类型”两者中，对于N型功率半导体器件，第一导电类型指N型，第二导电类型为P型；对于P型功率半导体器件，第一导电类型与第二导电类型所指的类型与N型功率半导体器件正好相反。
本发明的优点：在半导体漂移区内设置第二导电类型埋层，第二导电类型埋层通过半导体漂移区与场氧化层间隔，当背面电极施加正向偏置，正面电极接地，终端结构内PN结表现为反向偏置状态，第二导电类型埋层由于掺杂较轻而全耗尽，第二导电类型埋层上方及下方的半导体漂移区同时耗尽，等效于增加了受主杂质与施主杂质接触面积，击穿电压比相同尺寸的传统JTE终端结构更高，即利用第二导电类型埋层的辅助耗尽，缩短了终端结构的尺寸，与现有工艺兼容，制造简单，且相比传统JTE终端结构在高温下可靠性更好，不易受表面固定电荷影响且尺寸更短。
附图说明
图1为本发明的结构示意图。
附图标记说明：1-正面电极、2-场氧化层、3-P型场限环、4-P型埋层、5-N+场限环、6-半导体漂移区、7-N+衬底以及8-背面电极。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图1所示：为了利用所述终端结构能提高功率半导体器件在高温下的可靠性，以N型功率半导体器件为例，本发明包括具有N导电类型的半导体漂移区6以及设置于所述半导体漂移区6内的场限环；在所述半导体漂移区6内还设置P型埋层4，所述P型埋层4与半导体漂移区6正面上的场氧化层2间通过半导体漂移区6隔离。
具体地，对于功率半导体器件，一般包括有源区以及终端结构，有源区位于半导体漂移区6的中心区，终端结构位于半导体漂移区6的外圈，终端结构环绕包围有源区，终端结构位于终端区域内，有源区与终端结构的位置关系以及终端结构的具体作用为本技术领域的技术人员所熟知，此处不再赘述。
本发明实施例中，半导体漂移区6的材料可以为硅或其他常用的材料，具体材料的类型可以根据需要进行选择，此处不再赘述。场限环设置于半导体漂移区6的终端区域内。在终端区域内还设置P型埋层4，场氧化层2覆盖在半导体漂移区6上，场氧化层2一般为二氧化硅层，场氧化层2与场限环交叠。具体实施时，P型埋层4位于半导体漂移区6内，P型埋层4被半导体漂移区6包围，通过半导体漂移区6与场氧化层2隔离，即P型埋层4在半导体漂移区6内呈浮空状态，P型埋层4不与场氧化层2接触。
进一步地，所述场限环包括P型场限环3以及N+场限环5，P型埋层4位于P型场限环3与N+场限环场5之间，N+场限环5位于半导体漂移区6的外圈边缘，P型埋层4的掺杂浓度低于P型场限环3的掺杂浓度，N+场限环4的掺杂浓度大于半导体漂移区6的掺杂浓度。
本发明实施例中，半导体漂移区6内的场限环包括P型场限环3以及N+场限环5，在半导体漂移区6内，P型场限环3邻近有源区，N+场限环5位于半导体漂移区6内的外圈边缘，P型场限环3、N+场限环5均与场氧化层2接触。P型埋层4位于P型场限环3与N+场限环5之间，P型埋层4的掺杂浓度低于P型场限环3的掺杂浓度，N+场限环4的掺杂浓度大于半导体漂移区6的掺杂浓度。
具体实施时，所述P型埋层4与P型场限环3接触。当然，P型埋层4也可以与P型场限环3不接触，P型埋层4在半导体漂移区6内层水平分布。此外，在半导体漂移区6内，P型埋层4的深度可以与P型场限环3的深度相一致，当然，P型埋层4的底部也可以位于P型场限环3底部的下方或上方，具体可以根据需要进行选择，此处不再赘述。
进一步地，在所述半导体漂移区6的背面还设置背面结构，所述背面结构包括与半导体漂移区6邻接的N+衬底7以及与所述N+衬底7适配的背面电极8，在半导体漂移区6的正面设有正面电极1。
本发明实施例中，对于一个完整的功率半导体器件，还需要背面结构，具体地，半导体漂移区6的背面设置N+衬底7，N+衬底7的掺杂浓度大于半导体漂移区6的掺杂浓度，N+衬底7的厚度一般小于半导体漂移区6的厚度。为了将背面结构引出，需要设置背面电极8，同时，在半导体漂移区6的正面设置正面电极1，背面电极8、正面电极1具体结构形式根据功率半导体器件的类型进行确定，如功率半导体器件为IGBT器件时，正面电极1一般为发射极，背面电极8一般为集电极。
本发明在半导体漂移区6内设置P型埋层4，P型埋层4通过半导体漂移区6与场氧化层2间隔，当背面电极8施加正向偏置，正面电极1接地，终端结构内PN结表现为反向偏置状态，P型埋层4由于掺杂较轻而全耗尽，P型埋层4上方及下方的半导体漂移区6同时耗尽，等效于增加了受主杂质与施主杂质接触面积，击穿电压比相同尺寸的传统JTE终端结构更高，即利用P型埋层4的辅助耗尽，缩短了终端结构的尺寸。

Claims (4)

1.一种具有埋层的终端结构，包括具有第一导电类型的半导体漂移区以及设置于所述半导体漂移区内的场限环；其特征是：在所述半导体漂移区内还设置第二导电类型埋层，所述第二导电类型埋层与半导体漂移区正面上的场氧化层间通过半导体漂移区隔离。
2.根据权利要求1所述的具有埋层的终端结构，其特征是：所述场限环包括第二导电类型场限环以及第一导电类型场限环，第二导电类型埋层位于第二导电类型场限环与第一导电类型场限环场之间，第一导电类型场限环位于半导体漂移区的外圈边缘，第二导电类型埋层的掺杂浓度低于第二导电类型场限环的掺杂浓度，第一导电类型场限环的掺杂浓度大于半导体漂移区的掺杂浓度。
3.根据权利要求2所述的具有埋层的终端结构，其特征是：所述第二导电类型埋层与第二导电类型场限环接触。
4.根据权利要求1所述的具有埋层的终端结构，其特征是：在所述半导体漂移区的背面还设置背面结构，所述背面结构包括与半导体漂移区邻接的半导体衬底以及与所述半导体衬底适配的背面电极，在半导体漂移区的正面设有正面电极。
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CN113314600A (zh) * 2021-06-22 2021-08-27 珠海市浩辰半导体有限公司 埋层终端结构及其制备方法
CN114497178A (zh) * 2021-12-16 2022-05-13 陕西半导体先导技术中心有限公司 一种功率器件的体内多区连续终端结构及制备方法
EP4343854A1 (en) * 2022-09-22 2024-03-27 Kabushiki Kaisha Toshiba Termination region for semiconductor device and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
CN113314600A (zh) * 2021-06-22 2021-08-27 珠海市浩辰半导体有限公司 埋层终端结构及其制备方法
CN113314600B (zh) * 2021-06-22 2022-04-15 珠海市浩辰半导体有限公司 埋层终端结构及其制备方法
CN114497178A (zh) * 2021-12-16 2022-05-13 陕西半导体先导技术中心有限公司 一种功率器件的体内多区连续终端结构及制备方法
EP4343854A1 (en) * 2022-09-22 2024-03-27 Kabushiki Kaisha Toshiba Termination region for semiconductor device and manufacturing method thereof

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