CN110364565B - 堆叠状的iii-v族半导体构件 - Google Patents

堆叠状的iii-v族半导体构件 Download PDF

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CN110364565B
CN110364565B CN201910279531.1A CN201910279531A CN110364565B CN 110364565 B CN110364565 B CN 110364565B CN 201910279531 A CN201910279531 A CN 201910279531A CN 110364565 B CN110364565 B CN 110364565B
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V·杜德克
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Abstract

一种堆叠状的III‑V族半导体构件(10)，其具有堆叠(100)，该堆叠具有上侧(102)、下侧(104)、侧面(106)和纵轴线(L)；其中，堆叠(100)具有p+区域(12)，n‑层(14)和n+区域(16)；p+区域(12)、n‑层(14)和n+区域(16)沿纵轴线(L)以所提及的顺序彼此相继，单片地构造且包括GaAs化合物；n+区域(16)或p+区域(12)构造为衬底层；堆叠(100)在侧面(106)的区域内具有环绕的凸肩状的第一和第二边缘(110、120)；第一边缘(110)由衬底层构成；第二边缘(120)由n‑层(16)或由邻接n‑层(16)和p+区域(12)的中间层(18)构成；并且环绕的第一和第二边缘(110、120)分别具有至少10μm的宽度。

Description

堆叠状的III-V族半导体构件
技术领域
本发明涉及一种堆叠状的III-V族半导体构件。
背景技术
由Josef Lutz等人的《Semiconductor Power Devices》，Springer 2011版，ISBN978-3-642-11124-2，已知基于硅或碳化硅的高阻断的肖特基二极管以及IGBT。
由German Ashkinazi的《GaAs Power Devices》，ISBN 965-7094-19-4已知基于砷化镓的高压稳定的半导体二极管p+-n-n+以及肖特基二极管、高压稳定的p-n-i-p晶体管。此外，在第5.3章中还描述台式(Mesa)工艺以及具有聚酰亚胺的侧面的涂层。
发明内容
在这些背景下，本发明的任务在于，给出一种扩展现有技术的设备。
该任务通过具有权利要求1的特征的堆叠状的III-V族半导体构件来解决。本发明有利的设计方案是从属权利要求的主题。
本发明的主题是一种堆叠状的III-V族半导体构件，所述III-V族半导体构件具有堆叠(Stapel)，所述堆叠具有上侧、下侧、连接上侧和下侧的侧面以及延伸通过上侧和下侧的纵轴线。
堆叠具有p+区域、n-层(14)以及n+区域，所述p+区域具有上侧、下侧和5·1018-5·1020N/cm3的掺杂剂浓度(Dotierstoffkonzentration)，所述n-层具有上侧和下侧、1012-1017N/cm3的掺杂剂浓度和10-300μm的层厚(D2)，所述n+区域具有上侧、下侧和至少1019N/cm3的掺杂剂浓度。
p+区域、n-层和n+区域沿堆叠的纵轴线以所提及的顺序彼此相继，分别单片地构造并且分别包括GaAs(砷化镓)化合物或者分别由GaAs化合物组成。n+区域或p+区域构造为衬底层。
堆叠在侧面的区域内具有环绕的凸肩状的第一边缘和环绕的凸肩状的第二边缘，其中，第一边缘由衬底层构成，第二边缘由n-层或由邻接n-层和p+区域的中间层构成，并且环绕的第一边缘和环绕的第二边缘分别具有至少10μm的宽度。
堆叠的上侧和下侧例如矩形、方形或圆形地构造。所有将下侧与上侧连接的面区段表示为侧面，这些面区段侧向包围堆叠。通过凸肩状的边缘阶梯状地构造侧面。
应注意到，优选地借助液相外延或借助金属有机物气相外延(MOVPE)设备制造所述层。
可以理解，半导体构件具有至少两个优选地构造为层的连接端接通部，其中，连接端接通部分别是能导电的并且具有金属特性。
优选地，连接端接通部层由能金属地导电的半导体层或金属层或两者的组合组成。连接端接通部建立到紧邻的掺杂的半导体层的低电阻的电接通。此外可以理解，连接端接通部优选地借助键合线与接通指(Kontaktfinger)——所谓的引脚——连接。
优选地，连接端接通部布置在由半导体区域或半导体层形成的堆叠的上侧或下侧上。
环绕的凸肩状的边缘分别借助刻蚀工艺
Figure BDA0002021194820000021
产生。优选地，阶梯的深度——即堆叠的上侧与第一边缘之间的间距或者在第一边缘与第二边缘之间的间距——根据刻蚀速率通过相应的刻蚀时间进行控制。
优点在于，借助边缘的结构化可以改善构件特性。尤其可以提高截止电压并且抑制在表面处的漏电流。
换句话说，在200V-3000V的范围内的截止电压的情况下，借助根据本发明的III-V族半导体二极管可以以简单的方式借助比由硅或碳化硅构成的常规的高阻断的二极管更小的接通电阻和更小的单位面积电容产生低的漏电流。
由此，可以实现30kHz直至0.5GHz的开关频率和0.5A/mm2至5A/mm2的电流密度。
另一优点在于，可以比由碳化硅构成的可比较的高阻断的二极管更成本有利地制造III-V族半导体二极管。
根据本发明的III-V族半导体二极管尤其可以用作续流二极管(Freilaufdiode)。
应注意到，根据本发明的III-V族半导体二极管有利地具有1mΩ至200mΩ之间的范围内的小的接通电阻。单位面积的电容处于2pF至100pF之间的范围内。
根据本发明的III-V族半导体二极管的另一优点是直至300℃的耐高温强度。换句话说，III-V族半导体二极管也可以用于热的周围环境中。在此，低的漏电流由于随着上升的温度而指数地上升是特别有助的。
在一种扩展方案中，至少沿堆叠的侧面的一部分在堆叠中构造有通过注入(Implantation)产生的第一隔离层(Isolationsschicht)。隔离层例如构造为非晶化的边缘区域，其中，非晶化例如通过注入氢离子实现。
根据另一扩展方案，至少沿堆叠的侧面的一部分延伸有隔离层。例如借助化学气相沉积(英语chemical vapor desposition，CVD)将氧化层施加到侧面上。优选地，氧化层具有10μm-15μm或20μm-30μm的厚度。
在另一实施方式中，半导体构件包括第一接通层和第二接通层，其中，第二接通层部分地覆盖堆叠的上侧，从而堆叠的上侧构成环绕的第三边缘，该第三边缘具有环绕第二接通层的至少10μm的宽度。第一接通层优选地完全地覆盖堆叠的下侧。
根据另一实施方式，p+区域和n+区域层状地构造，其中，层状的n+区域和层状的p+区域分别与n-层材料锁合(stoffschlüssig)地连接，层状的n+区域具有50-675μm的层厚，层状的p+区域具有大于2μm的层厚，堆叠状的III-V族半导体构件具有第一空穴层，所述第一空穴层具有0.5μm至50μm之间的层厚，并且空穴层布置在n-层内部并且具有1·1013N/cm3至5·1016N/cm3之间的范围内的空穴浓度。
可以理解，可以以不同方式例如通过注入或借助装入外来原子(Fremdatom)产生空穴层并且在空穴层内实现电荷载体的重组。优选地，通过装入铬实现空穴或重组中心。
根据一种扩展方案，空穴层的层厚、空穴层到n-层与p+区域之间的边界面的间距最高是n-层的层厚的一半。
应注意到，空穴层优选地没有构造在空间电荷区域(Raumladungszone)内。优选地，n-层的厚度如此构造，使得空穴层与空间电荷区域间隔开。
在另一实施方式中，p+区域和n+区域层状地构造，其中，层状的n+区域与n-层材料锁合地连接，在n-层与p+层之间布置有掺杂的中间层，该中间层具有1-50μm的层厚和1012-1017cm-3的掺杂剂浓度，并且中间层与n-层并且与p+层材料锁合地连接。
可以理解，中间层与材料锁合地连接的层相比具有至少一个不同的掺杂剂浓度。
优选地，中间层是p掺杂的并且特别优选地包括锌或碳作为掺杂剂。特别优选地，p掺杂的中间层的掺杂剂浓度小于p+区域的掺杂剂浓度，尤其小2倍直至5倍的数量级。
替代地，中间层是n掺杂的并且优选地包括硅和/或锌，其中，n掺杂的中间层的掺杂剂浓度特别优选地比n-区域的掺杂剂浓度小直至100倍。
在一种扩展方案中，III-V族半导体二极管单片地构造，也就是说，各个单片构造的层彼此同样单片地构造。
在另一实施方式中，III-V族半导体二极管包括至少一个半导体键合。
应注意到，表述“半导体键合”与表述“晶圆键合”同义地使用。
在另一实施方式中，在堆叠状的层结构的情况下，在n-层与p掺杂的中间层之间形成半导体键合，该堆叠状的层结构由p+层、p掺杂的中间层、n-层和n+层组成。
在一种实施方式中，由p+层和p掺杂的中间层组成的层结构形成第一部分堆叠，并且由n+层和n-层组成的层结构形成第二部分堆叠。
在一种扩展方案中形成第一部分堆叠，在所述第一部分堆叠中从p+层出发借助外延产生p掺杂的中间层。
优选地，构造为p-层的中间层具有小于1013N/cm-3的掺杂或在1013N/cm-3至1015N/cm-3之间的掺杂。在一种实施方式中，p+层在键合前或在键合后通过磨削工艺(Schleifprozess)减薄到200μm至500μm之间的厚度。
在一种扩展方案中，第一部分堆叠和第二部分堆叠分别单片地构造。
在一种实施方式中形成第二堆叠，在所述第二堆叠中从n-衬底出发将n-衬底与第二堆叠通过另一晶圆键合工艺连接。
在另一工艺步骤中，将n-衬底减薄到所期望的厚度。优选地，n-衬底的厚度处于50μm至250μm之间的范围内。优选地，n-衬底的掺杂处于1013N/cm-3至1015N/cm-3之间的范围内。
晶圆键合的优点在于，可以容易地产生厚的n-层。由此在外延时省去长时间的沉积工艺。借助键合也可以减少在厚的n-层情况下堆叠错误的数量。
在另一扩展方案中，在接合前优选地借助注入离子到第一部分堆叠的表面中、即到p掺杂的中间层中来产生空穴层。
在一种替代的实施方式中，n-衬底具有大于1010N/cm-3且小于1013N/cm-3的掺杂。在该n-衬底中掺杂极其小，n-衬底也可以理解为本征层(intrinsische Schicht)。
在一种扩展方案中，在使n-衬底减薄后借助外延或高剂量注入在n-衬底上产生1018N/cm-3至小于5×1019N/cm-3的范围内的n+层。
可以理解，优选地借助CMP步骤(即借助化学机械抛光)实现使n-衬底减薄。
在另一扩展方案中，在二极管结构的前侧上施加辅助层。接下来，使二极管结构的背侧减薄并且置于载体上。在另一扩展方案中，接下来将辅助层从前侧分离。
在一种实施方式中，将n+衬底的表面和p+层的表面金属化，以便电连接半导体二极管。优选地，半导体二极管的阴极在金属化后与构造为热沉
Figure BDA0002021194820000051
的基底材料锁合地连接。换句话说，阳极在二极管的表面上构造在p+层上。
研究已经表明：借助p-中间层和n-层的确定组合可以实现不同的截止电压。
在第一变型方案中包括：p-中间层具有10μm至25μm之间的厚度并且n-层具有40μm至90μm之间的厚度。得出约900V的截止电压。
在第二变型方案中包括：p-中间层具有25μm至35μm之间的厚度并且n-层具有40μm至70μm之间的厚度。得出约1200V的截止电压。
在第三变型方案中包括：p-中间层具有35μm至50μm之间的厚度并且n-层具有70μm至150μm之间的厚度及70μm得出约1500V的截止电压。
在第一至第三变型方案中的二极管也可以称为潘趣酒二极管(Punsch-Diode)。
在第四变型方案中包括：p-中间层具有10μm至25μm之间的厚度并且n-层具有60μm至110μm之间的厚度。
在第五变型方案中包括：p-中间层具有10μm至25μm之间的厚度并且n-层具有70μm至140μm之间的厚度。
在第六变型方案中包括：p-中间层具有35μm至50μm之间的厚度和n-层具有80μm至200μm之间的厚度。
第四至第六变型方案中的二极管也可以称为“不穿透”二极管(“non-reach-through”-Diode)。
附图说明
接下来参照附图进一步阐述本发明。在此，同类的部分以同样的标志来标记。所示出的实施方式是极其示意性的，也就是说，间距以及横向和纵向的延伸不是按比例的并且——只要未另外说明——互相也不具有能推导的几何关系。在此示出：
图1示出半导体构件的根据本发明的第一实施方式的示意性视图；
图2示出半导体构件的一种根据本发明的实施方式的层顺序的示意截面图；
图3示出半导体构件的根据本发明的第二实施方式的层顺序的示意截面图。
具体实施方式
图1的视图示意地示出根据本发明的堆叠状的III-V族半导体构件10的第一实施方式的立体图。
半导体构件10具有由多个半导体层组成的堆叠100，该堆叠具有矩形的上侧102、矩形的下侧104和连接上侧102与下侧104的侧面106。下侧104大于上侧102。侧面106由四个阶梯状的面组成，从而在侧面106的区域内构造具有第一宽度B1的环绕的凸肩状的第一边缘110和具有第二宽度B2的环绕的凸肩状的第二边缘120。
堆叠100的下侧104完全被第一接通层K1覆盖。第二接通层K2布置在半导体构件10的上侧102上。
在图2的视图中示出半导体构件10的堆叠100的半导体层的层顺序的第一实施方式。
堆叠100沿纵轴线L具有层状的p+区域12、n-层和层状的n+区域，该p+区域具有5·1018-5·1020N/cm3的掺杂剂浓度，该n-层具有1012-1017N/cm3的掺杂剂浓度，该层状的n+区域具有至少1019N/cm3的掺杂剂浓度，其中，每个层具有下侧和上侧。
p+层12构造为具有层厚D1的衬底，其中，p+层12的下侧构成堆叠100的下侧。p+层12的上侧的第一部分构成具有宽度B1的环绕的第一边缘110。在p+层12的上侧的第二部分上布置有n-层14的下侧。n-层14具有层厚D2。n-层的上侧的一部分构成具有宽度B2的环绕的第二边缘130。在n-层14的上侧的第二部分上布置有n+层16的下侧。n+层16具有层厚D3。n+层16的上侧构成堆叠100的上侧。
堆叠100的下侧完全被第一接通层K1覆盖。第二接通层K2面状地构造在堆叠100的上侧的中心区域上，从而堆叠100的上侧(即在此为n+层16)构成具有宽度B3的环绕的凸肩状的第三边缘130。
所有层12、14和16单片地构造并且包括GaAs化合物或由GaAs化合物组成。可选择地并且因此虚线地描绘，堆叠100具有具有层厚D4的空穴层30，其中，空穴层布置在n-层14内部并且相对于n-层14的下侧或p+层12的上侧具有间距A1。
在图3的视图中示出III-V族半导体构件的根据本发明的层顺序的另一实施方式。以下仅阐述与图2的视图的区别。
n+层16构造为衬底层，紧跟着n-层14、具有层厚D5的p或n掺杂的中间层18以及p+层12。
通过注入，堆叠100的邻接侧面的区域从环绕的第一边缘110直至邻接堆叠100的上侧的棱边隔离地构造，并且该区域构成第一隔离层20。
将第二隔离层22(例如氧化物层或者由氧化物层与氮化物层构成的组合)借助化学气相沉积施加到从环绕的第一边缘110直至邻接堆叠100的上侧的棱边的区域内的侧面上。在此，隔离层22可以延伸直至表面102。

Claims (9)

1.一种堆叠状的III-V族半导体构件(10)，所述III-V族半导体构件具有：
堆叠(100)，所述堆叠具有上侧(102)、下侧(104)、侧面(106)以及纵轴线(L)，所述侧面连接所述上侧(102)和所述下侧(104)，所述纵轴线延伸通过所述上侧(102)和所述下侧(104)；其中，
所述堆叠(100)具有p+区域(12)，所述p+区域包括上侧、下侧和5·1018-5·1020N/cm3的掺杂剂浓度；
所述堆叠(100)具有n-层(14)，所述n-层具有上侧和下侧、1012-1017N/cm3的掺杂剂浓度和10-300μm的层厚(D2)；
所述堆叠(100)具有n+区域(16)，所述n+区域具有上侧、下侧和至少1019N/cm3的掺杂剂浓度；
所述p+区域(12)、所述n-层(14)和所述n+区域(16)沿所述堆叠(100)的所述纵轴线(L)以所提及的顺序彼此相继，分别单片地构造并且分别包括GaAs化合物或者分别由GaAs化合物组成；并且
所述n+区域(16)或所述p+区域(12)构造为衬底层；
其特征在于，
所述堆叠(100)在所述侧面(106)的区域内具有环绕的凸肩状的第一边缘(110)和环绕的凸肩状的第二边缘(120)；
所述第一边缘(110)由所述衬底层构成；
所述第二边缘(120)由所述n-层(14)或由邻接所述n-层(14)和所述p+区域(12)的中间层(18)构成；并且
环绕的第一边缘(110)和环绕的第二边缘(120)分别具有至少10μm的宽度(B1、B2)。
2.根据权利要求1所述的堆叠状的III-V族半导体构件(10)，其特征在于，至少沿所述堆叠(100)的所述侧面(106)的一部分在所述堆叠(100)中构造有通过注入产生的第一隔离层(20)。
3.根据权利要求1或2所述的堆叠状的III-V族半导体构件(10)，其特征在于，至少沿所述堆叠(100)的所述侧面(106)的一部分延伸有第二隔离层(22)。
4.根据权利要求1或2所述的堆叠状的III-V族半导体构件(10)，其特征在于，所述半导体构件(10)包括第一接通层(K1)和第二接通层(K2)，其中，所述第二接通层(K2)部分地覆盖所述堆叠(100)的上侧(102)，并且所述堆叠(100)的上侧(102)构成环绕的第三边缘(130)，所述第三边缘具有环绕所述第二接通层(K2)的至少10μm的宽度(B3)。
5.根据权利要求1或2所述的堆叠状的III-V族半导体构件(10)，其特征在于，
所述p+区域(12)和所述n+区域(16)层状地构造；
层状的所述n+区域(16)和层状的所述p+区域(12)分别与所述n-层(14)材料锁合地连接；
层状的所述n+区域(16)具有50-675μm的层厚(D3)；
层状的所述p+区域具有大于2μm的层厚(D1)；并且
所述堆叠状的III-V族半导体构件(10)具有第一空穴层(30)，所述第一空穴层具有0.5μm至50μm之间的层厚(D4)；
其中，所述第一空穴层(30)布置在所述n-层(14)内并且具有1·1013N/cm3至5·1016N/cm3之间的范围内的空穴浓度。
6.根据权利要求5所述的堆叠状的III-V族半导体构件(10)，其特征在于，所述第一空穴层(30)到所述n-层(14)与所述p+区域(12)之间的边界面的间距(A1)最高是所述n-层(14)的层厚(D2)的一半。
7.根据权利要求1或2所述的堆叠状的III-V族半导体构件(10)，其特征在于，
所述p+区域(12)和所述n+区域(16)层状地构造；
层状的所述n+区域(16)与所述n-层(14)材料锁合地连接；并且
在所述n-层(14)与所述p+区域(12)之间布置有掺杂的中间层(18)，所述中间层具有1-50μm的层厚(D5)和1012-1017N/cm-3的掺杂剂浓度；
其中，所述中间层(18)与所述n-层(14)并且与所述p+区域(12)材料锁合地连接。
8.根据权利要求1或2所述的III-V族半导体构件(10)，其特征在于，所述III-V族半导体构件(10)构造为III-V族半导体二极管，其中，所述III-V族半导体二极管单片地构造或具有半导体键合。
9.根据权利要求8所述的III-V族半导体构件(10)，其特征在于，所述半导体键合构成在所述n-层(14)与p掺杂的所述中间层(18)之间。
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