CN108682694B - Iii-v族半导体二极管 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 230000007547 defect Effects 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 8
- -1 GaAs compound Chemical class 0.000 claims abstract description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000009826 distribution Methods 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 150000002736 metal compounds Chemical class 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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Abstract
堆叠状III‑V族半导体二极管,具有至少1019N/cm3掺杂剂浓度的n+层、1012‑1016掺杂剂浓度和10‑300μm厚的n‑层、5·1018‑5·1020掺杂剂浓度和大于2μm厚的p+层,它们以所提及的顺序依次跟随,包括GaAs化合物,n+层或p+层构造为衬底,n‑层下侧与n+层上侧材料锁合连接,n‑层与p+层之间布置掺杂中间层,其具有上侧和下侧,其下侧与n‑层上侧且其上侧与p+层下侧材料锁合连接,中间层与n‑层且与p+层材料锁合地连接且p掺杂,堆叠状III‑V族半导体二极管包括大于0.5μm层厚度的第一缺陷层,其布置在p‑层内且具有1·1013至5·1016N/cm3的缺陷浓度。
Description
技术领域
本发明涉及一种III-V族半导体二极管。
背景技术
由German Ashkinazi的《GaAs Power Devices》,ISBN 965-7094-19-4,第8和9页已知一种耐高压的半导体二极管p+-n-n+。值得期待的是,除了高的耐电压强度,耐高压的半导体二极管不仅具有低的接通电阻,而且在截止区域内具有小的漏电流。
发明内容
在这些背景下,本发明的任务在于,说明一种扩展现有技术的设备。
所述任务通过根据本发明的III-V族半导体二极管解决。以下还给出了本发明的有利的构型。
根据本发明的主题提供一种堆叠状的III-V族半导体二极管,其具有n+层、n-层以及p+层。
n+层具有上侧、下侧、至少1019N/cm3的掺杂剂浓度和10μm至675μm之间、优选50μm至675μm之间、优选50μm至400μm之间的层厚度,其中,n+衬底包括GaAs化合物或由GaAs化合物构成。
n-层具有上侧、下侧、1012-1016N/cm3的掺杂剂浓度和10-300μm的层厚度,并且包括GaAs化合物或由GaAs化合物构成。
p+层具有上侧、下侧、5·1018-5·1020N/cm3的掺杂剂浓度并且包括0.5μm至50μm之间的层厚度,或由GaAs化合物构成。
这些层以所提及的顺序依次并且单片地构造,其中,所述n+层或p+层构造为衬底,并且n-层的下侧与n+层的上侧材料锁合地连接。
在n-层(14)与p+层(18)之间布置有经掺杂的中间层,所述经掺杂的中间层具有1-50μm的层厚度和1012-1017cm-3的掺杂剂浓度,并且所述经掺杂的中间层具有上侧和下侧,其中,中间层的下侧与n-层的上侧材料锁合地连接并且中间层的上侧与p+层的下侧材料锁合地连接。
中间层(16)与n-层并且与p+层材料锁合地连接并且是p掺杂的。
此外,堆叠状的III-V族半导体二极管包括第一缺陷层(Defektschicht)。第一缺陷层具有0.5μm至40μm之间的层厚度,其中,缺陷层布置在p掺杂的中间层以内并且缺陷层具有1·1014N/cm3至5·1017N/cm3之间的范围内的缺陷浓度。以下同义地使用概念“中间层”与“p层”。
需要说明的是,借助液相外延或借助MOVPE(金属有机物气相外延)设备制造这些层。
可以理解,可以以不同的方式、例如通过注入或借助杂质原子(Fremdatom)的嵌入(Einbau)制造缺陷层,并且在缺陷层以内实现电荷载体的复合(Rekombination)。
需要说明的是,缺陷层尽可能地不构造在空间电荷区以内。优选地,p层的厚度如此构造,使得缺陷层与空间电荷区隔开。
优点是:借助缺陷层的嵌入可以降低截止区域内的漏电流的大小,而在导通区域内几乎不影响构件特性。尤其在截止区域内在1000V以上的电压的情况下不利地使漏电流变得可察觉到(bemerkbar)。
此外,漏电流随着温度强烈地上升。通过缺陷层的嵌入可以使漏电流相对于没有缺陷层的二极管降低超过一个数量级。此外,制造过程显著更稳健,也就是说,对高的背景掺杂不敏感。
另一优点是,以根据本发明的III-V族半导体二极管可以以简单的方式产生低的漏电流,所述二极管在200V-3300V的范围内的截止电压的情况下具有比由Si或SiC构成的传统的高截止的二极管在单位面积上更小的接通电阻和更小的电容。由此,能够实现30kHz直至0.5GHz的开关频率和0.5A/mm2至5A/mm2的电流密度。
另一优点是,可以比可比较的由SiC构成的高截止二极管更成本有利地制造III-V族半导体二极管。
根据本发明的III-V族半导体二极管尤其可以使用为空载二极管(Freilaufdiode)。
需要说明的是,根据本发明的III-V族半导体二极管当前具有1mOhm至200mOhm之间的范围内的小的接通电阻。单位面积的电容处于2pF至100pF之间的范围内。
根据本发明的III-V族半导体二极管的另一优点是,直至300℃的高的耐热性。换句话说,也可以在热的周围环境中使用III-V族半导体二极管。在此,基于随着上升的温度指数地上升的低漏电流是特别有帮助的。
在一种扩展方案中,缺陷浓度处于1·1013N/cm3至5·1016N/cm3之间的范围内。在另一扩展方案中,缺陷层的厚度是0.5μm至40μm之间。
在第一实施方式中,第一缺陷层具有相对于p-层的下侧的间距,所述间距是p层的层厚度的至少一半。
根据一种扩展方案,半导体二极管具有第二缺陷层,其中,第二缺陷层具有0.5μm至40μm之间的范围内、优选2μm至10μm之间的范围内的层厚度和1·1013N/cm3至5·1016N/cm3之间的范围内的缺陷浓度,并且具有相对于p层的上侧的间距,所述间距是p层的层厚度的最高一半。优选地,第一缺陷层的缺陷浓度与第二缺陷层的缺陷浓度不同。
在另一实施方式中,第一缺陷层和/或第二缺陷层具有至少一个第一层区域和一个第二层区域,所述第一层区域具有第一缺陷浓度,所述第二层区域具有第二缺陷浓度,并且尤其在第一缺陷层的和/或第二缺陷层的层厚度上遵循统计学上的优选高斯分布。换句话说,缺陷浓度沿着缺陷层的厚度是不同的。
根据另一实施方式,第一缺陷层和/或第二缺陷层包括铬和/或铟和/或铝。优选地,将铬在外延过程期间嵌入到n-层中。嵌入铬的优点是:在不中断外延过程的情况下,借助铬的浓度可以成本有利地并且以简单的方式调节杂质的数目并且由此调节复合中心的数目。
在另一实施方式中,在第一缺陷层中和/或第二缺陷层中通过注入原子或分子或通过电子束辐射产生杂质。优选地,使用具有相应的能量和剂量的H2分子用于产生杂质。
根据另一实施方式,由p+层、p掺杂的中间层、n-层和n+层构成的堆叠状的层结构的总高度是150-800μm之间。
根据一种替代的实施方式,由p+层、p掺杂的中间层、n-层和n+层构成的堆叠状的层结构具有矩形的或正方形的表面或者圆的(rund)、优选椭圆的(oval)或圆形的表面,所述矩形的或正方形的表面具有1mm至10mm之间的边长。
在一种扩展方案中,III-V族半导体二极管单片地构造,也就是说这些各个单片地构造的层彼此同样单片地构造。在另一实施方式中,III-V族半导体二极管包括至少一个半导体接合(Halbleiterbond)。
应说明,将措辞“半导体接合”与措辞“晶圆接合”同义地使用。
在另一实施方式中,在堆叠状的层结构情况下的半导体接合构造在n-层与p掺杂的中间层之间,所述堆叠状的层结构由p+衬底、p掺杂的中间层、n-层和n+层构成。
在一种实施方式中,由p+层和p掺杂的中间层构成的层结构构成第一部分堆叠,并且由n+层和n-层构成的层结构构成第二部分堆叠。
在一种扩展方案中,构造第一部分堆叠,在所述第一部分堆叠中由p+层开始借助外延法制造p掺杂的中间层。
优选地,构造为p-层的中间层具有小于1013N/cm-3的掺杂或1013N/cm-3至1015N/cm-3的掺杂。在一种实施方式中,将p+层在接合之前或之后通过磨削过程削薄到200μm至500μm之间的厚度。
在一种扩展方案中,第一部分堆叠和第二部分堆叠分别单片地构造。
在一种实施方式中,构造第二堆叠,在所述第二堆叠中,从n-衬底出发使n-衬底与第二堆叠通过另一晶圆接合过程连接。
在另一过程步骤中,将n-衬底削薄到所期望的厚度。优选地,n-衬底的厚度处于50μm至250μm之间的范围中。优选地,n-衬底的掺杂处于1013N/cm-3至1015N/cm-3之间的范围中。
晶圆接合的优点是:n-层的厚度可以容易地制造。由此省去在外延时的长的沉积过程。借助接合也可以使在厚的n-层的情况下的堆叠错误的数量减小。
在另一扩展方案中,在接合之前优选借助将离子注入到第一部分堆叠的表面中、也就是说注入到p掺杂的中间层中来制造缺陷层。
在一种替代的实施方式中,n-衬底具有大于1010N/cm-3且小于1013N/cm-3的掺杂。其中,掺杂极度小,n-衬底也可以理解为本征(intrinsisch)层。
在一种扩展方案中,在n-衬底的削薄之后借助外延法或高掺杂注入法在n-衬底上制造n+层,所述n+层处于1018N/cm-3至5×1019N/cm-3的范围中。
可以理解,n-衬底的削薄优选借助CMP步骤、也就是说借助化学机械研磨实现。
在另一扩展方案中,在二极管结构的前侧上涂覆辅助层。随后削薄二极管结构的背侧并且安置在载体上。在另一扩展方案中,随后溶解前侧的辅助层。
研究已经显示,借助p-中间层和n-层的确定组合能够实现不同的截止电压。
在第一变型方案中,p-中间层具有10μm至25μm之间的厚度并且n-层具有40μm至90μm之间的厚度。得出大约900V的截止电压。
在第二变型方案中,p-中间层具有25μm至35μm之间的厚度并且n-层具有40μm至70μm之间的厚度。得出大约1200V的截止电压。
在第三变型方案中,p-中间层具有35μm至50μm之间的厚度并且n-层具有70μm至150μm之间的厚度。得出大约1500V的截止电压。
第一至第三变型方案中的二极管可以称为潘趣酒二极管(Punsch-Diode)。
在第四变型方案中,p-中间层具有10μm至25μm之间的厚度并且n-层具有60μm至110μm之间的厚度。
在第五变型方案中,p-中间层具有10μm至25μm之间的厚度并且n-层具有70μm至140μm之间的厚度。
在第六变型方案中,p-中间层具有35μm至50μm之间的厚度并且n-层具有80μm至200μm之间的厚度。
第四至第六变型方案中的二极管也可以称为“不透穿”二极管(“non-reach-through”-Diode)。
根据另一实施方式,半导体二极管的p+层通过连接接通层替代,其中,连接接通层包括金属或金属化合物,或者由金属或金属化合物构成,并且构成肖特基接通部。
附图说明
以下参照附图进一步阐述本发明。在此,同类的部分以同样的标志来标记。所显示的实施方式是强烈示意性的,也就是说,间距以及横向和纵向的延伸不是按比例的并且——只要未另外说明——互相也不具有能推导的几何关系。在此示出:
图1:III-V族半导体二极管的根据本发明的第一实施方式的视图;
图2:III-V族半导体二极管的根据本发明的第二实施方式的视图;
图3:图1或图2中的III-V族半导体二极管的俯视图;
图4:III-V族半导体二极管的根据本发明的第三实施方式的视图;
图5:III-V族半导体二极管的根据本发明的第四实施方式的视图。
具体实施方式
图1的图示出根据本发明的堆叠状的III-V族半导体二极管10的第一实施方式的视图,所述半导体二极管具有作为衬底的n+层12、与n+层12材料锁合地连接的低掺杂的n-层14和与n-层14材料锁合地连接的p掺杂的中间层15和与中间层材料锁合地连接的p+层18以及第一接通部20和第二接通部22。在p层15以内布置有第一缺陷层16。
第一接通部20与n+层12的下侧材料锁合地连接,而第二接通部22与p+层18的上侧材料锁合地连接。
n+层12是强n掺杂的并且具有1019N/cm3的掺杂剂浓度。n+层12的层厚度D1处于100μm至675μm之间。
n-层14是以1012-1016N/cm3的掺杂剂浓度低n掺杂的并且具有10-300μm的层厚度D2。
p中间层15是以1012-1017N/cm3的掺杂剂浓度低p掺杂的并且具有1μm至50μm的层厚度D5。
p+层18是以1019N/cm3的掺杂剂浓度强p掺杂的并且具有大于2μm的层厚度D3。
第一缺陷层16具有0.5μm至10μm之间的范围内的层厚度D41和1·1013N/cm3至5·1016N/cm3之间的范围内的缺陷密度(Defektdichte)。
图2的图中示出III-V族半导体二极管的第二实施方式,其中,与图1的图的区别在于,p+层18构造为衬底,在所述衬底上跟随其他层。
图3的图中示出根据本发明的III-V族半导体二极管的图1中示出的第一实施方式的俯视图。以下仅阐述与图1的图的区别。
III-V族半导体二极管10的由n+衬底12、包括缺陷层16的n-层14和p+层18构成的堆叠状的层结构100具有矩形的周边,并且因此也具有矩形的表面,所述矩形的表面具有边长L1和L2。布置在层序列100的表面上的接通面22仅覆盖表面的部分。
在另一未示出的实施方式中,堆叠状的层结构100的角是圆的,以便避免在高压情况下的场强峰值。
在另一未示出的实施方式中,堆叠状的层结构100的表面是圆的。由此,可以特别有效地降低场强的过高。优选地,表面是圆形的或椭圆形的。
在图4的附图中示出图1中的III-V族半导体二极管的一种扩展方案,其中,半导体二极管10的p中间层15区别于第一实施方式具有第二缺陷层24,所述第二缺陷层具有厚度42。
第二缺陷层24的层厚度D42是0.5μm至40μm之间。缺陷浓度(Defektkonzentration)处于1·1013N/cm3至5·1016N/cm3之间。相对于p层的上侧的间距具有中间层的层厚度D5的最高一半。
图5的图中示出图2中的III-V族半导体二极管的一种扩展方案,其中,所述半导体二极管10的p层15区别于第二实施方式具有第二缺陷层24。
Claims (12)
1.一种堆叠状的III-V族半导体二极管(10),其具有:
n+层(12),其具有上侧、下侧、至少1019N/cm3的掺杂剂浓度和10-675μm的层厚度(D1),其中,所述n+层(12)包括GaAs化合物或者由GaAs化合物构成,
n-层(14),其具有上侧和下侧、1012-1016N/cm3的掺杂剂浓度、10-300μm的层厚度(D2),并且包括GaAs化合物或者由GaAs化合物构成,
p+层(18),其具有上侧、下侧、5·1018-5·1020N/cm3的掺杂剂浓度和大于2μm的层厚度(D3),并且包括GaAs化合物或者由GaAs化合物构成,其中,
这些层以所提及的顺序依次并且单片地构造,所述n+层(12)或所述p+层(18)构造为衬底并且
所述n-层(14)的下侧与所述n+层(12)的上侧材料锁合地连接,
在所述n-层(14)与所述p+层(18)之间布置有经掺杂的中间层(15),所述经掺杂的中间层具有1-50μm的层厚度(D5)和1012-1017N/cm3的掺杂剂浓度,并且所述经掺杂的中间层具有上侧和下侧,并且所述中间层(15)的下侧与所述n-层(14)的上侧材料锁合地连接,并且所述中间层的上侧与所述p+层(18)的下侧材料锁合地连接,
其中,所述中间层(15)与所述n-层(14)并且与所述p+层(18)材料锁合地连接并且是p掺杂的,
其特征在于,所述堆叠状的III-V族半导体二极管(10)具有第一缺陷层(16),所述第一缺陷层具有0.5μm至40μm之间的层厚度(D41),
其中,所述第一缺陷层(16)布置在所述中间层以内,
所述第一缺陷层(16)具有1·1013N/cm3至5·1016N/cm3之间的范围内的缺陷浓度。
2.根据权利要求1所述的III-V族半导体二极管(10),其特征在于,所述第一缺陷层(16)具有相对于所述中间层(15)的下侧的间距,所述间距是所述中间层(15)的层厚度(D5)的至少一半。
3.根据权利要求1或2所述的III-V族半导体二极管(10),其特征在于,所述半导体二极管(10)具有第二缺陷层(24),其中,所述第二缺陷层(24)具有0.5μm至40μm之间的层厚度(D42)和1·1013N/cm3至5·1016N/cm3之间的缺陷浓度,并且具有相对于所述中间层的上侧的间距,所述间距是所述中间层(15)的层厚度(D5)的最高一半。
4.根据权利要求3所述的III-V族半导体二极管(10),其特征在于,所述第一缺陷层(16)和/或第二缺陷层(24)分别具有一个具有第一缺陷浓度的第一层区域和一个具有第二缺陷浓度的第二层区域。
5.根据权利要求3所述的III-V族半导体二极管(10),其特征在于,所述缺陷浓度在所述第一缺陷层(16)的和/或第二缺陷层(24)的层厚度(D41,D42)上遵循统计学分布。
6.根据权利要求3所述的III-V族半导体二极管(10),其特征在于,所述第一缺陷层(16)和/或所述第二缺陷层(24)包括铬和/或铟和/或铝。
7.根据权利要求1或2所述的III-V族半导体二极管(10),其特征在于,由所述p+层(18)、所述n-层(14)、所述p掺杂的中间层和所述n+层(12)构成的堆叠状的层结构(100)的总高度最高是150-800μm。
8.根据权利要求1或2所述的III-V族半导体二极管(10),其特征在于,由所述p+层(18)、所述n-层(14)、所述p掺杂的中间层(15)和所述n+层(12)构成的堆叠状的层结构(100)具有矩形的表面,所述矩形的表面具有1mm至10mm之间的边长(L1,L2)的。
9.根据权利要求1或2所述的III-V族半导体二极管(10),其特征在于,由所述p+层(18)、所述n-层(14)、所述p掺杂的中间层(15)和所述n+层(12)构成的堆叠状的层结构(100)具有圆的或椭圆的表面。
10.根据权利要求1或2所述的III-V族半导体二极管(10),其特征在于,所述半导体二极管(10)的p+层(18)通过连接接通层替代,其中,所述连接接通层包括金属或金属化合物或者由金属或金属化合物构成并且构成肖特基接通部。
11.根据权利要求1或2所述的III-V族半导体二极管(10),其特征在于,所述III-V族半导体二极管(10)单片地构造或具有半导体接合。
12.根据权利要求11所述的III-V族半导体二极管(10),其特征在于,所述半导体接合构造在所述p+层(18)与所述n-层(14)之间。
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