CN110311664A - 驱动装置以及功率模块 - Google Patents
驱动装置以及功率模块 Download PDFInfo
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Abstract
本发明的目的在于提供能够使过电流保护以及短路保护相辅相成的技术。LVIC(26)具备:过电流检测部(26a),其对流过负载(11)以及半导体开关元件(6)的第1电流是否异常进行检测;以及短路检测部(26b),其对不流过负载(11)而流过半导体开关元件(6)的第2电流是否异常进行检测。LVIC(26)基于过电流检测部(26a)的检测结果以及短路检测部(26b)的检测结果,将半导体开关元件(6)断开。
Description
技术领域
本发明涉及对半导体开关元件进行驱动的驱动装置、以及具备它们的功率模块。
背景技术
就使用了半导体开关元件的功率半导体装置而言,构成为在通过去饱和(Desat)方式的检测等而检测出短路的情况下,将该半导体开关元件断开而对电路进行保护。另外,提出了在逆变器装置等功率模块设置用于对电动机等负载进行控制的过电流保护电路(例如专利文献1)。
专利文献1:日本特开2015-005866号公报
在分流方式以及感测方式的过电流检测中,为了抑制误动作,通常使用插入了噪声滤波器的电路。但是,在这些方式中,由于噪声滤波器,难以设计迅速将半导体开关元件断开的电路。因此,存在无法适当地设计功率芯片的短路耐量,阻碍功率芯片的成本削减的问题。另外,在去饱和方式的短路检测中不需要插入滤波器,因而能够迅速将半导体开关元件断开,但存在以下问题,即,功率芯片的波动大,电流检测的精度低。
发明内容
因此,本发明是鉴于上述这样的问题而提出的,其目的在于提供能够使过电流保护以及短路保护相辅相成的技术。
本发明涉及的驱动装置对与负载连接的半导体开关元件进行驱动,具备:过电流检测部,其对流过所述负载以及所述半导体开关元件的第1电流是否异常进行检测;以及短路检测部,其对不流过所述负载而流过所述半导体开关元件的第2电流是否异常进行检测,所述驱动装置基于所述过电流检测部的检测结果以及所述短路检测部的检测结果,将所述半导体开关元件断开。
发明的效果
根据本发明,具备过电流检测部和短路检测部,基于过电流检测部的检测结果以及短路检测部的检测结果将半导体开关元件断开。根据这样的结构,能够使过电流保护以及短路保护相辅相成。
附图说明
图1是针对具备实施方式1涉及的驱动装置的半导体装置,示出其结构的电路图。
图2是表示实施方式1涉及的短路检测部的结构的电路图。
图3是针对具备实施方式1涉及的驱动装置的半导体装置,示出其动作的时序图。
图4是针对具备实施方式2涉及的驱动装置的半导体装置,示出其动作的时序图。
图5是表示实施方式3涉及的功率模块的结构的电路图。
标号的说明
1、6半导体开关元件,11负载,26 LVIC,26a过电流检测部,26b短路检测部,41封装件,42连接部分。
具体实施方式
<实施方式1>
图1是针对具备本发明实施方式1涉及的驱动装置的半导体装置,示出其结构的电路图。
图1的半导体装置具备:半导体开关元件1、2、6、7;负载11;分流电阻12;电阻13;电容器14;电源15;HVIC(High Voltage Integrated Circuit)21、22,它们是高电位侧栅极驱动器;以及LVIC(Low Voltage Integrated Circuit)26、27,它们是低电位侧栅极驱动器。
半导体开关元件1、2、6、7例如是MOSFET(Metal Oxide Semiconductor FieldEffect Transistor)、HEMT(High Electron Mobility Transistor)以及IGBT(InsulatedGate Bipolar Transistor)等。负载11例如是电动机等。
半导体开关元件1的源极端子与半导体开关元件6的漏极端子彼此连接,上述源极端子以及漏极端子与负载11连接。半导体开关元件6的栅极端子与对半导体开关元件6进行驱动的LVIC 26连接,半导体开关元件6的源极端子经由分流电阻12与电源15的负极(低电位)连接。半导体开关元件1的栅极端子与对半导体开关元件1进行驱动的HVIC 21连接,半导体开关元件1的漏极端子与电源15的正极(高电位)连接。即,半导体开关元件1连接在半导体开关元件6与高电位之间。
与半导体开关元件1、6、HVIC 21以及LVIC 26的连接同样地,半导体开关元件2、7、HVIC 22以及LVIC 27也进行连接。
从半导体开关元件6输出的电信号经过电阻13和向电容器14的分支点而输入至LVIC 26。如上所述地构成的电阻13以及电容器14作为低通滤波器起作用。
作为驱动半导体开关元件6的驱动装置的LVIC 26具备过电流检测部26a、短路检测部26b以及作为驱动电路的驱动部26c。
过电流检测部26a通过分流方式的检测,对流过负载11以及半导体开关元件6的第1电流是否异常进行检测。在本实施方式1中,过电流检测部26a对分流电阻12的电压进行检测,基于该电压,对流过负载11以及半导体开关元件6的第1电流进行检测,其中,在该分流电阻12流过通过上述的低通滤波器而去除了噪声的电流。
过电流检测部26a通过例如未图示的比较器,对检测到的第1电流是否大于或等于阈值进行判定。过电流检测部26a在第1电流大于或等于阈值的情况下判定为第1电流异常,在第1电流比阈值小的情况下判定为第1电流正常。此外,过电流检测部26a也可以通过例如感测方式的检测而对第1电流是否异常进行检测,而不是以上所说明的分流方式的检测。
驱动部26c在通过过电流检测部26a而检测到第1电流异常的情况下,通过输出将半导体开关元件6断开的栅极信号,从而将半导体开关元件6断开。
在如上所述地构成的本实施方式1中,实现了在流过负载11以及半导体开关元件6的第1电流异常的情况下对电路进行保护的过电流保护模式。此外,在过电流保护模式中难以作出断开时间小于或等于滤波时间这样的电路设计。但是,该模式是基于经过负载11的电流路径的第1电流的模式,在半导体开关元件6的漏极-源极之间,仅施加由半导体开关元件6的I-V特性引起的电压、例如0.1~2.31V左右的电压。因此,与接下来说明的短路模式相比较,半导体开关元件6处产生的损耗低,因而不需要以高速进行断开。
短路检测部26b通过去饱和方式的检测,对不流过负载11而流过半导体开关元件6的第2电流是否异常进行检测。
图2是表示本实施方式1涉及的短路检测部26b的结构与驱动部26c的电路图。短路检测部26b具备电阻31、32、比较器33、35、电容器34、36、计时器37以及NAND电路38。
半导体开关元件6的漏极电压通过电阻31、32而被分压。比较器33对电阻31、32的分压是否大于或等于与电容器34的电压对应的阈值TH1进行判定。
比较器35对LVIC 26的驱动部26c的输出、即半导体开关元件6的栅极电压是否大于或等于与电容器36的电压对应的阈值TH2进行判定。此外,在图2中,比较器35对驱动部26c的输出是否大于或等于阈值TH2进行判定,但并不限于此,也可以对驱动部26c的输入是否大于或等于阈值TH2进行判定。
在通过计时器37而使比较器35的输出与比较器33的输出取得了同步的状态下,表示比较器33的判定结果的输出以及表示比较器35的判定结果的输出被输入至NAND电路38。在本实施方式1中,构成为在第2电流正常的情况下,将电阻31、32的分压低于阈值TH1时的比较器33的输出以相对于LVIC 26的输出超过阈值TH2时的比较器35的输出,通过计时器37而延迟了一定时间的状态输入至NAND电路38。此外,在以下的说明中,也将通过计时器37而延迟的一定时间记述为“滤波时间”。
NAND电路38对通过计时器37而取得了同步的比较器33的输出以及比较器35的输出进行NAND运算,将其运算结果作为第2电流是否异常的检测结果向驱动部26c输出。
驱动部26c在通过短路检测部26b而检测到第2电流异常的情况下,输出将半导体开关元件6断开的栅极信号,由此将半导体开关元件6断开。这里,如果是在不具备短路检测部26b的电路中,第2电流异常即发生了短路,则产生下述等问题,即,将电源15的电压、例如大于或等于300V的高电压施加到半导体开关元件6的漏极-源极之间,在半导体开关元件6产生大的损耗,温度上升。
与此相对,本实施方式1涉及的LVIC 26具备无滤波器的短路检测部26b,因而在发生短路时,与在半导体开关元件6产生问题的时间相比更早地将半导体开关元件6断开。这样,在本实施方式1中,实现了在不流过负载11而流过半导体开关元件6的第2电流异常的情况下对电路进行保护的短路保护模式。此外,在短路保护模式中,只要能够相对于大于或等于100V左右的极高的电压对电路进行保护即可,因而不需要高的检测精度。
图3是表示本实施方式1涉及的半导体装置的短路检测的动作的时序图。在图3中,实线示出在正常动作时、即第2电流正常时的半导体装置的动作,双点划线示出在异常动作时、即第2电流异常时的半导体装置的动作。此外,电压Vds是漏极电压的由电阻31、32形成的分压。
首先,对正常动作时进行说明。在正常动作时,从LVIC 26的输出即栅极电压Vg超过阈值TH2的时刻t1起至经过了滤波时间为止,进行半导体开关元件6、7的导通,半导体开关元件6的漏极电压以及电压Vds降低。
将包含从时刻t2起至半导体开关元件6、7下一次成为截止的时刻以内的时刻t3为止的期间在内的期间设定为判定期间,该时刻t2是从时刻t1起经过了滤波时间的时刻。在正常动作时的判定期间,判定为电压Vds比阈值TH1小。此外,将阈值TH1设定为大于或等于接通时的电压Vds和导通时在电压Vds产生的噪声电压的合计电压。在正常动作时的判定期间,对NAND电路38输入High(高)信号以及Low(低)信号,NAND电路38将表示第2电流正常的High信号向驱动部26c输出。驱动部26c如果从NAND电路38接收到High信号,则维持半导体开关元件6的接通。
接下来,对异常动作时进行说明。在异常动作时的判定期间,判定为电阻31、32的分压大于或等于阈值TH1。在异常动作时的判定期间,对NAND电路38输入High信号以及High信号,NAND电路38将表示第2电流异常的Low信号向驱动部26c输出。驱动部26c如果从NAND电路38接收到Low信号,则将半导体开关元件6断开。
如上所述地构成的LVIC 26基于过电流检测部26a的检测结果以及短路检测部26b的检测结果而将半导体开关元件6断开。由此,能够与需要滤波时间以上的时间的过电流保护模式相比,更早地通过短路保护模式而将半导体开关元件6断开。因此,能够实现将得到功率芯片的短路耐量的时间提前的设计,因而能够实现接通电压的降低、以及电路的可靠性的提高。另外,能够通过过电流保护模式而实现高精度的电流检测以及保护。进而,能够通过将过电流检测部26a以及短路检测部26b设置于LVIC 26,从而实现芯片尺寸的削减以及成本降低。
另外,在本实施方式1中,LVIC 26在从半导体开关元件6的栅极电压超过阈值的时刻起经过了预先确定的时间(在这里是滤波时间)的时刻,在基于半导体开关元件6的漏极电压的电压(在这里是电压Vds)大于或等于阈值的情况下,检测为第2电流异常。由此,能够对过电流保护以及短路保护适当地进行控制,以使得过电流保护以及短路保护适当地相辅相成。
此外,半导体开关元件6优选包含碳化硅(SiC)、氮化镓(GaN)等宽带隙半导体。能够通过以上述方式构成半导体开关元件6,从而降低低接通电压,削减系统损耗。其结果,能够降低每个单元的接通电阻,因而能够实现系统损耗的削减、芯片尺寸的缩小以及成本的降低。
<实施方式2>
图4是表示本发明的实施方式2涉及的半导体装置的动作的时序图。以下,对本实施方式2涉及的结构要素中的与上述的结构要素相同或者类似的结构要素标注相同的参照标号,主要对不同的结构要素进行说明。
本实施方式2涉及的短路检测部26b基于半导体开关元件6的栅极电压和半导体开关元件6的镜像期间,对第2电流是否异常进行检测。例如,如图4所示,短路检测部26b也可以在半导体开关元件6的栅极电压Vg从升高的时刻起至变得与阈值TH3相等的时刻为止的时间T小于包含镜像期间mt的时间Tsc的情况下,检测为第2电流异常。就上述短路检测部26b而言,能够使用例如国际公开第2014/115272号所公开的电路等。另外,例如短路检测部26b也可以在半导体开关元件6的栅极电压Vg在半导体开关元件6的镜像期间mt内的时刻大于或等于阈值TH3的情况下,检测为第2电流异常。
根据上述这样的结构,即使不设置此前在实施方式1设置的漏极端子与LVIC 26之间的配线,也能够与实施方式1同样地实现对第2电流是否异常进行检测的短路检测部26b。因此,能够期待装置的成本降低。此外,就以上述方式构成的短路检测部26b而言,由于镜像电压乃至镜像期间mt存在波动,因此检测精度较低,但如在实施方式1所说明的那样,对于短路检测部26b,检测精度也可以以一定程度较低。
<实施方式3>
图5是表示本发明的实施方式3涉及的功率模块的结构的俯视图。以下,对本实施方式3涉及的结构要素中的与上述的结构要素相同或者类似的结构要素标注相同的参照标号,主要对不同的结构要素进行说明。
图5的功率模块具备LVIC 26、1个封装件41以及多个半导体开关元件6。封装件41将LVIC 26和多个半导体开关元件6覆盖,而且,将多个半导体开关元件6与LVIC 26之间的连接部分42覆盖。由此,能够在封装件41内部,将半导体开关元件6的漏极电压信号输入至LVIC 26。因此,即使将本实施方式3涉及的功率模块的外部引脚的绝缘间隔设为比将外部引脚设置于基板之上的功率模块的外部引脚的绝缘间隔窄,也能够维持相对于高电压的耐性。其结果,能够实现功率模块的小型化以及成本的降低。
此外,本发明能够在本发明的范围内对各实施方式自由地进行组合,或对各实施方式适当地进行变形、省略。
Claims (8)
1.一种驱动装置,其对与负载连接的半导体开关元件进行驱动,具备:
过电流检测部,其对流过所述负载以及所述半导体开关元件的第1电流是否异常进行检测;以及
短路检测部,其对不流过所述负载而流过所述半导体开关元件的第2电流是否异常进行检测,
所述驱动装置基于所述过电流检测部的检测结果以及所述短路检测部的检测结果,将所述半导体开关元件断开。
2.根据权利要求1所述的驱动装置,其中,
所述短路检测部通过去饱和方式的检测,对所述第2电流是否异常进行检测。
3.根据权利要求2所述的驱动装置,其中,
所述短路检测部在从所述半导体开关元件的栅极电压超过阈值的时刻起经过了预先确定的时间的时刻,在基于所述半导体开关元件的漏极电压的电压大于或等于阈值的情况下,检测为所述第2电流异常。
4.根据权利要求1所述的驱动装置,其中,
所述短路检测部基于所述半导体开关元件的栅极电压和所述半导体开关元件的镜像期间,对所述第2电流是否异常进行检测。
5.根据权利要求2至4中任一项所述的驱动装置,其中,
所述过电流检测部通过分流方式或者感测方式的检测,对所述第1电流是否异常进行检测。
6.根据权利要求1至5中任一项所述的驱动装置,其中,
所述半导体开关元件包含宽带隙半导体。
7.一种功率模块,其具备:
权利要求1至6中任一项所述的驱动装置;
所述半导体开关元件;以及
封装件,其将所述半导体开关元件的漏极端子与所述驱动装置之间的连接部分覆盖。
8.根据权利要求7所述的功率模块,其中,
所述半导体开关元件与低电位连接,
所述功率模块还具备与所述负载连接,连接在所述半导体开关元件与高电位之间的其他半导体开关元件。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008141841A (ja) * | 2006-11-30 | 2008-06-19 | Denso Corp | 過電流保護回路 |
CN102549925A (zh) * | 2009-07-23 | 2012-07-04 | 日立汽车系统株式会社 | 半导体元件控制装置、车载用电机系统 |
CN104937839A (zh) * | 2013-01-23 | 2015-09-23 | 三菱电机株式会社 | 半导体元件的驱动装置、半导体装置 |
US20160124037A1 (en) * | 2014-10-30 | 2016-05-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Short-circuit detection circuits, system, and method |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3883925B2 (ja) * | 2002-07-30 | 2007-02-21 | 三菱電機株式会社 | 電力用半導体素子の駆動回路 |
JP5780145B2 (ja) * | 2011-12-12 | 2015-09-16 | トヨタ自動車株式会社 | スイッチング素子駆動回路及びそれを備える駆動装置 |
TWI477788B (zh) * | 2012-04-10 | 2015-03-21 | Realtek Semiconductor Corp | 偵測發光二極體短路的方法及其裝置 |
JP6003819B2 (ja) | 2013-06-20 | 2016-10-05 | 株式会社デンソー | トランジスタ駆動回路 |
WO2015033449A1 (ja) | 2013-09-06 | 2015-03-12 | 三菱電機株式会社 | 半導体装置、半導体スイッチング素子の駆動装置 |
WO2015114788A1 (ja) | 2014-01-31 | 2015-08-06 | 株式会社日立製作所 | 半導体素子の保護回路 |
US9825625B2 (en) * | 2014-07-09 | 2017-11-21 | CT-Concept Technologie GmbH | Multi-stage gate turn-off with dynamic timing |
JP6320875B2 (ja) * | 2014-08-25 | 2018-05-09 | ルネサスエレクトロニクス株式会社 | 半導体装置、電力制御装置および電子システム |
JP6591220B2 (ja) | 2015-07-15 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置および電力制御装置 |
JP6805496B2 (ja) | 2016-01-15 | 2020-12-23 | 富士電機株式会社 | 半導体装置 |
JP6707873B2 (ja) | 2016-01-26 | 2020-06-10 | 株式会社デンソー | 車両用負荷駆動制御装置 |
JP2017212583A (ja) | 2016-05-25 | 2017-11-30 | 株式会社デンソー | 半導体素子の保護回路 |
-
2018
- 2018-03-20 JP JP2018051893A patent/JP7305303B2/ja active Active
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008141841A (ja) * | 2006-11-30 | 2008-06-19 | Denso Corp | 過電流保護回路 |
CN102549925A (zh) * | 2009-07-23 | 2012-07-04 | 日立汽车系统株式会社 | 半导体元件控制装置、车载用电机系统 |
CN104937839A (zh) * | 2013-01-23 | 2015-09-23 | 三菱电机株式会社 | 半导体元件的驱动装置、半导体装置 |
US20160124037A1 (en) * | 2014-10-30 | 2016-05-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Short-circuit detection circuits, system, and method |
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