CN110310923A - 功率元件的制造方法及其结构 - Google Patents

功率元件的制造方法及其结构 Download PDF

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CN110310923A
CN110310923A CN201910586768.4A CN201910586768A CN110310923A CN 110310923 A CN110310923 A CN 110310923A CN 201910586768 A CN201910586768 A CN 201910586768A CN 110310923 A CN110310923 A CN 110310923A
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silicon wafer
layer
isolated material
semiconductor element
power component
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CN110310923B (zh
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李怡慧
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Abstract

一种功率元件的制造方法及其结构，用以解决现有功率元件需独立封装及焊板的问题。其包括：在一个硅晶圆的正面形成多个间隔排列的半导体元件层；在该硅晶圆的正面挖设多个沟槽以隔开多个半导体元件层；在各沟槽中填充一种第一隔离材料；研磨该硅晶圆的背面至该多个第一隔离材料裸露；在该硅晶圆背面且相对该多个半导体元件层的区域附著多个金属层；各自独立的多个导线架分别电性连接该多个金属层。本发明另包括该功率元件结构。

Description

功率元件的制造方法及其结构
技术领域
本发明关于一种半导体制程，尤其是一种简化制程且安装快速的功率元件的制造方法及其结构。
背景技术
功率元件用于开关切换控制及电能传输转换的电子零组件，例如：金属氧化物半导体场效电晶体(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)、二极体(Diodes)、绝缘闸双极电晶体(Insulated Gate Bipolar Transistor，IGBT)等。在使用多个独立功率元件之前，必须将各个功率元件连接在各自独立的导线架(Lead Frame)上，再连接导线引脚并进行保护封装，以避免该多个独立功率元件形成共汲极(如：MOSFET)或共集极(如：IGBT)结构。
请参照第1图所示，其为一种现有功率元件9的制造过程，先在一个基板91的上表面堆叠氧化物、半导体等材质，形成彼此之间分隔的多个半导体元件92，再将该多个半导体元件92连同该基板91，经由背面研磨(Grinding)及切割(Dicing)制程分离为多个独立的晶粒93，各晶粒93再通过焊线(Bonding)、封胶(Molding)等封装制程，可以产生能够分别上板(On Board)并作用于电路中的多个独立功率元件9。
上述现有的功率元件9的制程，由于必须切割分离该多个晶粒93，该多个半导体元件92之间必须预留切割耗损的空间，且不同大小的多个半导体元件92需要妥善分配于该基板91上，导致难以有效利用该基板91面积；另外，同时使用多个独立的功率元件9，必须逐一焊板结合电路，导致加工时间延长及零组件安装空间利用率低。
有鉴于此，现有的功率元件的制造方法及其结构确实仍有加以改善的必要。
发明内容
为了解决上述问题，本发明的目的是提供一种功率元件的制造方法，可以简化分割晶粒及后续封装的步骤。
本发明的目的是提供一种功率元件的制造方法，可以提升晶圆面积利用率。
本发明的目的是提供一种功率元件的结构，可以节省安装时间及线路的空间。
本发明的目的是提供一种功率元件的结构，可以整合多个功率晶片于单一个元件，且多个功率晶片互不干扰。
本发明全文所述方向性或其近似用语，例如例如「上(顶)」、「下(底)」、「正面」、「背面」、「表面」等，主要参考附图的方向，各方向性或其近似用语仅用以辅助说明及理解本发明的各实施例，非用以限制本发明。
本发明的功率元件的制造方法，包括：在一个硅晶圆的正面形成多个间隔排列的半导体元件层；在该硅晶圆的正面挖设多个沟槽以隔开该多个半导体元件层；在各沟槽中填充一种第一隔离材料；研磨该硅晶圆的背面至该多个第一隔离材料裸露；在该硅晶圆背面且相对该多个半导体元件层的区域附著多个金属层；各自独立的多个导线架分别电性连接该多个金属层。
本发明的功率元件的另一种制造方法，包括：在一个硅晶圆的正面形成多个间隔排列的半导体元件层；在该硅晶圆的正面挖设多个沟槽以隔开该多个半导体元件层；在各沟槽中填充一种第一隔离材料；研磨该硅晶圆的背面至该多个第一隔离材料裸露；在该硅晶圆背面的各第一隔离材料区域附著一种第二隔离材料；在该硅晶圆背面附著一种金属层；第二次研磨该硅晶圆的背面至该多个第二隔离材料裸露，且形成多个金属层覆盖于相对该多个半导体元件层的区域；各自独立的多个导线架分别电性连接该多个金属层。
本发明的功率元件的结构，包括：多个半导体元件层；多个硅晶层，该多个半导体元件层分别位于该多个硅晶层的上表面；多个第一隔离材料，分别位于该多个硅晶层之间，由该多个第一隔离材料分别隔离该多个半导体元件层；多个金属层，分别位于多个硅晶层的下表面；及多个导线架，分别电性连接该多个金属层，另包括多个第二隔离材料，分别位于该多个第一隔离材料相对该半导体元件层的另一侧。该多个第二隔离材料分割该多个金属层。
据此，本发明的功率元件的制造方法及其结构，在晶圆的前端制程阶段，将多个功率半导体单元整合在单一个元件，可以简化分割晶粒及后续封装的步骤，且节省切割耗损的硅晶圆面积，具有提升晶圆利用率及简化制程的功效；另外，同时使用多个功率单元时，可以安装单一个元件而省去逐一焊接的时间，具有提升安装效率及安装空间利用率的功效。
其中，挖设该多个沟槽，使该硅晶圆形成由该多个硅晶层交错凸出于该硅晶圆正面的结构，且该多个半导体元件层分别位于该多个硅晶层的顶部。如此，可以分割该多个半导体元件层，具有避免多个半导体元件层的电性功能互相干扰的功效。
其中，该多个金属层分别附著于该多个硅晶层相对该多个半导体元件层的一端，如此，各金属层可以作为对应半导体元件层的电极，有导电，散热及薄型化的功效。
其中，该多个第一隔离材料填入该多个沟槽，至该多个第一隔离材料与该多个半导体元件层齐平。如此，可以确实隔离该多个半导体元件层，具有避免影响后续配线制程及电性干扰的功效。
其中，第二次研磨后形成多个金属层各自覆盖于该多个硅晶层的区域，且由该多个第二隔离材料分隔该多个金属层。如此，可以避免该多个金属层彼此间发生短路，具有确保功率单元独立运作的功效。
其中，该多个第二隔离材料在该硅晶圆背面的分布图案，与该多个第一隔离材料在该硅晶圆正面的分布图案相同。如此，可以维持隔离效果同时避免影响该多个半导体元件层及该多个金属层的接电面积，具有提升硅晶圆空间利用率的功效。
附图说明
图1为一种现有功率元件的制造过程；
图2为本发明第一实施例的前端制程的情形图；
图3为本发明第一实施例的挖沟步骤的情形图；
图4为本发明第一实施例的填充步骤的情形图；
图5为本发明第一实施例的研磨步骤的情形图；
图6为本发明第一实施例的附著金属层的情形图；
图7为本发明第一实施例的封装完成的结构图；
图8为本发明第二实施例的附著隔离层的情形图；
图9为本发明第二实施例的附著金属层的情形图；
图10为本发明第二实施例的研磨步骤的情形图；
图11本发明第二实施例的封装完成的结构图。
【附图标记说明】
1：半导体元件层；
2：硅晶层；
3：第一隔离材料；
4：金属层；
5：导线架；
6：第二隔离材料；
W：硅晶圆；
T：沟槽；
9：功率元件；
91：基板；
92：半导体元件
93：晶粒。
具体实施方式
为让本发明的上述及其他目的、特征及优点能更明显易懂，下文特举本发明的较佳实施例，并配合附图，作详细说明如下：
请参照第2-7图所示，其为本发明功率元件的制造方法的第一实施例的制程步骤，包括在一个硅晶圆W的正面形成多个间隔排列的半导体元件层1；在该硅晶圆W的正面挖设多个沟槽T以隔开该多个半导体元件层1及多个硅晶层2；在各沟槽T中填充一种第一隔离材料3；研磨该硅晶圆W的背面至该多个第一隔离材料3裸露；在该硅晶圆W背面且相对该多个半导体元件层1的区域附著多个金属层4；将各自独立的多个导线架5分别电性连接该多个金属层4。
请参照第2图所示，可以通过半导体前端制程(Front-end Process)，将各种不同功能组合的各个半导体元件层1结合于该硅晶圆W的正面，且该多个半导体元件层1相互之间具有适当的距离，可以避免该多个半导体元件层1的电性功能互相干扰。
请参照第3图所示，在该硅晶圆W的正面且该多个半导体元件层1以外的区域挖设该多个沟槽T，使该硅晶圆W形成由该多个硅晶层2交错凸出与该硅晶圆W正面的结构，且该多个半导体元件层1分别位于该多个硅晶层2的顶部。
请参照第4图所示，将该多个第一隔离材料3分别填入该多个沟槽T，较佳使该多个第一隔离材料3与该多个半导体元件层1齐平，可以确实隔离该多个半导体元件层1，及可以避免影响后续配线封装制程。
请参照第5图所示，进入半导体后端制程(Back-end Process)，由该硅晶圆W的背面进行研磨加工，使该硅晶圆W的厚度符合后续封装所需要的尺寸的大小，并通过研磨使该多个第一隔离材料3裸露与该硅晶圆W的背面，且各个硅晶层2独自隔离于该硅晶圆W。
请参照第6图所示，该多个金属层4分别附著与该多个硅晶层2相对该多个半导体元件层1的一端，各金属层4可以作为对应的半导体元件层1的电极，例如：IGBT的集极或二极体的接电端等。
请参照第7图所示，该多个导线架5电性独立且分别电性连接该多个金属层4。
请参照第2-5图及8-11图所示，其为本发明功率元件的制造方法的第二实施例的制程步骤，包括在一个硅晶圆W的正面形成多个间隔排列的半导体元件层1；在该硅晶圆W的正面挖设多个沟槽T以隔开该多个半导体元件层1及多个硅晶层2；在各沟槽T中填充一种第一隔离材料3；研磨该硅晶圆W的背面至该多个第一隔离材料3裸露；在该硅晶圆W背面的各第一隔离材料3区域附著一种第二隔离材料6；在该硅晶圆W背面附著一个金属层4；研磨该硅晶圆W的背面至该多个第二隔离材料6裸露，且该金属层4留存于相对多个半导体元件层1的区域；各自独立的多个导线架5分别电性连接该多个金属层4。
请参照第2-5图所示，本发明第二实施例与第一实施例的前四项制程步骤相同，如第5图所示，形成该多个半导体元件层1附著于该多个硅晶层2，该多个第一隔离材料3分别间隔该多个半导体元件层1及该多个硅晶层2。
请参照第8图所示，该多个第二隔离材料6分别附著于该多个第一隔离材料3在该硅晶圆W背面的一侧，使该多个第二隔离材料6在该硅晶圆W背面的分布图案，与该多个第一隔离材料3在该硅晶圆W正面的分布图案相同。
请参照第9图所示，该多个金属层4位于该硅晶圆W的背面，并分别附著于该多个硅晶层2及该多个第二隔离材料6，使该多个金属层4相互连通并完整覆盖该硅晶圆W的背面。
请参照第10图所示，通过第二次研磨该硅晶圆W的背面，使该多个第二隔离材料6裸露，且该多个金属层4仅各自覆盖于该多个硅晶层2的区域，由该多个第二隔离材料6分隔该多个金属层4，可以避免该多个金属层4彼此间发生短路，而影响对应的半导体元件层1及硅晶层2的电性功能。另外，较佳使该多个金属层4与该多个第二隔离材料6齐平，可以避免影响后续配线封装制程。
请参照第11图所示，该多个导线架5电性独立且分别电性连接该多个金属层4。
请参照第7图所示，其为上述功率元件的制造方法的第一实施例所制成该功率元件结构，包括该多个半导体元件层1、该多个硅晶层2、该多个第一隔离材料3、该多个金属层4及多个导线架5，该多个半导体元件层1分别位于该多个硅晶层2的上表面，该过个半导体元件层1由该多个第一隔离材料3分别隔离，各金属层4位于该硅晶层2的下表面，该多个导线架5通过该金属层一对一连接该多个硅晶层2。
各半导体元件层1可以由掺杂(Doping)成分含量不同的半导体(如：P型半导体、N型半导体)、绝缘材料(如：二氧化硅)、导电材料(如：金属、多晶硅等)，以沉积、蚀刻、布线等前端制程堆叠建构而成，各半导体元件层1可以是电晶体、二极体或电容等电子元件，该多个半导体元件层1互相间隔地排列于本发明的功率元件的同一表面。
该多个硅晶层2可以由该硅晶圆W经过挖沟，填充等加工程序，而成为个别分隔的状态，该多个硅晶层2一对一承载该多个半导体元件层1。
该多个第一隔离材料3为电绝缘材料(如：二氧化硅、陶瓷、树脂或其复合材料等)，该多个第一隔离材料3分别位于该多个半导体元件层1之间，用以避免该多个半导体元件层1互相导通，该多个第一隔离材料3还可以分隔该多个硅晶层2。
各个金属层4及各导线架5位于该硅晶层2相对该半导体元件层1的另一侧，该多个硅晶层2通过该多个金属层4分别连接该多个独立的导线架5，该金属层4具有导电，散热及薄型化的作用，该导线架5提供传导路径使功率元件的功能连接至外部系统。
请参照第11图所示，其为上述功率元件的制造方法的第二实施例所制成该功率元件结构，在本实施例中，该功率元件另包括多个第二隔离材料6，分别位于该多个第一隔离材料3相对该半导体元件层1的另一侧，各第二隔离材料6与各第一隔离材料3较佳具有相同的分布图案，该多个第二隔离材料6可以用于分隔该多个金属层4，具有避免该多个金属层4彼此间发生短路的作用。
综上所述，本发明的功率元件的制造方法及其结构，在晶圆的前端制程阶段，将多个功率单元整合在单一个元件，可以简化分割晶粒及后续封装的步骤，且节省切割耗损的硅晶圆面积，具有提升圆利用率及简化制程等功效；另外，同时使用多个功率单元时，可以安装单一个元件而省去逐一焊接的时间，具有提升安装效率及安装空间利用率的功效。
虽然本发明已利用上述较佳实施例公开，但其并非用以限定本发明，本领域技术人员在不脱离本发明的精神和范围之内，相对上述实施例进行各种更动与修改仍属于本发明所保护的技术范畴，因此本发明的保护范围应当以权力要求书所界定为准。

Claims (13)

1.一种功率元件的制造方法，包括：
在一个硅晶圆的正面形成多个间隔排列的半导体元件层；
在该硅晶圆的正面挖设多个沟槽以隔开该多个半导体元件层；
在各沟槽中填充一种第一隔离材料；
研磨该硅晶圆的背面至该多个第一隔离材料裸露；
在该硅晶圆背面且相对该多个半导体元件的区域附著多个金属层；
将各自独立的多个导线架分别电性连接该多个金属层。
2.根据权利要求1所述的功率元件的制造方法，其特征在于，在该硅晶圆的正面挖设该多个沟槽，使该硅晶圆形成由该多个硅晶层交错凸出于该硅晶圆正面的结构，且该多个半导体元件层分别位于该多个硅晶层的顶部。
3.根据权利要求2所述的功率元件的制造方法，其特征在于，该多个金属层分别附著于该多个硅晶层相对该多个半导体元件层的一端。
4.根据权利要求1所述的功率元件制造方法，其特征在于，该多个第一隔离材料填入该多个沟槽，至该多个隔离材料与该多个半导体元件层齐平。
5.一种功率元件的制造方法，包括：
在一个硅晶圆的正面形成多个间隔排列的半导体元件层；
在该硅晶圆的正面挖设多个沟槽以隔开该多个半导体元件层；
在各沟槽中填充一种第一隔离材料；
研磨该硅晶圆的背面至该多个第一隔离材料裸露；
在该硅晶圆背面的各第一隔离材料区域附著一种第二隔离材料；
在该硅晶圆背面附著一个金属层；
第二次研磨该硅晶圆的背面至该多个第二隔离材料裸露，且形成多个金属层覆盖于相对该多个半导体元件层的区域；
将各自独立的多个导线架分别电性连接该多个金属层。
6.根据权利要求5所述的功率元件的制造方法，其特征在于，在该硅晶圆的正面挖设该多个沟槽，使该硅晶圆形成由该多个硅晶层交错凸出于该硅晶圆正面的结构，且该多个半导体元件层分别位于该多个硅晶层的顶部。
7.根据权利要求6所述的功率元件的制造方法，其特征在于，该金属层附著该硅晶圆背面的该多个硅晶层及该多个第二隔离材料。
8.根据权利要求7所述的功率元件的制造方法，其特征在于，第二次研磨后形成多个金属层各自覆盖于该多个硅晶层的区域，且由该多个第二隔离材料分隔该多个金属层。
9.根据权利要求5所述的功率元件的制造方法，其特征在于，该多个第一隔离材料填入该多个沟槽，至多个第一隔离材料与该多个半导体元件层齐平。
10.根据权利要求5所述的功率元件的制造方法，其特征在于，该多个第二隔离材料在该硅晶圆背面的分布图案，与该多个第一隔离材料在该硅晶圆正面的分布图案相同。
11.一种功率元件的结构，包括：
多个半导体元件层；
多个硅晶层，该多个半导体元件层分别位于该多个硅晶层的上表面；
多个第一隔离材料，分别位于该多个硅晶层之间，由该多个第一隔离材料分别隔离该多个半导体元件层；
多个金属层，分别位于该多个硅晶层的下表面；及
多个导线架，分别电性连接该多个金属层。
12.根据权利要求11所述的功率元件的结构，另包括多个第二个礼材料，分别位于该多个第一隔离材料相对该半导体元件层的另一侧，该多个第二隔离材料分隔该多个金属层。
13.根据权利要求12所述的功率元件的结构，其特征在于，该多个第一隔离材料与多个第二隔离材料的分布区域图案相同。
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