CN110246756B - 碳化硅静电感应晶体管以及用于制作碳化硅静电感应晶体管的工艺 - Google Patents

碳化硅静电感应晶体管以及用于制作碳化硅静电感应晶体管的工艺 Download PDF

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CN110246756B
CN110246756B CN201910419476.1A CN201910419476A CN110246756B CN 110246756 B CN110246756 B CN 110246756B CN 201910419476 A CN201910419476 A CN 201910419476A CN 110246756 B CN110246756 B CN 110246756B
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J·H·张
P·莫林
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STMicroelectronics lnc USA
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Abstract

一种静电感应晶体管被形成在掺杂有第一导电类型的碳化硅衬底上。在碳化硅衬底的顶表面中的第一凹陷区域由原位掺杂有第二导电类型的外延生长栅极区域填充。原位掺杂有第一导电类型的外延生长沟道区域被定位在邻近的外延沟道区域之间。原位掺杂有第一导电类型的外延生长源极区域被定位在外延沟道区域上。碳化硅衬底的底表面包括与沟道区域纵向对准并且被硅化以支持形成漏极接触的第二凹陷区域。源极区域的顶表面被硅化以支持形成源极接触。栅极引线被外延生长并且电耦合到栅极区域，其中栅极引线被硅化以支持形成栅极接触。

Description

碳化硅静电感应晶体管以及用于制作碳化硅静电感应晶体管 的工艺
本申请是申请日为2015年03月27日、申请号为201510142161.9、发明名称为“碳化硅静电感应晶体管以及用于制作碳化硅静电感应晶体管的工艺”的中国发明专利申请的分案申请。
技术领域
本申请涉及集成电路的制作，并且更具体地涉及一种用于制作碳化硅(SiC)静电感应晶体管(SIT)的工艺。
背景技术
用于将电流接通和关断的半导体的选择依赖于操作电压和必须控制多少电流。硅是用于在低功率晶体管中使用的良好材料，但是对于高电流和电压，基于硅的开关器件的实施方式变得复杂并且出现热管理问题。
对于可以操作在提高的温度下的高电压、高电流器件，碳化硅(SiC)被本领域技术人员认作用于晶体管制作的首选材料。针对SiC衬底最容易合成的六方多型体，4H和6H，具有大间接带隙(～3.2eV)和大击穿电场(2MV cm-1)以及高电子迁移率(900cm2V-1s-1)和热导率(400W m-1K-1)。给定这些性质，基于SiC的功率开关可以呈现硅衬底开关十到一百倍的性能品质因数。
碳化硅(SiC)静电感应晶体管(SiT)在本领域中众所周知。这样的晶体管例如可以使用在高功率射频(RF)应用中。SiC SIT器件呈现由超低功率损失表征的优越性能。例如，已知的600V～1.2kV等级的开关器件已经被示出具有700V的击穿电压(VBR)和1.01mΩ·cm2的特定(specific)导通电阻(RonS)。
SiC SIT器件的制作通常利用离子注入技术。例如，目前制作工艺针对n+区域掺杂物使用高能量。然而，掺杂物注入可以引起对SiC衬底的损伤，从而导致对器件可靠性(诸如漏电)的顾虑。为解决该顾虑，现有技术教导使用更低能量的注入制作双台面SiC SIT器件，但是该工艺不幸地需要工艺步骤的增加和更高的制作成本。
因此在本领域中有需要解决前述以及与制作SiC SIT器件有关的其他顾虑。
发明内容
在一个实施例中，一种静电感应晶体管(SIT)包括：碳化硅衬底，掺杂有第一导电类型并且包括在碳化硅衬底的顶表面中的多个第一凹陷区域；多个外延栅极区域，在第一凹陷区域内并且原位掺杂有第二导电类型；多个外延沟道区域，定位在邻近的外延栅极区域之间并且原位掺杂有第一导电类型；以及多个外延源极区域，在多个外延沟道区域上并且原位掺杂有第一导电类型。
在一个实施例中，一种用于制作静电感应晶体管(SIT)的方法包括：在掺杂有第一导电类型的碳化硅衬底的顶表面中形成多个第一凹陷区域；在第一凹陷区域内外延生长多个栅极区域；利用第二导电类型对栅极区域进行原位掺杂；外延生长定位在邻近的栅极区域之间的多个沟道区域；利用第一导电类型对沟道区域进行原位掺杂；在多个沟道区域上外延生长多个源极区域；以及利用第一导电类型对源极区域进行原位掺杂。
附图说明
为了更好地理解实施例，现在将仅通过示例的方式参考附图，在附图中：
图1-图18示出了根据用于制作静电感应晶体管(SIT)的实施例的工艺步骤；以及
图19是SIT的平面视图。
具体实施方式
现在参考示出用于制作包括碳化硅(SiC)静电感应晶体管(SIT)器件的集成电路的工艺步骤的图1-图18。将理解的是所提供的图示不一定示出成比例绘制的特征。
如图1所示提供衬底晶片10。晶片10包括具有例如300μm厚度的碳化硅(SiC)衬底晶片12。SiC衬底晶片12可以例如是4H多型体。备选地，晶片12也可以是6H多型体或者3C多型体，或者SiC的任何其他合适的多型体。层12优选地更加重掺杂有第一导电类型(例如，n型掺杂物)(n+)并且具有小于0.10ohm·cm的电阻率。SiC缓冲层14被生长在具有例如0.0025至1.0μm的厚度的晶片12顶上。该缓冲层14优选地重掺杂有第一(n型)导电性(n+)并且可以具有5×1017至1×1019cm-3的典型施主浓度。SiC漂移层16被生长在具有例如0.0001至15μm的厚度的缓冲层14顶上。漂移层16优选地轻掺杂有第一(n型)导电性(n-)并且可以具有1×1015至1×1017cm-3的典型施主浓度。漂移层16起作用以提供期望的晶体管阻挡电压电平。晶片10可以进一步可选地包括生长在具有例如0.0005至5μm的厚度的漂移层16顶上的SiC沟道层18。沟道层18优选地轻掺杂有第一(n型)导电性(n-)并且可以具有1×1016至5×1017cm-3的典型施主浓度。沟道层18被配置以提供有效的沟道传导特性。
如图2所示，硬掩膜20被沉积在晶片10的顶表面上并且使用对本领域技术人员众所周知的常规的光刻工艺技术进行图案化以限定若干掩膜开口22。硬掩膜20可以包括通过对于本领域技术人员已知的热化学气相沉积(CVD)或者等离子体增强化学气相沉积(PECVD)沉积的二氧化硅(SiO2或者SiO)材料、氮化硅(SiN)材料或者氮氧化硅(SiON)材料。硬掩膜20可以具有例如0.03至1.0μm的厚度。
然后执行湿法或者干法刻蚀(例如，使用350℃的NaOH(非各向同性)或者利用氮化铝硬掩膜的基于氟的温度辅助RF等离子体刻蚀(各向同性))以去除晶片10的通过硬掩膜20中的开口22露出的部分。刻蚀工艺在晶片10的顶表面中产生凹陷区域24。凹陷区域24可以具有例如0.001至1μm的深度，并且优选地延伸完全通过沟道层18(如果存在)并且至少部分地进入漂移层16。图3中示出了在后续去除硬掩膜20之后的刻蚀工艺的结果。
然后执行如本领域技术人员已知的外延生长工艺以生长覆在晶片10之上的外延碳化硅(SiC)层30。结果在图4中示出。层30填充由图3的刻蚀工艺留在晶片10中的凹陷区域24。层30优选地原位重掺杂有第二导电类型(例如，p型掺杂物)(p+)并且可以具有1×1016至5×1018cm-3的典型施主浓度。层30可以例如具有0.0001至5μm的厚度。由于外延生长工艺的共形本质，层30的上表面将包括凹陷区域32(在位置上通常纵向地对应于区域24)。
硬掩膜36被沉积在晶片10的顶表面上、在层30之上。硬掩膜36可以包括通过对于本领域技术人员已知的热化学气相沉积(CVD)或者等离子体增强化学气相沉积(PECVD)技术沉积的二氧化硅(SiO2或者SiO)材料、氮化硅(SiN)材料或者氮氧化硅(SiON)材料。硬掩膜36可以具有例如0.03至1.0μm的厚度。硬掩膜的沉积是共形的并且因此将填充凹陷区域32。然后使用如本领域技术人员已知的化学机械抛光(CMP)工艺去除硬掩膜36材料的未定位在凹陷区域32内的上覆部分。因此CMP工艺停止在外延层30的顶表面处。结果在图5中示出。
保留在凹陷区域32中的硬掩膜材料形成用于在自对准沟道形成中使用的阻挡掩膜40。选择性刻蚀，例如，反应离子刻蚀(RIE)，被应用到晶片以去除外延层30的不由阻挡掩膜40保护的部分并且留下外延层30的剩余部分42。结果在图6中示出。应理解，该刻蚀可去除衬底10的在顶表面处的部分(该事实在图6中未明确图示)。然而，对于下文所讨论的外延再生长原因，该材料去除无关紧要。
进一步的选择性刻蚀(例如，反应离子刻蚀(RIE))被应用到晶片以去除阻挡掩膜40以及剩余部分42的部分，以留下栅极区域46和通过由层30提供的p+掺杂材料形成的保护区域48。结果在图7中示出。应理解，该刻蚀可以去除衬底10的在顶表面处的部分(该事实在图7中未明确图示)。然而，对于下文所讨论的外延再生长的原因，该材料去除无关紧要。
在外延层30上执行的RIE工艺限定晶体管的沟道长度(即，在纵向方向上从p型区域的顶部到底部的长度)以及晶体管的沟道宽度(即，p型区域之间的水平距离)。如此限定的沟道长度确定晶体管的跨导(gm)，并且沟道长度和沟道宽度一起确定晶体管的Vp。总栅极电容(Cgg)由p型栅极区域46的周界长度确定，并且包括在沟道台面的纵向方向上的本征栅极电容以及在沟道台面之间的水平方向上的外在“寄生”栅极电容。晶体管的截止频率ft取决于比率：gm/Cgg。因此，最小化Cgg并且最大化Gm是有利的以便实现期望的高频功率放大。
然后共形绝缘材料层50被沉积在晶片10上以覆盖栅极区域46、环形区域48和沟道层18。层50可以例如包括氧化物层(诸如，二氧化硅SiO2)或者高K电介质氧化物材料(诸如，氧化铪HfO2)。层50可以具有0.0001-0.1μm的厚度，并且可以使用如本领域已知的等离子体增强化学气相沉积(PECVD)或者物理气相沉积(PVD)工艺进行沉积。结果在图8中示出。
使用对于本领域技术人员众所周知的掩膜和光刻技术，去除在晶片10的区域52之上的层50，如图9所示。通过图形化掩膜执行的选择性反应离子刻蚀(RIE)可以例如用于选择性地打开区域52中的晶片10的上表面。在区域52中，该刻蚀可以去除沟道层18的所有或者主要部分(并且也可以延伸到层16中)。然而，对于下文所讨论的外延再生长的原因，该材料去除无关紧要。
然后执行对于本领域技术人员已知的外延再生长工艺以生长覆在区域52中的晶片10的露出的n型衬底部分之上的外延碳化硅(SiC)层60。结果在图10中示出。层60填充通过图9的刻蚀工艺留在晶片10中的栅极区域46之间的空间。层50优选地原位轻掺杂有第一(n型)导电掺杂物(n-)并且可以具有1×1016至1×1018cm-3的典型施主浓度。层60可以例如具有0.0005至5μm的厚度。就这点而言，重要的是注意由于晶格失配，n-外延生长将比p+外延生长更快。虽然在图9中未明确图示，外延碳化硅(SiC)层60的薄部分可以被形成在栅极区域46的顶表面上。然而，这不是顾虑，因为上覆沉积与PN结的形成一致以支持器件操作。
提供邻近的栅极区域46之间的层60以限定用于晶体管的沟道区域。第一(n型)导电材料的该外延再生长用作修复由于先前的RIE工艺(图9)对沟道层18做出的损伤。因此，再生长形成用于将支持高频操作的晶体管的高质量的短的第一导电类型的沟道。
然后执行如对于本领域技术人员已知的外延生长工艺以生长外延碳化硅(SiC)层70。结果在图11中示出。层70共形地覆盖层60和栅极区域46。层70优选地原位重掺杂有第一(n型)导电掺杂物(n+)并且可以具有1×1018至2×1019cm-3的典型施主浓度。层70可以例如具有0.0001至5μm的厚度。提供层70以限定用于晶体管的源极区域，其中重掺杂第一(n型)导电材料促进到源极区域的欧姆接触的形成，正如下文将讨论的。
然后在晶片10上沉积介电层80。层80可以例如包括使用PECVD工艺沉积的超低K(ULK)材料(诸如如本领域已知的OMCATS)。层80可以具有0.2至2μm的厚度。用于沉积层80的工艺可以导致层80跨晶片10的表面区域的非均匀厚度。在层80的沉积之后，可以使用如对于本领域技术人员已知的化学机械抛光(CMP)工艺以便提供均匀的期望的厚度和用于层80的平整的顶表面。结果在图12中示出。
然后使用对于本领域技术人员众所周知的大马士革工艺使某些位置中的介电层80凹陷以打开多个孔径84和86。在通常定位在邻近栅极区域46之间以便露出由外延层70形成的源极区域的位置处使用掩膜和刻蚀在区域52中形成孔径84。在通常定位以便露出栅极区域46的位置处使用掩膜和刻蚀在晶片10的邻近区域54中形成孔径86。结果在图13中示出。
就这点而言，应理解，在晶片10的区域54中的栅极区域46被电耦合到晶片10的区域52中的栅极区域46。更具体地，栅极区域54可以包括在晶片10内的待形成的集成电路芯片的外围区域，并且区域52可以包括在待形成的集成电路芯片内的中心区域。在一个实施例中，区域54可以延伸以完全包围区域52。在另一实施例中，区域54可以在两侧上界定区域52。在图19中图示了栅极区域46之间的电连接，其例如将由延伸通过中心区域52的区域46与沿着外围区域54延伸的区域46的交叉提供。图19中的附图标记线A-A示出了其中截取图1至图18的截面的一个示例。图19中的附图标记线B-B示出了其中截取图1至图18的截面的另一示例。
然后使用对于本领域技术人员众所周知的大马士革工艺以使SiC衬底晶片12在某些位置中凹陷以在晶片10的底表面上打开多个孔径88。在通常定位以与孔径84纵向地对准的位置处使用掩膜和刻蚀在区域52中形成孔径88。结果在图14中示出。区域52中的SiC衬底晶片12形成晶体管的漏极区域。
然后使用如对于本领域技术人员众所周知的自对准硅化(salicidation)工艺形成用于源极区域和漏极区域的欧姆接触100，如图15所示。在a)针对区域52中的衬底晶片12(包括在孔径88内)的碳化硅(SiC)材料上、b)区域52中的外延层70(在孔径84内)上、以及c)区域54中的栅极区域46(在孔径86内)上沉积薄金属膜。金属膜可以例如包括镍(Ni)，其中膜具有500至
Figure BDA0002065532180000071
的厚度。晶片10受到热退火工艺，该工艺使得Ni与SiC形成合金以形成硅化镍(NixSi，其中x包括例如2)接触100。热退火工艺可以包括多个不同温度的退火。在一个实施例中，工艺中的至少最后的退火被执行在850℃至1000℃的温度。
然后在区域52和区域54中的晶片10上沉积金属衬垫110，如图16所示。金属衬垫110的沉积是共形的，并且因此衬垫110覆盖介电层80的顶部表面以及孔径84和孔径86的侧壁和底部。金属衬垫110可以包括例如钛(Ti)、氮化钛(TiN)、钨化钛(TiW)或者氮化钽(TaN)。衬垫110具有1至10nm的厚度，并且使用PVD工艺进行沉积。
然后用于源极和栅极连接120的金属被沉积在孔径84和孔径86内并且填充孔径84和孔径86。例如可以使用化学气相沉积或者电镀工艺进行沉积。用于连接120的金属可以例如包括钨(W)、铝(Al)、铜(Cu)或者金(Au)。在一个实施例中，用于孔径84中的源极连接所使用的金属可以与用于孔径86中的栅极连接所使用的金属不同。例如，源极连接可以使用上文所公开的金属或其合金，而栅极连接可以使用钛(Ti)、铂(Pt)或者金(Au)或其合金。用来填充孔径84和孔径86的金属的沉积将很可能导致在介电层80的顶表面上沉积金属。如对于本领域技术人员已知的化学机械抛光(CMP)工艺可以用于去除层80的顶表面上的过度金属沉积。结果在图17中示出。
然后用于漏极连接130的金属被沉积在晶片10的背侧上、在漏极欧姆接触100上。例如可以使用CVD或者电镀工艺进行沉积。用于连接130的金属被选择用于裸片附连适用性并且可以例如包括：a)用于金/硅(Au/Si)共熔合金裸片附连的沉积的硅层，b)由钛、铂和金(Ti/Pt/Au)形成的合金或者层状结构，c)由钛、镍和金(Ti/Ni/Au)形成的合金或者层状结构，或者d)由本领域技术人员已知的任何其他常规裸片附连金属。结果在图18中示出。
图18中示出了完成的SiC SIT器件的截面。图19中示出了SiCSIT器件的平面视图，该平面视图仅仅示出了总体器件的一部分(例如，四分之一)。器件包括由区域52中的p+栅极区域46形成的多个栅极指状件140。器件进一步包括由外围区域54中的栅极区域46形成的栅极引线142。栅极指状件140被电连接到栅极引线142并且从栅极引线142垂直地延伸。器件进一步包括由外围区域54中的保护区域48形成的保护环144。保护环144通常是电浮置结构。器件的源极区域由n+外延碳化硅(SiC)层70形成。器件的沟道区域由再生长n-外延碳化硅(SiC)层60形成。器件的漏极区域由晶片10的n+碳化硅(SiC)衬底层(12、14、16)形成。
接下来晶片10可以被切割成单独的集成电路芯片。图18和图19在附图标记150处图示了当切割晶片10时用于切割线的示例位置。在切割晶片10之后，单独的芯片经受对于本领域技术人员众所周知的常规后段制程(BEOL)工艺和封装动作。
SiC SIT器件呈现对现有技术电路的若干优点，包括：该工艺是无注入的以避免对SiC衬底损伤的顾虑；沟道区域由具有外围掺杂物的外延生长的材料形成；用于接触形成的源极和漏极大马士革凹陷工艺提供增加的欧姆接触区域并且允许制作具有降低的接触电阻的结构；用于制作的工艺与压缩工艺节点兼容；器件的n型沟道具有支持当关断晶体管时形成完全耗尽区域并且用于提供非常适于实现高频器件操作的降低的Cgg和增加的gm的新形状；填充凹陷区域32的硬掩膜材料支持用于沟道形成的自对准工艺，而无需附加的光刻工艺步骤；该工艺支持用于打开源极接触的自对准操作；该工艺以更低的成本在更少的步骤中完成器件制作。
虽然本文详细地讨论了做出和使用各个实施例，应理解，如本文所描述的是提供可以在各种背景中实施的很多发明构思。本文所讨论的实施例仅仅是代表性的而不限制本发明的范围。
虽然已经在附图和前述描述中详细地图示和描述了本发明，但是这样的图示和描述被认为是说明性或者示例性的而不是限制性的；本发明并不限于所公开的实施例。本领域技术人员在实践所要求权利的发明中，从学习附图、公开和所附权利要求书中可以理解和影响对所公开的实施例的其他变化。

Claims (24)

1.一种用于制造静电感应晶体管SIT的方法，包括：
在掺杂有第一导电类型的碳化硅衬底上生长多个外延栅极区域，其中所述多个外延栅极区域以第二导电类型进行原位掺杂；
生长定位在邻近的外延栅极区域之间的多个外延沟道区域，其中所述多个外延沟道区域以所述第一导电类型进行原位掺杂；以及
在所述多个外延沟道区域上生长多个外延源极区域，其中所述多个外延源极区域以所述第一导电类型进行原位掺杂，
其中所述多个外延源极区域进一步延伸以覆盖在所述多个外延栅极区域之上。
2.根据权利要求1所述的方法，其中生长所述多个外延栅极区域包括将所述多个外延栅极区域图案化为栅极指状件和栅极引线，所述栅极引线电耦合到所述栅极指状件。
3.根据权利要求2所述的方法，还包括：
沉积覆在所述多个外延源极区域之上的介电层并覆盖所述栅极引线；
在所述介电层中形成栅极接触开口；以及
利用金属材料填充所述栅极接触开口以形成与所述栅极引线的栅极接触。
4.根据权利要求1所述的方法，进一步包括生长以所述第二导电类型进行原位掺杂的外延保护区域。
5.根据权利要求4所述的方法，其中所述外延保护区域形成保护环。
6.根据权利要求1所述的方法，还包括在所述碳化硅衬底的底表面中形成多个凹陷区域，所述多个凹陷区域与定位在邻近的外延栅极区域之间的所述外延沟道区域垂直对准。
7.根据权利要求6所述的方法，还包括在所述多个凹陷区域中形成硅化物材料。
8.根据权利要求1所述的方法，还包括在所述多个外延源极区域上形成硅化物材料。
9.根据权利要求1所述的方法，其中生长所述多个外延源极区域还包括生长所述多个外延源极区域以延伸并覆盖在所述多个外延栅极区域之上。
10.根据权利要求1所述的方法，还包括：
沉积覆在所述多个外延源极区域之上的介电层；
在所述介电层中形成多个源极接触开口；以及
用金属材料填充所述源极接触开口以形成源极接触。
11.一种用于制造静电感应晶体管SIT的方法，包括：
在掺杂有第一导电类型的碳化硅衬底的顶表面中形成多个第一凹陷区域；
在所述顶表面上外延生长碳化硅层，所述碳化硅层以第二导电类型进行原位掺杂并且具有与所述第一凹陷区域对准的多个第二凹陷区域；
用掩模材料填充所述第二凹陷区域以限定栅极掩模；
使用所述栅极掩模蚀刻所述碳化硅层以限定多个栅极区域；
外延生长多个沟道区域，所述多个沟道区域定位在邻近的栅极区域之间并且以所述第一导电类型进行原位掺杂；
在所述多个沟道区域上外延生长多个源极区域并以所述第一导电类型进行原位掺杂；
形成与所述碳化硅衬底的背表面的第一硅化物接触；
形成与所述多个源极区域的第二硅化物接触；以及
形成针对电连接至所述栅极区域的栅极引线的第三硅化物接触，
其中所述多个源极区域进一步延伸以覆盖在所述多个栅极区域之上。
12.一种静电感应晶体管SIT，包括：
第一碳化硅层，掺杂有第一导电类型的掺杂剂以形成漏极区域，并且在所述第一碳化硅层的顶表面中包括多个第一凹陷；
每个第一凹陷内的栅极区域，所述栅极区域由掺杂有第二导电类型的掺杂剂的外延碳化硅形成；
定位在邻近的栅极区域之间的沟道区域，所述沟道区域由掺杂有所述第一导电类型的掺杂剂的外延碳化硅形成；以及
第二碳化硅层，掺杂有所述第一导电类型的掺杂剂，所述第二碳化硅层覆在所述栅极区域之上，以形成源极区域。
13.根据权利要求12所述的SIT，其中每个栅极区域限定栅极指状件，并且还包括栅极引线，所述栅极引线电耦合到所述栅极指状件并且由掺杂有所述第二导电类型的掺杂剂的外延碳化硅形成。
14.根据权利要求13所述的SIT，还包括覆在所述第二碳化硅层之上的介电层，所述介电层包括填充有金属材料的栅极接触开口，以形成与所述栅极引线的栅极接触。
15.根据权利要求12所述的SIT，其中所述第一碳化硅层还包括在所述第一碳化硅层的顶表面中的附加凹陷，还包括在由掺杂有所述第二导电类型的掺杂剂的半导体材料形成的所述附加凹陷内的保护区域。
16.根据权利要求15所述的SIT，其中所述半导体材料是碳化硅。
17.根据权利要求15所述的SIT，其中所述附加凹陷具有基本围绕所述第一凹陷的环形形状，并且所述保护区域形成保护环。
18.根据权利要求12所述的SIT，还包括覆在所述第二碳化硅层之上的介电层，所述介电层包括填充有金属材料的源极接触开口，以形成与所述源极区域的源极接触。
19.根据权利要求12所述的SIT，还包括在所述第一碳化硅层下方的第三碳化硅层，其中所述第三碳化硅层包括在所述第三碳化硅层的底表面中的多个第二凹陷，每个第二凹陷与一个所述沟道区域垂直对准。
20.根据权利要求19所述的SIT，还包括在所述多个第二凹陷中形成的硅化物材料。
21.根据权利要求12所述的SIT，还包括在所述源极区域上形成的硅化物材料。
22.一种静电感应晶体管SIT，包括：
碳化硅衬底，掺杂有第一掺杂剂浓度的第一导电类型的掺杂剂，以形成漏极区域，并包括在所述碳化硅衬底的顶表面中的多个第一凹陷；
栅极区域，位于每个第一凹陷内，所述栅极区域由掺杂有第二导电类型的掺杂剂的外延碳化硅形成；
沟道区域，定位在邻近的栅极区域之间，所述沟道区域由掺杂有第二掺杂剂浓度的所述第一导电类型的掺杂剂的外延碳化硅形成，其中所述第二掺杂剂浓度小于所述第一掺杂剂浓度；以及
源极区域，定位在邻近的栅极区域之间，位于每个沟道区域之上，并且由掺杂有第三掺杂剂浓度的所述第一导电类型的掺杂剂的外延碳化硅形成，所述第三掺杂剂浓度大于所述第二掺杂剂浓度，
其中所述源极区域进一步延伸以覆盖在所述栅极区域之上。
23.根据权利要求22所述的SIT，还包括在每个源极区域上的硅化物材料和在所述碳化硅衬底的底表面上的硅化物材料。
24.根据权利要求22所述的SIT，其中所述第三掺杂剂浓度大于所述第一掺杂剂浓度。
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