CN110235533B - 制造电路的方法 - Google Patents

制造电路的方法 Download PDF

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Publication number
CN110235533B
CN110235533B CN201880009065.9A CN201880009065A CN110235533B CN 110235533 B CN110235533 B CN 110235533B CN 201880009065 A CN201880009065 A CN 201880009065A CN 110235533 B CN110235533 B CN 110235533B
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conductive medium
insulator
contact surface
circuit
insulating body
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CN110235533A (zh
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斯特凡·普费弗莱因
托马斯·比格尔
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Siemens AG
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Siemens AG
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Abstract

本发明涉及一种用于制造电路(2)的方法(20),其中,提供具有第一接触面(14)并且具有第二接触面(16)的电路载体(4)。将绝缘体(26)施加到电路载体(4)上,其中,绝缘体(26)至少部分地覆盖第一接触面(14)以及第二接触面(16),并且其中,绝缘体(26)在两个接触面(14、16)的区域中分别具有空隙(34)。在绝缘体(26)中填充可流动的导电介质(44)。另外,本发明涉及一种电路(2)以及另一种用于制造电路(2)的方法(60)。

Description

制造电路的方法
技术领域
本发明涉及一种制造电路的方法以及一种电路。
背景技术
电路大多具有电路载体,在该电路载体处固定有电气和/或电子部件。电路载体本身大多由被玻璃纤维增强的环氧树脂制成,由铜制成的印制导线连接在电路载体处,或者印制导线嵌入进电路载体中。电气或电子部件与印制导线电接触并且固定在印制导线处。这大多借助表面安装技术(SMD技术)来完成。在此,电气或电子部件的端子或者与印制导线连接的接线面设置有焊膏,并且端子安置到印制导线上,其中,焊料随后在加热过程中融化。因此,电气或电子部件的端子在电路载体的表面上基本上是平坦的。
特定类型的电气或电子部件,例如特别是功率半导体开关,具有额外的端子,这些端子在安装状态下与电路载体间隔开。因此,这些部件通常设计为长方形,并且背离电路载体的表面具有一个或多个端子,或者形成一个或多个端子。为了该端子与印制导线的电气触而通常使用接合线。在部件固定在电路载体处之后,接合线由部件的接线面引导到印制导线的接线面上。
为了提供足够的载流能力,特别是如果部件是半导体,接合线必须构造为比较结实的或者多重的。因此,基本上不可能使这些接合线在事后发生变形而不出现电路损害。对此,仍然需要借助用于安装的工具来保持接合线。借助工具来引导接合线,该工具不仅借助于超声波焊接产生接合连接,而且使接合线形成所需的几何形状(即所谓的回路Loop)。因此,在电路制成之后,为此所需的几何形状也被保留,因此结构空间增大。此外,在电路安装时或者运行时,其他的部件能够与接合线处于机械接触并且将接合线例如从印制导线或者从端子处脱离。此外,接合线提供电感,在电路的规划和生产中必须考虑该电感。
由WO2012/060091A1已知一种用于制造芯片的三维结构的方法。在此,借助激光器部分地去除树脂,以便形成用于电连接导体的容纳部。
在EP2 147463A2中已知一种用于制造微型器件的电连接的方法。芯片被安装到基板上并且基板在芯片的周围范围中被去除。
由US2004/227235A1已知用于制造电子部件的方法。该电子部件具有基板,其上连接有芯片。
发明内容
本发明所基于的目的是,提供一种特别适合用于制造电路的方法,以及一种电路,其中,优选地提高了耐温性,并且特别是可靠性,以及优选地提高了设计灵活性并且适当地降低了制造成本。
在方法方面,该目的根据本发明的用于制造电路的方法来实现,并且在电路方面根据本发明的电路来实现。
该方法用于制造电路。电路例如是驱控电路。特别地,电路是变流器的组件(如逆变器或整流器)。优选地,电路被设置用于承受至少1安培(A)、10安培、20安培、50安培或者100安培的电流,例如,电路的载流能力小于或等于50kA、20kA、10kA、5kA、1000安培、900安培或者800安培。
该方法提出,提供具有第一接触面并且具有至少一个第二接触面的电路载体。电路载体例如被制作或者使用已经预制的电路载体。电路载体例如是DCB(直接铜键合)基板或者电路板,其特别地包含由玻璃纤维增强的环氧树脂或其他基板材料制成的基板,例如是注塑成型的电路载体。电路载体优选地具有印制导线,例如如果电路载体具有基板,印制导线就连接在基板处。
优选地,这两个接触面位于电路载体的同一表面侧。特别地,第一接触面和/或第二接触面至少部分地借助印制导线之一来形成,或者连接在印制导线之一处。适合地,该电路载体具有电气或电子部件,特别是多个以下部件,其例如连接在基板处或者优选地连接在印制导线之一处或者连接在接线面之一处,并且特别地与印制导线电接触。例如,利用电气或电子部件的端子来形成第二接触面。适合地,电气或电子部件是功率半导体。优选地,电气或电子部件是半导体开关,特别是功率半导体开关,如场效应晶体管,例如MOSFET、IGBT或GTO。电气或电子组件特别地借助焊接、烧结或粘接来材料配合地连接到电路载体的其他组件处,如基板和/或印制导线之一和/或接线面之一。
电路载体优选地设计成基本上平坦的,其中,例如借助一个或多个部件在电路载体的表面上形成凸起。除了凸起外,电路载体优选地基本上是平坦的。
优选地,第一接触面和第二接触面彼此平行地布置。换句话说,第一接触面位于一个平面中,而第二接触面位于另一个平面中,其中,这两个平面彼此平行。优选地,这两个平面彼此间隔开,使得第一接触面与第二接触面错开。适合地,第一接触面与第二接触面是电绝缘的。
在另一工作步骤中,绝缘体被施加到电路载体上。绝缘体由电绝缘材料制成,特别地,如塑料或硅树脂。此外,绝缘体优选地连接在电路载体处,优选地固定在电路载体处,例如以材料配合的方法固定,使得绝缘体相对于电路载体的位置是稳定的。绝缘体优选地是中空体或槽形体,如中空体,并且布置成第一接触面与第二接触面借助绝缘体被至少部分地覆盖。换句话说,绝缘体不仅贴靠在第一接触面处也贴靠在第二接触面处,并且因此与两个接触面直接机械接触。
绝缘体在两个接触面的区域中分别具有空隙。在此,空隙被预设在相应的接触面上,并且例如,这两个接触面的边沿或者这两个接触面中至少一个接触面(即第一接触面或第二接触面)的边沿借助绝缘体被密封,使得接触面基本上没有绝缘体。例如,至少借助中空体状的绝缘体限定空间区域,借助该空间区域将第一接触面与第二接触面连接。换句话说,借助绝缘体至少部分地提供空腔或者槽形体。如果在保护气氛或者类似条件下进行制造,该空间区域(空腔)本身优选地填充有空气或者其他气体。例如,空隙仅仅覆盖分别配属的接触面的区域,其中特别地,在空隙与分别配属的接触面之间的区域借助绝缘体被密封。总之,绝缘体被制成为,其在被施加到电路载体上之后具有位于两个接触面的区域中的两个空隙,并且因此空隙与两个接触面接触。特别地,两个空隙在此借助第一接触面以及借助第二接触面来封闭。
在另一工作步骤中,可流动的导电介质输入到绝缘体中。在此,获得以下绝缘体,使得电路不仅具有绝缘体而且还具有导电介质。导电介质具有较低的电阻,并且优选地包括较高密度的可自由移动的载流子。特别地,导电介质的导电率大于106S/m(西门子每米)。该导电介质在加工时是可流动的并且例如是液态的。优选地,粘度小于106mPa s、105mPa s、104mPa s、103mPa s、100mPa s、10mPa s或者1mPa s。至少在向绝缘体内填充的时间点,导电介质是可流动的。适合地,以物理或化学的方法使得导电介质处于这种状态,从而导电介质在填充进绝缘体中的时间点是可流动的。因此,导电介质至少部分地填充绝缘体,例如填满绝缘体,因而第一接触面和第二接触面借助导电介质电接触,例如被润湿。优选地,导电介质机械地直接贴靠在两个接触面处。特别地,导电介质在两个接触面的区域中通过两个空隙来部分地溢出,两个空隙优选地借助两个接触面被封闭。
例如,如下地选择导电介质,其在两个接触面的至少一个的区域中形成合金,或者至少与该接触面进行化学反应。特别地,在导电介质与接触面之间实现材料配合的连接。这例如借助所谓的粘接剂交联、即粘结剂来实现,粘接剂在空隙区域中施加到接触面上。特别地,导电介质是液体、膏状或者所谓的预成型件或插入件。
在本发明的一个设计方案中,导电介质填充进绝缘体中,其中,导电介质以固态的物质状态存在,因而插入到绝缘体中。在此之后,导电介质软化,并且转化为可流动的状态,从而导电介质填充绝缘体。换句话说,可流动的导电介质填充到绝缘体中的工作步骤,以及因此形成电连接的工作步骤由两个步骤组成,其中,首先将固态的导电介质安置到绝缘体中,然后导电介质在绝缘体中软化,这特别是借助加热来实现。在此,导电介质仅仅加热到低于绝缘体的分解温度的温度,从而不会伤害绝缘体。导电介质因此基本上完全填充绝缘体,从而两个接触面借助导电介质彼此接触。例如,导电介质被如下软化,以使其处于液态。特别地,导电介质是所谓的预成型件或者插入件。例如,导电介质由焊料制成,并且特别地是“预成型焊料”(Lot Preform)。为了制造,优选地将预成型件插入槽形绝缘体中。
导电介质借助绝缘体保持所期望的形状,或者在凝固之前获得期望的形状,因此能使用较大量的导电介质。因此,电路具有较高的载流能力和较大的可靠性。另外,耐温性升高,这是因为由于较大量的导电介质,即使在大电流的情况下,加热较小。在此,绝缘体可以基本上自由地成型,并且导电介质至少部分地填充绝缘体。由此,提高了设计灵活性。结构空间也被降低了。此外,由于工作步骤的数量较少,制造成本也降低了。
例如,使用合金作为导电介质,合金例如包括镓或铟或锡。换句话说,导电介质至少具有两种成分,其中一种是镓、铟或锡。特别地,合金不仅包括镓,而且还包括铟和锡。适合地,合金由这三种成分组成。特别地,合金的65%至96%由镓构成,5%至22%由铟构成,以及0%至11%由锡构成,其中,优选地存在至少一个不可忽视的锡份额,其大于一般的杂质。优选地,锡的份额大于总重量的1%。所说的百分比特别是重量百分比。这种合金以“Galinstan”的名字已知。这种合金在室温下也是液态的,从而如果电路在室温下或者至少在-19℃以上的温度下使用,则利用液态的导电介质填充绝缘体。以这种方式简化了加工。
导电介质例如以0℃与100℃之间的温度、10℃与50℃之间的温度,例如15℃与35℃之间的温度填充进绝缘体中。因此,降低了绝缘体的物理负荷,特别是由于过高的温度所引起的物理负荷,因而能够使用成本较低廉的材料来制作绝缘体。在另一替代方案中,导电介质例如是膏状并且包括导电颗粒,例如含碳颗粒或金属颗粒,其特别地溶解在粘接剂中。在此,绝缘体的热负荷也降低了。
适合地,使用导电率小于铜的导电率(即小于58x106S/m(西门子每米))的介质作为导电介质。例如,导电率小于铜的导电率的一半。因此,可以使用成本比较低廉的导电介质。因为电阻是基于导电率和几何维度确定的,也可以借助较大的尺寸产生较低的欧姆电阻。因为借助绝缘体可以基本上自由地选择导电介质的几何形状,可以选择较大的几何形状。因此,也可以借助绝缘体以及因此借助导电介质填满以下区域,该区域是以机械方式较难进入的,并且该区域例如在两个部件之间或者在底部凹陷的区域中。由于较大的尺寸,电阻被降低,因此也可以使用导电率较小的导电介质,而不会在电路的运行时存在过高的欧姆电阻以及因此过度的损耗以及因此过度的温度增长。
例如,导电介质在填充进绝缘体中之后硬化。这优选地借助添加其他化学元素来实现,从而导电介质的化学组成发生变化。特别地,在此添加额外的金属。例如,在填充进绝缘体之前加热导电介质,并且导电介质转化为(粘稠的)液态的物质状态。在填充进绝缘体之后,导电介质优选地重新冷却,使得该导电介质重新转化为固态的物质状态,但是其中,绝缘体借助导电介质被填充。以这种方式,提高了鲁棒性。在另一替代方案中,导电介质也在填充之后保持液态,并且特别是所谓的液态金属。适合地,在这种情况下导电介质是Galinstan。在此,借助绝缘体防止了导电介质的泄露。
借助绝缘体,避免了由于不希望的机械接触引起的短路。也避免了在导电介质与在其他部件处的其他组成部分之间产生电弧。在替代方案中,绝缘体由铸造制成,优选地借助塑料注射成型制成。适合地,形成绝缘体的材料填充到模具中,其例如布置在电路载体上。此外,可替代地,绝缘体相对于电路载体单独制作,并且直到完全制成后才施加到电路载体上,并且特别地连接在电路载体处。例如,在此使用所谓的丢失式型芯(verlorenerKern)。换句话说,模具具有一型芯,其在制造绝缘体的过程中被毁坏,特别是被融化。因此,绝缘体的模具可以比较自由地选择,使得制成的电路的导电介质具有自由选择的形状。
在另一替代方案中,绝缘体借助3D打印机来制造。换句话说,使用所谓的3D打印机用于制造绝缘体,其中绝缘体优选地打印到电路载体上。借助该方法,也可以比较自由地选择绝缘体的形状。
优选地,选择具有开口的绝缘体,其中,开口例如是填充开口。导电介质通过该填充开口填充进绝缘体中,这简化了制造。可替代地,开口是排气开口,在绝缘体被填充时,空气或者在绝缘体内部的其他气体能通过该排气开口逸出,使得绝缘体的机械负荷降低。优选地,绝缘体具有至少一个填充开口以及排气开口。特别优选地,开口,特别是填充开口或者排气开口,适合地是绝缘体的全部开口,即优选地是填充开口和排气开口,或填充开口和/或排气开口,在填充导电介质之后封闭。在两个接触面的区域中的两个空隙优选地保持打开。由于封闭,禁止导电介质从绝缘体溢出,因此产生比较鲁棒的电路。如果导电介质保持液态或者至少粘性的状态,则防止溢出,所以提高了电路的可靠性和鲁棒性。
在替代方案中,使用槽状绝缘体,其因此以槽或沟道的方式制成。换句话说,绝缘体至少在较大的部分上(例如其长度的一半上)具有基本上U形的横截面,其中,由于U形而形成的开口优选地以远离电路载体的方式定向。因为绝缘体的这种设计方案,简化了导电介质的填充。以这种方式,还能够确保绝缘体在较宽的区域上填充有导电介质,并且防止了没有例如因为制造公差而使得导电介质流入到特定区域中而引起的不期望的污染等。
优选地,在导电介质填充(引入)进绝缘体中之后,借助盖将绝缘体封闭。适合地,盖被设计成在封闭之后,导电介质借助绝缘体并借助盖以及借助两个接触面被基本上完全包围。因此,基本禁止了导电介质从绝缘体中溢出,即便导电介质保持液态。此外,还避免了电短路。
在另一替代方案中,除了与接触面对应的空隙以外,绝缘体被完全封闭。导电介质注射进绝缘体中,例如借助针头。在此,绝缘体借助注射装置被部分地打开,其中,绝缘体在该区域中优选地弹性变形。在填充导电介质之后,移除注射装置,并且绝缘体在开口区域被封闭,其中这优选地由于绝缘体的介质松弛而特别是自主地进行。例如,绝缘体的材料与此目的相配合。在替代方案中,设置有排气开口,使得绝缘体内部可能存在的空气或者其他气态的介质可以溢出。在另一替代方案中,绝缘体由于导电介质的注入而膨胀,其中,在填充导电介质之前,在绝缘体的内部例如没有容积或者仅仅存在很小的容积,该容积例如小于或者等于十分之一,相当于导电介质的5%或1%。
电路包括电路载体,其具有第一接触面和第二接触面。电路载体例如是电路板或MID,并且第一接触面和/或第二接触面至少彼此部分地借助印制导线或印制导线的一部分形成。特别地,第一接触面和/或第二接触面借助铜导线形成。特别优选地,接触面中的至少一个借助电子和/或电气部件的端子形成,其安置在电路载体的其他组成部分上,如与印制导线连接的端子垫上,并且特别地与该端子垫电接触。优选地,两个接触面彼此平行布置,特别地彼此错开,并且适合地,位于电路载体的同一侧面上。优选地,两个接触面彼此机械地间隔开。
两个接触面借助导电介质彼此电接触,借助绝缘体至少部分地包围该导电介质。导电介质例如是固态或者液态。特别地,导电介质是可流动的,因此至少在电路的运行温度下导电介质适合地是粘性的。绝缘体例如由塑料或硅树脂制成。
电路通过一种方法制造,其中在一个工作步骤中为电路载体提供接触面,在另一工作步骤中,将绝缘体施加到电路载体上,其中,绝缘体至少部分地覆盖第一接触面和至少一个第二接触面,并且其中,绝缘体在两个接触面的区域中分别具有空隙。在另一工作步骤中,可流动的导电介质填充进绝缘体中。
结合用于制造电路的方法所设计的实施方案和改进方案在精神上也转移到电路上,并且反之亦然。
附图说明
本发明的实施例通过附图进一步说明。其中示出:
图1示出了电路的示意性俯视图,
图2示出了用于制造电路的方法,
图3-8分别示出了在制造的中间阶段中电路的侧向剖视图,
图9示出了用于制造电路的另一方法,并且
图10-13分别示出了在制造的中间阶段中电路的侧向剖视图。
在所有附图中,互相对应的部件使用相同的附图标记。
具体实施方式
图1以俯视图示意性示出了电路2,该电路是未详细示出的逆变器的组成部分。电路2具有电路载体4,其包括基板6,基板由玻璃纤维增强的环氧树脂制成,或者在其他替代方案中由陶瓷(DCB)或者热塑性塑料(MID)制成。在基板6的表面处连接有印制导线8,印制导线由铜或其他导电材料(如银或金)制成。两个功率半导体10(例如功率半导体开关或二极管)借助SMD技术与印制导线8焊接,并且因此与印制导线8机械接触且电接触。可替代地,功率半导体10借助烧结、粘接或者焊接连接到印制导线8处,其中,例如使用THD技术。
功率半导体10在背离基板6的一侧上分别具有端子12,端子以未示出的方式与另外的印制导线电接触。印制导线8形成第一接触面14,并且每个端子12形成一个第二接触面16。在此,接触面14、16位于不同的平面并且彼此平行。此外,电路载体4具有其他电气或电子部件18,电气或电子部件与其他未详细示出的印制导线电接触。部件18例如是电容器。
图2中示出了用于制造电路2的方法20。在第一工作步骤22中,为电路载体4提供第一接触面14和第二接触面16。为此,基板6和印制导线8首先被制作为第一接触面14,功率半导体10借助SMD技术或者其他技术连接在第一接触面处。
在第二工作步骤24中,由塑料或者硅树脂制成的绝缘体26施加到电路载体4上。在此,绝缘体26例如与电路载体4分开制作,或者直接制造在电路载体上。绝缘体26借助3D打印机打印到电路载体4上。在一个替代方案中,使用铸造装置30。绝缘体26是中空体,并且为了铸造绝缘体26而借助铸造装置30使用所谓的丢失式型芯,该丢失式型芯在铸造绝缘体26时被毁坏,其中,制造绝缘体26的空腔32,如图3所示。绝缘体26至少部分地覆盖第一接触面14和第二接触面16,其中,绝缘体26在两个接触面14、16的区域中分别具有空隙34。两个空隙34借助分别对应的接触面14、16封闭。此外,绝缘体26具有填充开口36和排气开口38,它们位于绝缘体26的背离电路载体4的一侧上。每个功率半导体10在此分别配属有绝缘体26,其中,两个绝缘体26彼此间隔开。在另一替代方案中,绝缘体26在多个功率半导体10(例如两个功率半导体10)上延伸,特别是在半桥的情况下。
在第三工作步骤40中,可流动的导电介质44借助于填充装置42(例如是喷嘴)通过填充开口36填充进绝缘体26中,可流动的导电介质也进入绝缘体26的空隙34中。位于空腔32中的空气通过排气开口38溢出。导电介质44基本上完全填充绝缘体26。导电介质44是合金,其导电率小于铜的导电率的一半,并且例如基本上等于铜的导电率的四分之一。导电介质44在室温下处于固态的物质状态,并且在填充之前被加热,但是其中,加热小于导电介质44的分解温度并且低于绝缘体26的分解温度。
在第四工作步骤46中,填充开口36和排气开口38分别借助帽48封闭,从而禁止导电介质44从绝缘体26溢出。帽48由与绝缘体26相同的材料制成,并且优选地同样借助3D打印或者铸造制成。在随后的第五工作步骤50中,导电介质44被硬化。为此将其冷却。在另一替代方案中,导电介质44在开口36、38打开时硬化。为此,特别地省去了帽48,并且保留了开口36、38。可替代地,在这种情况下,开口36、38也借助帽48封闭。
在另一替代方案中,帽48由与绝缘体26不同的材料制成。在另一替代方案中,帽48作为半成品(塞子)提供,并且不通过3D打印或者铸造来制造。当通过帽48保持导电介质44封闭时,第五工作步骤50也可以完全取消。
借助导电介质44,第一接触面14以及第二接触面16彼此电接触,其中,绝缘体26并且因此通过绝缘体使得导电介质44较大面积地贴靠在电路载体4处,使得其借助电路载体4被稳固。因此,提高了可靠性并且也可以使用较大量的导电介质44,因此电阻较低,这提高了耐温性。
如果在运行时导电介质44重新转化为液态,则发生所谓的自修复过程,从而也可以实现电路2的较长使用寿命。以及,可能的最大工作温度不因为导电介质44受限制,而仅由于绝缘体26的最大工作温度而受限。
图5示出了根据图3的绝缘体26的替代实施方式,其在第二工作步骤24中借助3D打印机28或铸造装置30制造。以及,绝缘体26具有两个空隙34并且其根据图3所示的绝缘体26布置。绝缘体26构造成槽形,并且因此在背离电路载体4的侧面上具有较大的开口52。特别地,如图所示,绝缘体26在那里没有壁,使得绝缘体26基本上构造成U形。
在第三工作步骤40中,同样将可流动的导电介质44填充进绝缘体26中,并且在填充导电介质44之后,用盖54封闭绝缘体26。盖54由与绝缘体相同的材料制成,此外,执行第五工作步骤50并且导电介质44硬化。在其他替代方案中,导电介质44在绝缘体26打开时硬化。在这种情况下,绝缘体26例如保持打开,或者随后借助盖54封闭。
在另一替代方案中,盖54不必由与绝缘体26相同的材料制成。例如,盖54以半成品提供。当可流动的导电介质44通过盖54保持封闭时,也能够完全取消第五工作步骤50。
图7示出绝缘体26的另一实施方式,其在第二工作步骤24中借助3D打印机28或者铸造装置30制造,其中,在铸造时优选地存在开口,以便于移除型芯,只要型芯不被保留并且能通过导电介质44被溶解。绝缘体26除了空隙34以外没有其他的开口,并且由此设计为封闭的。绝缘体26再次布置为至少部分地覆盖第一接触面14和第二接触面16,并且绝缘体26在两个接触面14、16的区域中分别具有空隙34。
如图8所示,借助注射装置56将导电介质44注射进绝缘体26中。在此,绝缘体26借助注射装置56的注射针头58点状地打开,并且导电介质44被压入空腔32中。在借助导电介质44填充绝缘体26之后,注射针头58从绝缘体26移除,并且由于绝缘体26的弹性回弹,借助注射针头58产生的点状开口自主闭合。
在其他的设计方案中,使用在室温下也以液态的物质状态存在的导电介质44。为了硬化,在第五工作步骤50中添加额外的物质,特别是金属,从而导电介质44的合金组分被改变。在这种情况下,合金在室温下处于固态的物质状态。在另一替代方案中,完全取消第五工作步骤50,并且导电介质44在室温下也处于液态的物质状态。在此,在优选的替代方案中,使用包含镓、铟和锡的合金作为导电介质44,其中,镓的份额在65重量百分比与95重量百分比之间,铟的份额在5%与22%之间,并且锡的份额在0%与11%之间,以重量百分比计。特别是使用所谓的Galinstan作为合金。
图9示出了用于制造电路2的另一方法50。在此,也执行第一工作步骤22,并且为电路载体4提供第一接触面14和第二接触面16。在随后的第六工作步骤62中,处于固态的物质状态的导电介质44部分地安置到第一接触面14上,其中,导电介质44与第二接触面16间隔开,但导电介质在投影时覆盖在基板6上。第一接触面14基本上完全被导电介质44覆盖。导电介质44是预成型焊料,如图10所示。在替代方案中,如图11所示,导电介质44不仅部分地安置到第一接触面14上,而且也安置到第一接触面16上,从而该导电介质与两个接触面14、16直接机械接触。在另一替代方案中,导电介质44开始仅仅位于绝缘部上。然后,在后一工作步骤(第七步工作步骤64)中,实现与接触面14和16的最终接触。
在第七工作步骤64中,导电介质44借助加热装置66软化,从而导电介质部分地转化为可流动的状态。在此,导电介质44没有被完全液化,而是仅仅转化为粘性状态。因此,导电介质44紧贴到电路载体4上,并且借助导电介质44至少部分地覆盖第一接触面14和第二接触面16。导电介质44大面积地位于电路载体4上。在此,导电介质44要么机械地直接贴靠在电路载体4上,要么通过可能的未详细示出的绝缘部贴靠在电路载体上,从而避免不希望的短路。至少在电路载体4与导电介质44之间没有形成空腔等。
在随后的第八工作步骤68中,导电介质44硬化,这通过冷却完成。在随后的第九工作步骤70中,再次处于固态的物质状态的导电介质44被绝缘体26包围,绝缘体利用3D打印机28来施加。在另一未详细示出的实施方案中,借助于浸涂、喷涂、点胶或者涂装来施加绝缘体26。
在此,所有不与电路载体4贴靠的表面都借助导电介质44被绝缘体26包围。
在另一未详细示出的实施方式中,根据图5所示的变体制成绝缘体26,并且根据图10或者图11中所示的布置,将导电介质44以固态的物质状态放到绝缘体26中。之后,导电介质44借助加热装置66被加热,使得导电介质填充绝缘体26,如图6所示。之后,用盖54封闭绝缘体26。
总之,使用以下绝缘体26,其除了作为电绝缘的功能以外还容纳并且因此稳固导电介质44。绝缘体26被构造为中空体并且用作为铸造通道,其中,在特定替代方案中,绝缘体具有填充开口36、排气开口38以及空隙34。绝缘体26优选地借助铸造利用丢失式型芯来制成或者借助3D打印在基板6上制成,并且功率半导体(功率半导体开关)10在一侧借助烧结、粘接或焊接以材料配合的方式连接在基板6上。在接合之后完成绝缘体26的制造。
在制成之后,低粘度的或者液态的导电介质44例如通过填充开口36,或者开口52被填充到绝缘体26中,导电介质例如是Galinstan或者其他在填充阶段呈液态的金属合金。导电介质44在其他替代方案中是具有粘接剂的由导电颗粒制成的膏,粘结剂在填充之后硬化。在填充导电介质44之后,可以在两个接触面14、16处通过润湿和/或形成合金来形成电气结。接触也能够通过粘接剂交联或者通过合金组成的改变来实现。如果导电介质44在运行期间也保持液态,那么绝缘体26就封闭,特别是借助帽48或盖54封闭。如果借助注射装置56填充导电介质44,则在注射针头58的插入区域中由于绝缘体26的材料松弛而自主封闭,使得绝缘体26密封。
在另一替代方案中,绝缘体26以槽的方式构造,导电介质44被输入到绝缘体中,并且绝缘体随后借助盖54被覆盖。在另一替代方案中,使用预成型焊料或者其他的预成型件/插入件作为导电介质44,其借助由加热装置66实现的热引发在低于绝缘体26的材料的分解温度的情况下转化为熔融流动的状态。其中,造型出表面形貌,使得导电介质44紧靠到电路载体4的表面形貌处,并且形成与两个接触面14、16的电接触。接着,借助绝缘体26覆盖导电介质44,使得导电介质44在运行的情况下即使在熔融时也能保持位置固定。
由于导电介质44,在较短的时间内提供电导体,其具有较大的横截面,并且因此具有高载流能力。因此,可以使用具有较低导电率的导电介质作为导电介质44。
本发明不局限于前述的实施例。确切来说,本领域技术人员可以从中得出本发明的其他变体,而不脱离本发明的主题。特别是,所有结合各个实施例所描述的单独特征也能够以其他方式彼此组合,而不脱离本发明的主题。

Claims (8)

1.一种用于制造电路(2)的方法(20),其中,
-提供具有第一接触面(14)并且具有第二接触面(16)的电路载体(4),
-将绝缘体(26)施加到所述电路载体(4)上,其中,所述绝缘体(26)至少部分地覆盖所述第一接触面(14)和所述第二接触面(16),并且其中,所述绝缘体(26)在所述第一接触面(14)和所述第二接触面(16)的区域中分别具有空隙(34),其特征在于,
-在所述绝缘体(26)中填充可流动的导电介质(44),并且
-所述绝缘体(26)借助于使用丢失式型芯的铸造或者3D打印来制造。
2.根据权利要求1所述的方法(20),其特征在于,将合金用作为所述导电介质(44),所述合金至少部分地包含镓、铟和/或锡。
3.根据权利要求1所述的方法(20),其特征在于,将导电率小于铜的导电率的介质用作为所述导电介质(44)。
4.根据权利要求3所述的方法(20),其特征在于,将导电率小于铜的导电率的一半的介质用作为所述导电介质(44)。
5.根据权利要求1所述的方法(20),其特征在于,所述导电介质(44)被硬化。
6.根据权利要求1至5中任一项所述的方法(20),其特征在于,使用具有填充开口(36)和/或排气开口(38)的绝缘体(26),其中,所述填充开口(36)和/或所述排气开口(38)在填充所述导电介质(44)后被封闭。
7.根据权利要求1至5中任一项所述的方法(20),其特征在于,使用槽状的绝缘体(26),其中,该绝缘体(26)在填充所述导电介质(44)后配设有盖(54)。
8.根据权利要求1至5中任一项所述的方法(20),其特征在于,使用除了与接触面对应的所述空隙(34)以外都封闭的绝缘体(26),其中,所述导电介质(44)注入进该绝缘体(26)中。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1618129A (zh) * 2001-12-21 2005-05-18 普罗格瑞森特技术公司 负微分电阻场效应晶体管及其电路
WO2012060091A1 (ja) * 2010-11-05 2012-05-10 パナソニック株式会社 立体構造物の表面への配線方法、表面に配線が設けられた立体構造物を得るための中間構造物、及び、表面に配線が設けられた立体構造物

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4515558A (en) * 1982-01-06 1985-05-07 Gte Products Corporation Encapsulated photoflash device having a radiant energy-activated disconnect switch as part of the circuitry thereof
US4397803A (en) * 1982-01-06 1983-08-09 Gte Products Corporation Method of making a photoflash device having a radiant energy-activated disconnect switch as part of the circuitry thereof
US6344160B1 (en) * 1996-09-17 2002-02-05 Compcast Technologies, Llc Method for molding composite structural plastic and objects molded thereby
DE10065624C2 (de) * 2000-12-29 2002-11-14 Hans Kragl Kopplungsanordnung zum optischen Koppeln eines Lichtwellenleiters mit einem elektro-optischen oder opto-elektrischen Halbleiterwandler
JP2004281538A (ja) 2003-03-13 2004-10-07 Seiko Epson Corp 電子装置及びその製造方法、回路基板並びに電子機器
DE102004016205B4 (de) * 2004-03-30 2008-02-21 Sefar Ag Multilayer-Leiterplatte sowie Verfahren zum Herstellen einer solchen
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7696013B2 (en) 2007-04-19 2010-04-13 Eastman Kodak Company Connecting microsized devices using ablative films
US7870067B2 (en) * 2007-06-21 2011-01-11 Crowl Thomas C Donation system
JP5457851B2 (ja) * 2010-01-19 2014-04-02 パナソニック株式会社 照明器具
EP2731783A4 (en) * 2011-07-13 2016-03-09 Nuvotronics Llc METHOD FOR PRODUCING ELECTRONIC AND MECHANICAL STRUCTURES
US9620439B2 (en) * 2013-03-09 2017-04-11 Adventive Ipbank Low-profile footed power package
US9949376B2 (en) * 2013-12-06 2018-04-17 Second Sight Medical Products, Inc. Cortical implant system for brain stimulation and recording
US9544696B2 (en) * 2013-12-23 2017-01-10 Disney Enterprises, Inc. Flexible, shapeable free-form electrostatic speakers
US20170317223A1 (en) * 2014-08-12 2017-11-02 Ceramtec Gmbh Ceramic carrier body having solar cells
US20160118361A1 (en) * 2014-10-28 2016-04-28 Infinera Corporation Integrated circuit package structure and interface and conductive connector element for use with same
KR20160120074A (ko) * 2015-04-07 2016-10-17 (주)와이솔 반도체 패키지 및 그 제조 방법
US9837484B2 (en) * 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US20170178990A1 (en) * 2015-12-17 2017-06-22 Intel Corporation Through-mold structures
US10640369B2 (en) * 2016-07-13 2020-05-05 Hewlett-Packard Development Company, L.P. Microelectromechanical system (MEMS) devices
WO2018019921A1 (en) * 2016-07-29 2018-02-01 Trinamix Gmbh Optical sensor and detector for optical detection
JP7053786B2 (ja) * 2017-07-26 2022-04-12 ヒューレット-パッカード デベロップメント カンパニー エル.ピー. ダイコンタクト形成物
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
CN111448068A (zh) * 2017-09-12 2020-07-24 马格纳斯金属有限公司 用于零件的增材铸造的装置和方法
DE102017121914A1 (de) * 2017-09-21 2019-03-21 Endress+Hauser Conducta Gmbh+Co. Kg Sensorelement und Verfahren zum Herstellen eines Sensorelements
US20200206972A1 (en) * 2018-12-31 2020-07-02 Douglas Ray Sparks Methods of making monolithic structures and devices and monolithic structures and devices made therefrom

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1618129A (zh) * 2001-12-21 2005-05-18 普罗格瑞森特技术公司 负微分电阻场效应晶体管及其电路
WO2012060091A1 (ja) * 2010-11-05 2012-05-10 パナソニック株式会社 立体構造物の表面への配線方法、表面に配線が設けられた立体構造物を得るための中間構造物、及び、表面に配線が設けられた立体構造物

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