CN110223967A - Tri- base island packaging frame of DFN-6L - Google Patents
Tri- base island packaging frame of DFN-6L Download PDFInfo
- Publication number
- CN110223967A CN110223967A CN201910464558.8A CN201910464558A CN110223967A CN 110223967 A CN110223967 A CN 110223967A CN 201910464558 A CN201910464558 A CN 201910464558A CN 110223967 A CN110223967 A CN 110223967A
- Authority
- CN
- China
- Prior art keywords
- dao
- pin
- chip
- lead
- base island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 25
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical compound OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000009434 installation Methods 0.000 abstract description 4
- 230000006641 stabilisation Effects 0.000 abstract description 3
- 238000011105 stabilization Methods 0.000 abstract description 3
- 239000004033 plastic Substances 0.000 description 7
- 239000005022 packaging material Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007664 blowing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A kind of tri- base island packaging frame of DFN-6L, its installation that three chips can be realized using a frame, it can guarantee the stabilization of integrated circuit overall performance, area occupied and manufacturing cost can be reduced, it includes Ji Dao, pin, pin includes six, six pins are divided into two groups of upsides for being distributed in frame, downside, pin is connected by lead with the chip on Ji Dao, it is characterized in that, Ji Dao includes three, it is respectively as follows: the first Ji Dao, second Ji Dao, third Ji Dao, three islands Ge Ji successively vertical arranged in parallel from left to right, wherein one group of pin is distributed in the first Ji Dao, second Ji Dao, the upside of third Ji Dao, another set pin is distributed in the first Ji Dao, second Ji Dao, the downside of third Ji Dao.
Description
Technical field
The present invention relates to chi frame technical field, specially a kind of tri- base island packaging frame of DFN-6L.
Background technique
Chi frame is the main carriers of IC chip, realizes chip internal circuits by connecting lines such as metal wires
The electrical connection of exit and outer lead, to form electric loop, currently used chi frame includes DFN miniature electric member
The chip packaging unit of device, wherein DFN-6L is the chi frame with 6 pins, and existing DFN packaging frame is Dan Ji
Island structure can only generally place a chips on Ji Dao, as shown in Figure 1, if desired three chip collective effects realize certain function
When energy, then need to realize by way of increasing base island area or being further added by additional packaging and aerial lug, wherein increasing
Add the mode of additional packaging to refer to be packaged in three chips in frame respectively, then is connected each frame by aerial lug
It connects, the use of three frames not only reduces the stability of entire performance of integrated circuits, but also occupies compared with many areas, increases
Manufacturing cost is unable to satisfy current electronics industry miniaturization, simplifies, the demand for development of low cost.
Summary of the invention
For the installation existing in the prior art for realizing three chips using three frames, lead to integrated circuit globality
Energy is unstable, area occupied is big, manufacturing cost is high, is not able to satisfy current electronics industry miniaturization, simplifies, the development of low cost
It is required that the problem of, the present invention provides a kind of tri- base island packaging frames of DFN-6L, and three cores can be realized using a frame
The installation of piece, it is ensured that the stabilization of integrated circuit overall performance can reduce area occupied and manufacturing cost.
A kind of tri- base island packaging frame of DFN-6L comprising Ji Dao, pin, the pin include six, and described six are drawn
Foot is divided into two groups and is distributed in the upside of frame, downside, and the pin is connected by lead with the chip on Ji Dao, and feature exists
Include three in, the Ji Dao, be respectively as follows: the first Ji Dao, the second Ji Dao, third Ji Dao, three Ji Dao from left to right according to
Secondary vertical arranged in parallel, wherein pin described in one group is distributed in the upside of first Ji Dao, the second Ji Dao, third Ji Dao, separately
Pin described in outer one group is distributed in the downside of first Ji Dao, the second Ji Dao, third Ji Dao.
It is further characterized by,
The pin of upside and the pin of downside are arranged by axial symmetry of the cross central line of the frame.
The chip is respectively the first chip, the second chip, third chip, the model of first chip are as follows: 78L05,
The model of second chip are as follows: the model of ME6206A33, the third chip are as follows: LC1208CB5TR30, the pin packet
The first pin to the 6th pin is included, the lead includes first lead to the 8th lead, and first chip passes through described respectively
First lead, the second lead are connect with first pin, the 6th pin, and second chip is drawn by the third respectively
Line, the 4th lead are connect with the second pin, the 5th pin, and the third chip passes through the 6th lead and the described 4th
Pin connection, the third Ji Dao are connect by the 5th lead with the third pin, first Ji Dao and second base
It is connected between island by the 7th lead, is connected between second Ji Dao and third base island by the 8th lead
It connects.
The Ji Dao, pin are encapsulated by plastic packaging material, and the plastic packaging material is epoxy resin；
The Ji Dao, pin material be copper, the electroplate of the Ji Dao, pin.
An island Ge Ji in existing DFN-6L frame is cut into from left to right successively vertical arranged in parallel by the present apparatus
Three islands Ge Ji, install associated chip respectively on Ji Dao, no longer need to increase base island area or are further added by additional encapsulation
Frame realizes the installation of three chips by a frame, to reduce input cost, it is hardened to avoid integrated circuit
Structure complexity, the problem of product overall performance difference occur；First Ji Dao, the second Ji Dao, third Ji Dao from left to right successively it is vertical simultaneously
Row arrangement, by wherein one group of pin arrangement in the upside on three islands Ge Ji, by another set pin arrangement in the downside on three islands Ge Ji,
This arragement construction, the pin for passing through lead and two sides respectively convenient for the chip on three islands Ge Ji are all connected with, and reduce lead
Dosage reduces input cost, improves processing efficiency, ensure that the stabilization of integrated circuit overall performance.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the main view of traditional DFN-6L frame；
Fig. 2 is the structural schematic diagram of main view of the invention；
Fig. 3 is the structural schematic diagram that chip of the invention passes through that lead is connect with pin.
Specific embodiment
See Fig. 2, Fig. 3, a kind of tri- base island packaging frame of DFN-6L comprising base island 1, pin 2, pin 2 include six, point
Not Wei 21 to the 6th pin 26 of the first pin, six pins 2 are divided to for two groups of upsides for being distributed in frame, downsides, the pin of upside
Arrange that pin 2 is connected by the chip 4 on lead 3 and base island 1 by axial symmetry of the cross central line of frame with the pin 2 of downside
Connect, base island 1 includes three, be respectively as follows: the first base island 11, the second base island 12, third base island 13, three islands Ge Ji 1 from left to right according to
Secondary vertical arranged in parallel, wherein three pins 2 are distributed in the upside on the first base island 11, the second base island 12, third base island 13, in addition
Three pins 2 are distributed in the downside on the first base island 11, the second base island 12, third base island 13, chip 4 be respectively the first chip 41,
Second chip 42, third chip 43, the first chip 41, the second chip 42, third chip 43 are respectively arranged in the first base island 11,
The chip is respectively the first chip, the second chip, third chip on diyl island 12, third base island 13, first chip
Model are as follows: the model of 78L05, the second chip are as follows: the model of ME6206A33, third chip are as follows: LC1208CB5TR30, pin 2
Including 21 to the 6th pin 26 of the first pin, lead 3 includes 31 to the 8th lead 38 of first lead, and the first chip 41 passes through respectively
First lead 31, the second lead 32 are connect with the first pin 21, the 6th pin 26, and the second chip 42 passes through third lead respectively
33, the 4th lead 34 is connect with second pin 22, the 5th pin 25, and third chip 43 passes through the 6th lead 36 and the 4th pin 24
Connection, third base island 13 are connect with third pin 23 by the 5th lead 35, are passed through between the first base island 11 and the second base island 12
The connection of 7th lead 37, is connected between the second base island 12 and third base island 13 by the 8th lead 38, base island 1, pin 3 pass through
Plastic packaging material encapsulation, plastic packaging material is epoxy resin, base island 1, pin 2 material be copper, base island 1, the surface of pin 3 are silver-plated.
That the specific working principle is as follows is described for it: being packaged to tri- base island frame of DFN-6L, in overall appearance, size and draws
In the case that foot spacing is constant, an island Ge Ji is changed to three islands Ge Ji, a chip is installed respectively on each Ji Dao, is realized
The encapsulation of three chips in one product, the encapsulation of frame can be used existing packaging technology and realize, specific: in the first Ji Dao
11, the second base island 12, put bonding die glue respectively on third base island 13, the first chip 41 is bonded on the first base island 11, by second
Chip 42 is bonded on the second base island 12, by lead by the first chip 41, the second chip 42, third chip 43 respectively with respectively draw
Foot 2 connects, and rear entirety is put into mould pressing die, and high temperature injects plastic packaging material, by the first chip 41 to third chip 43, the first base
Island 11 to third base island 13,21 to the 6th pin 26 of the first pin a part, be surrounded, constitute packaging part, then pass through
Mode of blowing a cold wind over is cooling by entire packaging part, and plastic packaging material forms plastic-sealed body under cooling effect, the frame after plastic packaging is put into super
Ultra sonic scanner instrument (SONOSCAN company, the U.S.) has detected whether gas hole, to detect the delamination of packaging part, passes through inspection
It surveys, this encapsulating structure tool is well bonded.
Three islands Ge Ji 1 are set on frame, and the first base island 11, the second base island 12, third base island 13 are successively erected from left to right
To arranged in parallel on frame, pin 2 is divided to two groups of upsides for being distributed in frame, downsides, and the pin of the pin 2 of upside and downside
2 arrange by axial symmetry of the center line of frame, not only make all parts arrangement in frame neat, but also make the entirety point of frame
Cloth is simple and reasonable, is convenient for chip array and lead, so as to effectively reduce the layering between base island 1 and plastic-sealed body,
Ensure to have between the frame 3 and plastic-sealed body and be well bonded；Chip 4 on base island 1 can by lead respectively with two sides
Pin is all connected with, and can be arranged in chip 4 on the Ji Dao adjacent with one group of pin that the chip 4 is connected, and the length of lead is made
Degree greatly shortens, and the reduction of lead deformation hidden danger and the reduction of lead dosage can be further reduced between frame and plastic-sealed body
Layering, it is ensured that between the frame and plastic-sealed body tool be well bonded；If by three islands Ge Ji by successively parallel from the top down
Mode arrange, then the lead of the chip on intermediate base island need to be connect across the Ji Dao of wherein side with pin 2, not only be increased
The length of the lead added, and lead easily with this across on Ji Dao chip or conducting wire generation be electrically connected short circuit etc. caused to be asked
Topic, can effectively avoid the generation of the problem using the arragement construction of this frame；
Three packaging part assembled packages of existing relevant effect in a packaging part, are reduced outside and connected by this frame
Line has saved packaging cost, while the reduction of aerial lug can effectively reduce interference of the external environment to packaging part overall performance,
Improve product stability；This frame will need to be substituted by the function that two or more packaging parts are realized by a packaging part, and
Volume shared by it is identical as a packaging body, enormously simplifies the structure of integrated circuit board, reduces manufacturing cost.
Claims (3)
1. a kind of tri- base island packaging frame of DFN-6L comprising Ji Dao, pin, the pin include six, six pins
It is divided into two groups and is distributed in the upside of frame, downside, the pin is connected by lead with the chip on Ji Dao, and feature exists
Include three in, the Ji Dao, be respectively as follows: the first Ji Dao, the second Ji Dao, third Ji Dao, three Ji Dao from left to right according to
Secondary vertical arranged in parallel, wherein pin described in one group is distributed in the upside of first Ji Dao, the second Ji Dao, third Ji Dao, separately
Pin described in outer one group is distributed in the downside of first Ji Dao, the second Ji Dao, third Ji Dao.
2. tri- base island packaging frame of a kind of DFN-6L according to claim 1, which is characterized in that the pin of upside and
The pin of downside is arranged by axial symmetry of the cross central line of the frame.
3. tri- base island packaging frame of a kind of DFN-6L according to claim 1, which is characterized in that the chip is respectively
One chip, the second chip, third chip, the model of first chip are as follows: the model of 78L05, second chip are as follows:
The model of ME6206A33, the third chip are as follows: LC1208CB5TR30, the pin include the first pin to the 6th pin,
The lead includes first lead to the 8th lead, and first chip passes through the first lead, the second lead and institute respectively
The first pin, the connection of the 6th pin are stated, second chip is drawn by the third lead, the 4th lead with described second respectively
Foot, the connection of the 5th pin, the third chip are connect by the 6th lead with the 4th pin, and the third Ji Dao is logical
It crosses the 5th lead to connect with the third pin, be connected between first Ji Dao and second base island by the 7th lead
It connects, is connected between second Ji Dao and third base island by the 8th lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910464558.8A CN110223967A (en) | 2019-05-30 | 2019-05-30 | Tri- base island packaging frame of DFN-6L |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910464558.8A CN110223967A (en) | 2019-05-30 | 2019-05-30 | Tri- base island packaging frame of DFN-6L |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110223967A true CN110223967A (en) | 2019-09-10 |
Family
ID=67818679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910464558.8A Pending CN110223967A (en) | 2019-05-30 | 2019-05-30 | Tri- base island packaging frame of DFN-6L |
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| Country | Link |
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| CN (1) | CN110223967A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08195470A (en) * | 1995-01-19 | 1996-07-30 | Murata Mfg Co Ltd | Lead frame for semiconductor integrated circuit, and semiconductor integrated circuit |
| JP2002373964A (en) * | 2001-06-14 | 2002-12-26 | Nec Kansai Ltd | Lead frame |
| CN103855120A (en) * | 2012-12-06 | 2014-06-11 | 美格纳半导体有限公司 | Multichip package and fabrication method thereof |
| CN105742269A (en) * | 2014-12-26 | 2016-07-06 | 瑞萨电子株式会社 | Method of Manufacturing Semiconductor Device |
| US20170263542A1 (en) * | 2016-03-14 | 2017-09-14 | Chang Wah Technology Co., Ltd. | Preformed lead frame device and lead frame package including the same |
| CN108962844A (en) * | 2018-06-04 | 2018-12-07 | 瑞能半导体有限公司 | Chip packing-body and packaging method |
| CN209929295U (en) * | 2019-05-30 | 2020-01-10 | 无锡红光微电子股份有限公司 | DFN-6L three-base island packaging frame |
-
2019
- 2019-05-30 CN CN201910464558.8A patent/CN110223967A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08195470A (en) * | 1995-01-19 | 1996-07-30 | Murata Mfg Co Ltd | Lead frame for semiconductor integrated circuit, and semiconductor integrated circuit |
| JP2002373964A (en) * | 2001-06-14 | 2002-12-26 | Nec Kansai Ltd | Lead frame |
| CN103855120A (en) * | 2012-12-06 | 2014-06-11 | 美格纳半导体有限公司 | Multichip package and fabrication method thereof |
| CN105742269A (en) * | 2014-12-26 | 2016-07-06 | 瑞萨电子株式会社 | Method of Manufacturing Semiconductor Device |
| US20170263542A1 (en) * | 2016-03-14 | 2017-09-14 | Chang Wah Technology Co., Ltd. | Preformed lead frame device and lead frame package including the same |
| CN108962844A (en) * | 2018-06-04 | 2018-12-07 | 瑞能半导体有限公司 | Chip packing-body and packaging method |
| CN209929295U (en) * | 2019-05-30 | 2020-01-10 | 无锡红光微电子股份有限公司 | DFN-6L three-base island packaging frame |
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