CN108962844A - Chip packing-body and packaging method - Google Patents
Chip packing-body and packaging method Download PDFInfo
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- CN108962844A CN108962844A CN201810563822.9A CN201810563822A CN108962844A CN 108962844 A CN108962844 A CN 108962844A CN 201810563822 A CN201810563822 A CN 201810563822A CN 108962844 A CN108962844 A CN 108962844A
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 14
- 238000005538 encapsulation Methods 0.000 claims description 12
- 238000001816 cooling Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 8
- 238000009826 distribution Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 15
- 230000017525 heat dissipation Effects 0.000 description 10
- 238000003466 welding Methods 0.000 description 10
- 239000000047 product Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Basic Packing Technique (AREA)
Abstract
The invention discloses a kind of chip packing-body and packaging methods.The chip packing-body includes: lead frame (10), and the lead frame (10) has multiple Ji Dao (11) and multiple cathode pins (12)；Multiple chips (20), the multiple chip (20) and the multiple Ji Dao (11) correspond, and the anode of each chip (20) is electrically connected to corresponding Ji Dao (11)；And the cathode of first conductive sheet (30), first conductive sheet (30) and each cathode pin (12) and each chip (20) is electrically connected with together.By the above-mentioned description to chip packing-body as can be seen that being welded on the cathode of the chip 20 of all chips using the first conductive sheet 30 of one piece of large area, compared to traditional conductive wire bonding, thermal diffusivity and the ability for bearing high current are greatly improved.And DFN technology is combined, special equipment investment is not needed, manufacturability and changeability are more preferable.
Description
Technical field
The invention belongs to semiconductor chip packaging field more particularly to a kind of chip packing-body and packaging methods.
Background technique
Chip can be widely used for the fields such as industry, traffic, household electrical appliance, open with AC voltage adjusting, electric machine speed regulation, exchange
Close control, street lamp automatically turns on and the multiple functions such as closing, temperature control, desk lamp light modulation, stage adjusting light.The encapsulation of current chip
Structure, occupancy PCB volume is big, radiates bad, it is therefore desirable to propose new change to existing chip packing-body and its packaging method
Into.
Summary of the invention
The embodiment of the invention provides a kind of chip packing-body and its packaging method, it is able to solve chip envelope in the prior art
It fills body poor radiation and occupies the big problem of pcb board area.
One aspect of the present invention provides a kind of chip packing-body, and the chip packing-body includes:
Lead frame, the lead frame have multiple Ji Dao and multiple cathode pins；
Multiple chips, the multiple chip are arranged in a one-to-one correspondence with the multiple Ji Dao, and make each chip just
Pole is electrically connected to corresponding Ji Dao；And
The cathode of first conductive sheet, each cathode pin and each chip is electric with first conductive sheet
Connection.
Optionally, first conductive sheet covers the cathode of all chips on the lead frame and all described negative
Pole pipe foot.
Optionally, there is first conductive sheet conductive sheet ontology to connect with the chip being set on the conductive sheet ontology
Portion and pin interconnecting piece, for connecting with the cathode of the chip, the pin interconnecting piece is used for and institute the chip interconnecting piece
State the connection of cathode pin.
Optionally, the conductive sheet ontology is plate-like, and arranges with the multiple chip laminate, the pin interconnecting piece
Number is multiple, and is corresponded with the multiple cathode pin, length of the pin interconnecting piece in the conductive sheet ontology
Distribution is spaced apart from each other on direction, each pin interconnecting piece is in the width direction of the conductive sheet ontology by the conductive sheet
Ontology extends outward to form.
Optionally, the chip interconnecting piece and/or the pin interconnecting piece be formed in it is convex on the conductive sheet ontology
Play structure.
Optionally, the lead frame also has the multiple controls being arranged in a one-to-one correspondence with the control electrode of the multiple chip
Pole pipe foot, each control electrode pin are located at the side of corresponding Ji Dao；
The chip packing-body further includes multiple conducting connecting parts；
Wherein, each control electrode pin passes through a conducting connecting part electricity with the control electrode of corresponding chip
Connection.
Optionally, the conducting connecting part is the second conductive sheet or conductor wire.
Optionally, the chip packing-body further includes for encapsulating the lead frame, the multiple chip and described
The DFN encapsulating structure of first conductive sheet, the DFN encapsulating structure be set as making first conductive sheet, each Ji Dao with
And each cathode pin at least partly exposes the DFN encapsulating structure.
Optionally, the chip packing-body further includes cooling fin, and the cooling fin is set to the dew of first conductive sheet
On surface for the DFN encapsulating structure.
Another aspect of the present invention provides a kind of packaging method of chip packing-body, comprising the following steps:
The step of providing lead frame, lead frame have multiple Ji Dao and multiple cathode pins；
Each of the step of chip is arranged, provides multiple chips, each chip is correspondingly arranged on the lead frame
On Ji Dao, and the anode of each chip is made to be electrically connected to corresponding Ji Dao；
First conductive sheet is set to the cathode of all chips and all negative by the step of the first conductive sheet is arranged
On pole pipe foot, the cathode of each cathode pin and each chip is connected electrically in one by first conductive sheet
It rises；
The control electrode electrical connecting step of the chip, by the control of the control electrode pin of lead frame and corresponding chip
Pole is electrically connected；
Encapsulation step implements encapsulation to the lead frame for being loaded with chip, the first conductive sheet, to form chip packing-body.
Optionally, in the control electrode electrical connecting step of the chip, using conducting connecting part by the control electrode of lead frame
The control electrode of pin and corresponding chip is electrically connected；
Wherein, the conducting connecting part is the second conductive sheet and/or conductor wire.
Optionally, when the conducting connecting part uses the second conductive sheet, the step of the first conductive sheet of the setting and institute
It states in the control electrode electrical connecting step of chip, first conductive sheet is implemented to weld simultaneously with the second conductive sheet.
Compared with prior art, chip packing-body provided by the embodiments of the present application utilizes the first conductive sheet of one piece of large area
It is welded on the cathode of all chips, compared to traditional conductive wire bonding, thermal diffusivity and the ability for bearing high current are greatly improved.
And DFN technology is combined, special equipment investment is not needed, manufacturability and changeability are more preferable.
Other beneficial effects of the invention can be further explained in detail in specific embodiment.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will make below to required in the embodiment of the present invention
Attached drawing is briefly described, it should be apparent that, drawings described below is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the circuit diagram of the chip packing-body of one embodiment of the invention.
Fig. 2 is the structural schematic diagram of the lead frame of one embodiment of the invention.
Fig. 3 is the schematic diagram being arranged on the lead frames after chip in one embodiment of the invention.
Fig. 4 is to weld one first conductive sheet in one embodiment of the invention on the cathode of all chips and all cathode pins
Schematic diagram afterwards.
Fig. 5 is to weld second in the control electrode of each chip and corresponding control electrode pin in one embodiment of the invention
Schematic diagram after conductive sheet.
Fig. 6 is the schematic diagram of chip in one embodiment of the invention.
Fig. 7 is the schematic cross-section of the first conductive sheet in one embodiment of the invention.
Fig. 8 is the positive stereoscopic schematic diagram of chip packing-body in one embodiment of the invention.
Fig. 9 is the stereoscopic schematic diagram at the chip packing-body back side in one embodiment of the invention.
In attached drawing:
10- lead frame；11- Ji Dao；12- cathode pin；13- control electrode pin；
20- chip；21- cathode；22- control electrode；
The first conductive sheet of 30-；31- chip interconnecting piece；32- pin interconnecting piece；33- conductive sheet ontology；
40- conducting connecting part.
Specific embodiment
The feature and exemplary embodiment of various aspects of the invention is described more fully below.In following detailed description
In, many details are proposed, in order to provide complete understanding of the present invention.But to those skilled in the art
It will be apparent that the present invention can be implemented in the case where not needing some details in these details.Below to implementation
The description of example is used for the purpose of providing by showing example of the invention and better understanding of the invention.
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.Embodiment is described in detail below in conjunction with attached drawing.
Fig. 1 shows the circuit diagram of the chip packing-body of the embodiment of the present invention.Chip packing-body in the present embodiment
Packaged number of chips is three and (only describes technical solution of the present invention as example, actual quantity can be two, four
It is a or more), each chip all has anode, cathode and control electrode, in the present embodiment using the side for sharing cathode
Formula, and the connection circuit of the connection circuit of cathode and control electrode is directly packaged in chip package body, and use multiple cores
Piece is integrated in the intracorporal mode of encapsulation, has saved the area occupied of pcb board, and encapsulate in present embodiment using DFN,
To keep the product of chip packing-body thin, and it is few more many than traditional exposed pin package to encapsulate raw material usage, so sealing
Dress raw material usage and cost reduce again.In addition, being welded on multiple silicon chips just using one piece of first conductive sheet of large area 30
Face, also the ability than the heat dissipation performance of traditional welding manner and receiving high current is all high.
In conjunction with refering to Fig. 2 to Fig. 5, which respectively show the structural schematic diagram of lead frame 10, on the lead frames it is arranged
Schematic diagram after chip, welded on the cathode and all cathode pins of all chips the schematic diagram after one first conductive sheet and
Schematic diagram after welding the second conductive sheet in the control electrode of each chip and corresponding control electrode pin.It is described in Fig. 2
Lead frame 10 has multiple base islands 11 and multiple cathode pins 12；Wherein, installation site of the base island 11 as chip 20 can be used
In welding chip 20, cathode pin 12 with the cathode traces on pcb board for being electrically connected.Further combined with Fig. 6, show
The schematic diagram of chip 20 in the present embodiment, the one side of chip 20 are cathode 21, and another side is anode, in a corner of chip 20 position
Setting also has control electrode 22.
In conjunction with refering to Fig. 5, chip packing-body provided by the present embodiment includes: that lead frame 10, multiple chips 20 are (coating
Cover the lower section in first conductive sheet 30) and the first conductive sheet 30, the multiple chip 20 and the multiple base island 11 1
One is corresponding, and the anode of each chip 20 is electrically connected to corresponding base island 11；First conductive sheet 30 and each institute
The cathode for stating cathode pin 12 and each chip 20 is connected together, to make in entire chip packing-body
Chip shares cathode, and using the first conductive sheet 30 come the cathode of welding chip, heat dissipation area is big, and thermal diffusivity is preferable.
In one embodiment of the present invention, in order to improve heat dissipation performance and bear the ability of high current, larger cover is set
First conductive sheet 30 of capping product, size can cover the cathode and all cathode pins 12 of all chips 20.Fig. 3 is originally to apply
The schematic diagram after chip 20 is set on the lead frames in example, in Fig. 4 by the first conductive sheet 30 be covered on all chips 20 and
Cathode pin 12, the first conductive sheet 30 are a slab construction, and shape is according to the position of chip 20 and the position of cathode pin 12
And it is arranged.It certainly, can there are many forms, as much as possible covering chip for the coverage area of practical first conductive sheet 30
20 cathode 21 is preferred, and covering cathode pin 12 as much as possible is preferred, space, multiple cathode tubes between multiple chips 20
The space between space and chip 20 and cathode pin 12 between foot 12 is covered using the first conductive sheet 30 as much as possible.
First conductive sheet 30 has biggish area coverage, has the advantages that at least following both sides:
On the one hand, the electric conductivity for improving the first conductive sheet 30, since its area coverage is big, then its resistance value becomes
It is relatively small, so conductor wire is compared, with better electric conductivity；On the other hand, radiating rate, the first conductive sheet 30 are improved
Area it is bigger, heat dissipation area is also bigger, and heat dissipation effect is naturally also improved.
Further combined with Fig. 7, first conductive sheet 30 has conductive sheet ontology 33 and is set to the conductive sheet ontology 33
On chip interconnecting piece 31 and pin interconnecting piece 32, wherein the cathode of the chip interconnecting piece 31 and the chip 20 welds, institute
It states pin interconnecting piece 32 and the cathode pin 12 welds.Chip interconnecting piece 31 and pin interconnecting piece 32 can be convenient for the first conductive sheet
30 with the welding of the cathode 21 and cathode pin 12 of chip 20.Specifically, the conductive sheet ontology 33 is plate-like, and with it is described
Multiple 20 arranged stackeds of chip, the number of the pin interconnecting piece 32 are multiple, and a pair of with the multiple cathode pin 12 1
It answers, the pin interconnecting piece 32 is spaced apart from each other distribution on the length direction of the conductive sheet ontology 33, and each pin connects
Socket part 32 is extended outward to form in the width direction of the conductive sheet ontology 33 by the conductive sheet ontology 33.
The specific set-up mode of chip interconnecting piece 31 and pin interconnecting piece 32 can also be following form:
The chip interconnecting piece 31 and/or the pin interconnecting piece 32 be formed in it is convex on the conductive sheet ontology (33)
Play structure.The top of chip interconnecting piece 31 is a flat surface, the area of plane according to the cathode 21 of chip 20 real area and set
It sets, the mode that punching press can be used in the generation type of chip interconnecting piece 31 is formed；The pin interconnecting piece 32 is strip structure, bar shaped
The length of structure according to cathode pin 12 size and be arranged, the generation type of strip structure can be the shape by way of bending
At.According to Fig. 7, certain space will form between chip interconnecting piece 31 and pin interconnecting piece 32, can be convenient for the circulation of air, from
And keep the heat dissipation effect of the first conductive sheet 30 more preferable.
It is a kind of in order to enhance the electric conductivity of the first conductive sheet 30 and the welding of the cathode 21 and cathode pin 12 of chip 20
Preferably embodiment are as follows: (herein referred to and the cathode 21 of chip 20 and negative on the surface of above-mentioned planar projections and strip bulge
The face that pole pipe foot 12 contacts) setting annular knurl, equally distributed small protrusion or little groove are either set, so as to increase its surface
Roughness, keep welding effect more preferable, electric conductivity is also further enhanced.
Further, the material of the first conductive sheet 30 can be for convenient for conductive any material, in the present embodiment, institute
Copper can be selected in the present embodiment for copper conductive sheet or aluminum conductive sheet or golden conductive sheet by stating the first conductive sheet 30
For matter conductive sheet as preferred forms, excellent heat dissipation performance, manufacturing cost are low, and conduct electricity very well.
In conjunction with Fig. 2, the lead frame 10 is also arranged in a one-to-one correspondence with the control electrode with the multiple chip 20 more
A control electrode pin 13；Chip packing-body in the present embodiment further includes multiple conducting connecting parts 40, for connecting chip 20
Control electrode 22 and control electrode pin 13, specifically, conducting connecting part 40 can be the second conductive sheet or conductor wire.It can be according to core
The size of the control electrode 22 of piece 20 specifically uses the second conductive sheet or conductor wire to determine, normally, if control electrode
22 area is greater than 0.4mmx0.4mm, can use better second conductive sheet of thermal diffusivity, and the second conductive sheet 40 is that a bar shaped is led
Electric piece, length according to chip 20 22 distance controlling pole pipe foot 13 of control electrode actual range and be arranged, material usually with
First conductive sheet 30 is identical.Wherein, the control electrode 22 of multiple control electrode pins 13 and multiple chips 20 corresponds, each described
Control electrode pin 13 is electrically connected with the control electrode of corresponding chip 20 by the conducting connecting part 40.The mode of electrical connection
It can be and welded using scolding tin, be also possible to be bonded by conducting resinl, solidification processing can be carried out after bonding.
Further, in conjunction with Fig. 8 and Fig. 9, the chip packing-body further includes DFN encapsulating structure 50, and DFN encapsulating structure 50 is used
In the encapsulation lead frame 10, the multiple chip 20 and first conductive sheet 30, and the DFN encapsulating structure 50 is set
Being set to makes described in first conductive sheet 30, each base island 11 and each cathode pin 12 at least partly expose
DFN encapsulating structure 50.The DFN encapsulating structure 50 is exposed in first conductive sheet, 30 part, can be convenient for heat dissipation, so as to improve core
The working environment of piece 20.That is in the present embodiment, chip packing-body uses DFN packaging technology, and product is made to have frivolous property
The characteristics of.Preferably, the chip packing-body further includes cooling fin (not shown), the cooling fin is set to exposed
The outer surface of one conductive sheet 30.Cooling fin can further speed up the radiating rate of the first conductive sheet 30.
By the above-mentioned description to chip packing-body as can be seen that being welded on using the first conductive sheet 30 of one piece of large area
The cathode of the chip 20 of all chips, compared to traditional conductive wire bonding, thermal diffusivity and the ability for bearing high current mention significantly
It is high.And DFN technology is combined, special equipment investment is not needed, manufacturability and changeability are more preferable.
In conjunction with said chip packaging body, the present embodiment also provides a kind of packaging method of chip packing-body, mainly include with
Lower step:
The step of lead frame 10 are provided, the lead frame 10 with multiple base islands 11 and multiple cathode pins 12；
The step of chip 20 are arranged, provides multiple chips 20, each chip 20 is correspondingly arranged in the lead frame 10
On each base island 11 on, and the anode of each chip 20 is made to be electrically connected to corresponding base island 11；
First conductive sheet 30 is set to cathode and the institute of all chips 20 by the step of the first conductive sheet 30 are arranged
On some cathode pins 12, by first conductive sheet 30 by each cathode pin 12 and each chip 20
Cathode is electrically connected；
The control electrode electrical connecting step of the chip 20, by the control electrode pin 13 and corresponding chip of lead frame 10
20 control electrode is electrically connected；
Encapsulation step implements encapsulation to the lead frame 10 for being loaded with chip 20, the first conductive sheet 30, to form chip package
Body.
Wherein, in the control electrode electrical connecting step of the chip 20, using conducting connecting part 40 by lead frame 10
The control electrode of control electrode pin 13 and corresponding chip 20 is electrically connected, and the conducting connecting part 40 is chosen as second and leads
Electric piece or conductor wire.
When the conducting connecting part 40 is using the second conductive sheet, the step of the first conductive sheet 30 of the setting and the core
In the control electrode electrical connecting step of piece 20, first conductive sheet 30 is implemented to weld simultaneously with the second conductive sheet.
Specifically, it in the step of lead frame 10 are provided and the step of chip 20 are set, first provides one and is suitable for reality
The lead frame 10 of chip packing-body, then on lead frame 10 point plus printing or solder application, and simultaneously place three
Chip 20 is on three independent base islands 11, wherein being placed on the anode of chip 20 on base island 11.Solder is preferably high thermal conductivity
Liquid alloy, such as: Pb92.5Sn5Ag2.5 tin cream.
In the step of the first conductive sheet 30 are set, first on the cathode and three cathode pins 12 of three chips 20 on point
The solder of same material, then place one first conductive sheet 30 and 20 positive three cathode 21 of chip and cathode pin 12 are passed through
Same first conductive sheet 30 is electrically connected.In general, can make to weld with Reflow Soldering baking oven after the first conductive sheet 30 places
Material solidification, so that chip 20 and the first conductive sheet 30 are fixed on lead frame 10.
In the control electrode electrical connecting step of the chip 20, if the area of control electrode 22 is sufficiently large, conducting connecting part 40
It is chosen as the second conductive sheet, specifically sees the description of hereinbefore chip packing-body.When the second conductive sheet electric connecting wire of selection
When the control electrode of the control electrode pin 13 of frame 10 and corresponding chip 20, first conductive sheet 30 and the second conductive sheet are same
When implement welding and solder solidification, to save processing step.
In encapsulation step, the technique of traditional DFN encapsulation can be used to complete, final product shape structure is at least
Two kinds optional, is total incapsulation (relevant drawings are not shown) one is the front of chip packing-body, this mode requires encapsulation low.
But in order to improve thermal diffusivity, another product shape structure is that the front of chip packing-body is made to expose the first conductive sheet 30, from
And convenient for heat dissipation.That is, making the DFN encapsulating structure 50 to be formed package be loaded with the lead frame of chip 20 in the S4
10, and make the one surface exposed of the first conductive sheet 30.In practical applications, in order to further improve heat dissipation performance, described
In S4, the surface setting cooling fin of the first exposed conductive sheet 30 may additionally include.Wherein, cooling fin is after the completion of DFN is encapsulated
Setting, the adhesion external application cooling fin again usually on the exposed copper material of the first conductive sheet 30.
In the present embodiment, for other techniques of DFN packaging technology, it will not go into details, and those skilled in the art can be according to normal
It advises technological means and carries out reasonability setting.
Volume description is it can be seen that the first conductive sheet 30 using large area realizes chip packing-body through the above technical solution
Shared cathode welding, not only make production chip packing-body product have preferable thermal diffusivity and and high conductivity, and
And can realize the synchronism of multiple chip cathode welding, it is improved packaging efficiency；On the other hand, the first conductive sheet is shared
The technology and DFN packaging technology of cathode combine, and make to also ensure while product has compared with high-cooling property and high conductivity
Frivolous property, manufacturability and the changeability of product.
In addition, the terms " and/or ", a kind of only incidence relation for describing affiliated partner, expression can be with
There are three kinds of relationships, for example, A and/or B, can indicate: individualism A, exist simultaneously A and B, individualism B these three
Situation.In addition, character "/" herein, typicallys represent the relationship that forward-backward correlation object is a kind of "or".
It should be understood that in embodiments of the present invention, " B corresponding with A " indicates that B is associated with A, B can be determined according to A.But
It should also be understood that determining that B is not meant to determine B only according to A according to A, B can also be determined according to A and/or other information.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or replace
It changes, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection scope subject to.
Claims (12)
1. a kind of chip packing-body, which is characterized in that the chip packing-body includes:
Lead frame (10), the lead frame (10) have multiple Ji Dao (11) and multiple cathode pins (12)；
Multiple chips (20), the multiple chip (20) are arranged in a one-to-one correspondence with the multiple Ji Dao (11), and make each described
The anode of chip (20) is electrically connected to corresponding Ji Dao (11)；And
The cathode of first conductive sheet (30), each cathode pin (12) and each chip (20) is with described first
Conductive sheet (30) electrical connection.
2. chip packing-body according to claim 1, which is characterized in that first conductive sheet (30) covers the lead
The cathode of all chips (20) on frame (10) and all cathode pins (12).
3. chip packing-body according to claim 1, which is characterized in that first conductive sheet (30) has conductive sheet sheet
Body (33) and the chip interconnecting piece (31) and pin interconnecting piece (32) being set on the conductive sheet ontology (33), the chip connect
For connecting with the cathode of the chip (20), the pin interconnecting piece (32) is used for and the cathode pin (12) socket part (31)
Connection.
4. chip packing-body according to claim 3, which is characterized in that the conductive sheet ontology (33) is plate-like, and with
The multiple chip (20) arranged stacked, the number of the pin interconnecting piece (32) are multiple, and with the multiple cathode pin
(12) it corresponding, the pin interconnecting piece (32) is spaced apart from each other distribution on the length direction of the conductive sheet ontology (33),
Each pin interconnecting piece (32) in the width direction of the conductive sheet ontology (33) from the conductive sheet ontology (33) to
It extends to form outside.
5. chip packing-body according to claim 3, which is characterized in that the chip interconnecting piece (31) and/or the pipe
Foot interconnecting piece (32) is the bulge-structure being formed on the conductive sheet ontology (33).
6. chip packing-body according to claim 1, which is characterized in that the lead frame (10) also have with it is described more
Multiple control electrode pins (13) that the control electrode of a chip (20) is arranged in a one-to-one correspondence, each control electrode pin (13) are located at
The side of corresponding Ji Dao (11)；
The chip packing-body further includes multiple conducting connecting parts (40)；
Wherein, each control electrode pin (13) passes through a conductive connection with the control electrode of corresponding chip (20)
Part (40) electrical connection.
7. chip packing-body according to claim 6, which is characterized in that the conducting connecting part (40) is the second conductive sheet
Or conductor wire.
8. chip packing-body according to claim 1, which is characterized in that the chip packing-body further includes for encapsulating
The DFN encapsulating structure (50) of lead frame (10), the multiple chip (20) and first conductive sheet (30) is stated, it is described
DFN encapsulating structure (50) is set as making first conductive sheet (30), each Ji Dao (11) and each cathode tube
Foot (12) at least partly exposes the DFN encapsulating structure (50).
9. chip packing-body according to claim 8, which is characterized in that the chip packing-body further includes cooling fin, institute
It states cooling fin and is set to being exposed on the surface of the DFN encapsulating structure (50) of first conductive sheet (30).
10. a kind of packaging method of chip packing-body, which comprises the following steps:
The step of providing lead frame (10), lead frame (10) have multiple Ji Dao (11) and multiple cathode pins (12)；
The step of chip (20) are arranged, provides multiple chips (20), each chip (20) is correspondingly arranged in the lead frame
(10) on each Ji Dao (11) on, and the anode of each chip (20) is made to be electrically connected to corresponding Ji Dao (11)；
The step of first conductive sheet (30) are set, by first conductive sheet (30) be set to all chips (20) cathode and
It is by each cathode pin (12) and each described by first conductive sheet (30) on all cathode pins (12)
The cathode of chip (20) is electrically connected；
The control electrode electrical connecting step of the chip (20), by the control electrode pin (13) of lead frame (10) and corresponding core
The control electrode of piece (20) is electrically connected；
Encapsulation step implements encapsulation to the lead frame (10) for being loaded with chip (20), the first conductive sheet (30), to form chip envelope
Fill body.
11. packaging method according to claim 10, which is characterized in that the control electrode electrical connecting step of the chip (20)
In, using conducting connecting part (40) by the control electrode of the control electrode pin (13) of lead frame (10) and corresponding chip (20)
It is electrically connected；
Wherein, the conducting connecting part (40) is the second conductive sheet and/or conductor wire.
12. packaging method according to claim 11, which is characterized in that
When the conducting connecting part (40) use the second conductive sheet, the step of setting the first conductive sheet (30) and the core
In the control electrode electrical connecting step of piece (20), first conductive sheet (30) implements to weld simultaneously with the second conductive sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810563822.9A CN108962844A (en) | 2018-06-04 | 2018-06-04 | Chip packing-body and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810563822.9A CN108962844A (en) | 2018-06-04 | 2018-06-04 | Chip packing-body and packaging method |
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| Publication Number | Publication Date |
|---|---|
| CN108962844A true CN108962844A (en) | 2018-12-07 |
Family
ID=64493157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810563822.9A Pending CN108962844A (en) | 2018-06-04 | 2018-06-04 | Chip packing-body and packaging method |
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| Country | Link |
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| CN (1) | CN108962844A (en) |
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| WO2022174396A1 (en) * | 2021-02-19 | 2022-08-25 | 华为数字能源技术有限公司 | Encapsulation structure, power electrical control system and manufacturing method |
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Address after: 330200 Jiangxi city of Nanchang Province, Nanchang County Blue Road Economic Development Zone No. 266 Building 2 Applicant after: Ruineng Semiconductor Technology Co., Ltd. Address before: 330200 Jiangxi city of Nanchang Province, Nanchang County Blue Road Economic Development Zone No. 266 Building 2 Applicant before: Supportan Semiconductor Co. Ltd. |