CN104851863B - A kind of integrated circuit, wire bond package chip and flip-chip packaged chip - Google Patents
A kind of integrated circuit, wire bond package chip and flip-chip packaged chip Download PDFInfo
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- CN104851863B CN104851863B CN201510185457.9A CN201510185457A CN104851863B CN 104851863 B CN104851863 B CN 104851863B CN 201510185457 A CN201510185457 A CN 201510185457A CN 104851863 B CN104851863 B CN 104851863B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a kind of integrated circuit, wire bond package chip and flip-chip packaged chip, belong to technical field of semiconductors.Integrated circuit includes：Bare chip；At least one pad group, at least one pad group are fixed on the active face of bare chip, with including the first signal pad group, secondary signal pad group, the first power supply pad group and second source ground the pad group of each pad group at least one pad group；First signal pad group and secondary signal pad group include at least one signal pad respectively, the first power supply ground pad group and second source ground pad group with including at least one power supply respectively pad；First power supply pad in pad group and the first outgoing line side the distance of pad and the first outgoing line side that is less than or equal in the first signal pad group of distance, second source pad in pad group and the first outgoing line side distance more than or equal to the pad and the distance of the first outgoing line side in secondary signal pad group.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of integrated circuit, wire bond package chip and upside-down mounting
Encapsulate chip.
Background technology
Growing with electronic information technology, on the one hand integrated circuit develops towards high performance direction, the opposing party
Compact direction is face toward to develop.Currently used IC regime includes wire bond package and flip-chip packaged two
Kind.
As shown in figure 1, in wire bond package, signal pad 11 is generally designed into the interior row in bare chip 10, power supply
Ground pad 12 designs the outer row in bare chip 10.As shown in Fig. 2 in flip-chip packaged, the position of pad then just with lead key
Encapsulation is closed on the contrary, being typically the interior row that pad 22 designs in bare chip 20 by power supply, signal pad 21 is designed in bare chip 20
Outer row.
When the bare chip to a certain function is packaged, due to the packaged type that is needed in different application scene not
Together, it is thus possible to need to carry out two secondary designs, making in two-stage to the pad locations of a function identical bare chip, to meet not
Required with encapsulation, add construction cycle and manufacturing cost.
The content of the invention
The embodiments of the invention provide a kind of integrated circuit, wire bond package chip and flip-chip packaged chip, and this is integrated
Circuit can meet that the two kinds of encapsulation of wire bond package and flip-chip packaged require simultaneously.The technical scheme is as follows：
In a first aspect, the embodiments of the invention provide a kind of integrated circuit, including：
Bare chip；And
At least one pad group, at least one pad group are fixed on the active face of the bare chip, it is described at least
Each pad group in one pad group with including the first signal pad group, secondary signal pad group, the first power supply pad group and
Second source ground pad group, the first signal pad group and first power supply pad group be used for wire bond package, institute
Pad group is used for flip-chip packaged with stating secondary signal pad group and the second source；
Wherein, the first signal pad group and the secondary signal pad group include at least one signal pad respectively,
First power supply ground pad group and the second source ground pad group with including at least one power supply respectively pad；
First power supply the distance of pad in pad group and the first outgoing line side be less than or equal to first signal
The distance of pad in pad group and first outgoing line side, first outgoing line side pad group and institute for first power supply
State a side of the first signal pad group bare chip that the routing that connects is passed through in encapsulation, the second source
The pad and institute that the distance of pad and first outgoing line side in pad group is more than or equal in the secondary signal pad group
State the distance of the first outgoing line side.
In a kind of implementation of the embodiment of the present invention, the pad in each pad group is set by row, and each
Row is parallel with first outgoing line side.
In another implementation of the embodiment of the present invention, the power supply is provided only with each row pad or described
Signal pad.
In another implementation of the embodiment of the present invention, the secondary signal pad group is with being in the second source
Between pad group and the first signal pad group, the first signal pad group be in the secondary signal pad group with it is described
First power supply between pad group；Or
First power supply ground pad group with being in the first signal pad group and the second source between pad group,
Second source ground pad group with being in first power supply between pad group and the secondary signal pad group.
In another implementation of the embodiment of the present invention, the first signal pad group is with being in the second source
Between pad group and the secondary signal pad group, the secondary signal pad group be in the first signal pad group with it is described
First power supply between pad group；Or
Second source ground pad group with being in the first signal pad group and first power supply between pad group,
First power supply ground pad group with being in the second source between pad group and the secondary signal pad group.
In another implementation of the embodiment of the present invention, the first signal pad group and the secondary signal pad
Group with being in first power supply pad group and the second source between pad group, in the first signal pad group extremely
A few pad is the pad on same position with least one pad in the secondary signal pad group；Or
First power supply pad group and the second source pad group be in the first signal pad group and institute
Between stating secondary signal pad group, first power supply ground at least one pad in pad group pad with the second source
At least one pad in group is the pad on same position.
In another implementation of the embodiment of the present invention, simultaneously provided with the signal pad and described in same row
Power supply ground pad.
In another implementation of the embodiment of the present invention, simultaneously provided with the first signal pad group in a row
Pad in pad group of pad and first power supply ground, the second source pad group and first outgoing line side away from
With a distance from pad group and first outgoing line side more than first power supply；Or
With being provided with the pad in the first signal pad group and first power supply simultaneously in a row in pad group
Pad, first power supply pad group and first outgoing line side distance with being more than the second source pad group with it is described
The distance of first outgoing line side.
In another implementation of the embodiment of the present invention, first signal pad is provided with simultaneously in an at least row
Pad in the group pad in pad group with the second source；Or simultaneously provided with the described second letter in an at least row
Pad in number pad group pad in pad group with first power supply；Or simultaneously provided with described in an at least row
Pad in the first signal pad group pad in pad group, and institute is provided with simultaneously in an at least row with the second source
With stating pad and first power supply in the secondary signal pad group pad in pad group；
The second source pad group and first outgoing line side distance with being more than first power supply pad group with
The distance of first outgoing line side.
In another implementation of the embodiment of the present invention, simultaneously provided with first power supply ground pad group in a row
In pad and the signal pad；Or simultaneously provided with the pad in the first signal pad group and institute in an at least row
With the stating second source pad in pad group；Or the pad provided with first power supply in pad group simultaneously in a row
With the signal pad, and simultaneously provided with the pad in the first signal pad group and the second source in an at least row
Pad in ground pad group；
The second source pad group and first outgoing line side distance with being more than first power supply pad group with
The distance of first outgoing line side, at least one pad in the first signal pad group with the secondary signal pad group
At least one pad be the pad on same position.
In another implementation of the embodiment of the present invention, simultaneously provided with the first signal pad group in a row
Pad and power supply ground pad；Or simultaneously provided with the pad in the secondary signal pad group and institute in an at least row
With stating the first power supply pad in pad group；Or in a row simultaneously provided with the pad in the first signal pad group and
Power supply ground pad, and simultaneously provided with the pad in the secondary signal pad group and first power supply in an at least row
Pad in ground pad group；
The distance of the first signal pad group and first outgoing line side be more than the secondary signal pad group with it is described
The distance of first outgoing line side, first power supply ground at least one pad in pad group in pad group with the second source
At least one pad be the pad on same position.
On the other hand, the embodiment of the present invention additionally provides a kind of wire bond package chip, the wire bond package core
Piece includes：
Substrate, intermediate layer, foregoing integrated circuit, soldered ball and routing；
The active face of the bare chip integrates backwards to the substrate, the intermediate layer located at the side of the substrate with described
Between circuit, the soldered ball is arranged on the opposite side of the substrate, the first power supply in the integrated circuit in pad group
Pad in pad and the first signal pad group is bonded in the substrate by the routing, and passes through walking in the substrate
Line and metal flat are connected with the soldered ball.
On the other hand, the embodiment of the present invention additionally provides a kind of flip-chip packaged chip, and the flip-chip packaged chip includes：
Substrate, intermediate layer, foregoing integrated circuit, soldered ball and metal coupling；
The active face of the bare chip integrates towards the substrate, the intermediate layer located at the side of the substrate with described
Between circuit, the soldered ball is arranged on the opposite side of the substrate, and the intermediate layer is provided with through hole, and the metal coupling is located at
In the through hole, second source in the integrated circuit pad in pad and secondary signal pad group in pad group lead to
Cross the metal coupling and be connected to the substrate, and be connected by the cabling in the substrate and metal flat with the soldered ball.
The beneficial effect that technical scheme provided in an embodiment of the present invention is brought is：
It is fixed with least one pad group on the active face of bare chip, each pad group bag at least one pad group
With including the first signal pad group, secondary signal pad group, the first power supply pad group and second source ground pad group, wherein, first
Power supply pad in pad group and the first outgoing line side the pad and first that is less than or equal in the first signal pad group of distance
The distance of outgoing line side so that the first power supply pad in pad group and the first signal pad group can meet wire bonding
The requirement of encapsulation, and second source the distance of pad in pad group and the first outgoing line side be more than or equal to secondary signal pad
The distance of pad and the first outgoing line side in group so that second source pad in pad group and secondary signal pad group can be with
Meet the requirement of flip-chip packaged, therefore wire bond package, upside-down mounting envelope can be used simultaneously using the integrated circuit of above-mentioned design
Dress two ways is packaged, and is avoided the pad locations of a function identical bare chip in the prior art and is needed by twice
Design, making in two-stage, to meet the problem of different encapsulation require, reduce the construction cycle, save manufacturing cost.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of structural representation of wire bond package chip provided by the invention；
Fig. 2 is a kind of structural representation of flip-chip packaged chip provided by the invention；
Fig. 3 is a kind of structural representation of integrated circuit provided in an embodiment of the present invention；
Fig. 4 is a kind of structural representation of wire bond package chip provided in an embodiment of the present invention；
Fig. 5 is the partial enlarged drawing of the pad group in Fig. 3 provided in an embodiment of the present invention；
Fig. 6 is the structural representation of another pad group provided in an embodiment of the present invention；
Fig. 7 is the structural representation of another pad group provided in an embodiment of the present invention；
Fig. 8 is the structural representation of another pad group provided in an embodiment of the present invention；
Fig. 9 is the structural representation of another pad group provided in an embodiment of the present invention；
Figure 10 is the structural representation of another pad group provided in an embodiment of the present invention；
Figure 11 is the structural representation of another pad group provided in an embodiment of the present invention；
Figure 12 is the structural representation of another pad group provided in an embodiment of the present invention；
Figure 13 is the structural representation of another pad group provided in an embodiment of the present invention；
Figure 14 is the structural representation of another pad group provided in an embodiment of the present invention；
Figure 15 is the structural representation of another pad group provided in an embodiment of the present invention；
Figure 16 is a kind of structural representation of wire bond package chip provided in an embodiment of the present invention；
Figure 17 is a kind of structural representation of flip-chip packaged chip provided in an embodiment of the present invention.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 3 provides a kind of structural representation of integrated circuit, in microelectronic, " bare chip ", " integrated circuit ",
Frequent used interchangeablies such as " monolithic devices ", " semiconductor devices " and " microelectronic component ", the present invention be applied to it is all it is above-mentioned this
The encapsulation of a little devices, referring to Fig. 3, the integrated circuit includes：
Bare chip 100 and at least one pad group, at least one pad group are fixed on the active face of bare chip 100.Its
Middle active face refers to that bare chip has the face of active region.Wherein, bare chip is that semiconductor components and devices manufacture is completed, before encapsulation
Product form, turn into integrated circuit after encapsulation.The active face of bare chip can include one or more circuit blocks, such as brilliant
Body pipe, memory cell, passive component, etc..
Wherein, each pad group at least one pad group includes the first signal pad group, secondary signal pad group, the
One power supply ground pad group and second source ground pad group.First signal pad group and the first power supply pad group be used for wire bonding
Encapsulation, secondary signal pad group and second source pad group be used for flip-chip packaged.Wherein, the first signal pad group and the second letter
Number pad group includes at least one signal pad respectively, the first power supply pad group and second source pad group include respectively extremely
With lacking power supply pad.
It is respectively to be according to its position as shown in figure 3, being fixed with three pad groups on the active face of bare chip 100
The pad group 200 on right side, the pad group 200A in top and the pad group 200B in left side.Wherein, pad group 200 includes
First signal pad group 221, secondary signal pad group 222, the first power supply ground pad group 211 and second source ground pad group 212,
Pad group 200A with including the first signal pad group 221A, secondary signal pad group 222A, the first power supply pad group 211A and the
Two power supplys ground pad group 212A, pad group 200B include the first signal pad group 221B, secondary signal pad group 222B, the first electricity
Source ground pad group 211A and second source ground pad group 212B.In the other accompanying drawings that Fig. 3 and the embodiment of the present invention are mentioned, black
Square with representing power supply pad, white square representation signal pad, dotted line frame represent pad group (such as 200,211,221,212,
222), it is not repeated to illustrate hereinafter.
First power supply the distance of pad in pad group and the first outgoing line side be less than or equal in the first signal pad group
Pad and the first outgoing line side distance, the first outgoing line side be the first power supply pad group and the first signal pad group in encapsulation
One side of the bare chip that the routing of connection is passed through, the first outgoing line side and the first power supply ground pad group and the first signal pad
Group is corresponding, second source pad in pad group and the first outgoing line side distance more than or equal in secondary signal pad group
The distance of pad and the first outgoing line side.
As shown in figure 3, in pad group 200, the first power supply pad in pad group 211 and the first outgoing line side 110 away from
With a distance from less than the pad in the first signal pad group 221 and the first outgoing line side 110, second source in pad group 212
The distance of pad and the first outgoing line side 110 is more than the distance of the pad and the first outgoing line side 110 in secondary signal pad group 222；
In pad group 200A, the first power supply pad in pad group 211A and the first outgoing line side 110A distance welded equal to the first signal
The distance of pad and the first outgoing line side 110A in disk group 221A, second source ground pad in pad group 212A and the first outlet
Side 110A distance is more than the distance of the pad and the first outgoing line side 110A in secondary signal pad group 222A；Pad group 200B
In, the first power supply pad in pad group 211B and the first outgoing line side 110B distance be less than in the first signal pad group 221B
Pad and the first outgoing line side 110B distance, second source pad in pad group 212B and the first outgoing line side 110B away from
With a distance from equal to the pad and the first outgoing line side 110B in secondary signal pad group 222B.
Fig. 4 provides a kind of structural representation of the chip using wire bond package, is wherein the shown in label 110
One outgoing line side.
In order to meet electrical code, meet the requirement of flip-chip packaged, be readily apparent that, second source any two in pad group
Individual power supply pad spacing in the setting range of electrical equipment specification, in secondary signal pad group between any two signal pad
Away from the setting range of electrical equipment specification.
Wherein, two power supplys pad either two signal pads spacing with referring to two power supplys pad or two letters
Distance between number pad center.Above-mentioned setting range can be more than or equal in copper pillar (copper coin post soldered ball) rules
Copper pillar diameters, such as can be 80-200 μm, certainly above-mentioned setting range needs basis to be actually needed determination, on
State content only as an example, the present invention is without limitation.
As shown in figure 3, bare chip 100 is generally rectangular in shape, every side of rectangle can set a pad group,
The module that each pad group is supplied in bare chip carries out the input and output of signal, such as DDR (English " Double Data
Rate ", Chinese " Double Data Rate synchronous DRAM ") 4 modules etc..The shape and pad group of bare chip 100 shown in Fig. 3
Quantity only as an example, the embodiment of the present invention is not limited the shape of bare chip 100 and the quantity of the pad group set thereon
System.
Be readily apparent that, in the integrated circuit shown in Fig. 3 in pad group the quantity of pad only as an example, the quantity of pad
It can be configured according to being actually needed.
As shown in figure 4, using wire bond package formed chip in, the first power supply pad group 211 and first believe
Pad in number pad group 221 is bonded in substrate 400 by routing 300, and passes through the cabling 401 and gold inside substrate 400
Category plane 402 (being illustrated as its section) is connected with soldered ball 500.In order to ensure power supply inductance minimum, to cause from the first power supply
The power source path of pad to soldered ball 500 in pad group 211 is minimum, so in wire bond package, can by the first power supply
Pad group 211 designs arranges outside, i.e., compared to the first signal pad group 221 close to the first outgoing line side 110, then with bare chip
The soldered ball 500 of 100 lower sections connects.And in order to meet the requirement of routing rule, avoid routing from intersecting, by the first signal pad group
221 are arranged on interior row, ensure that the pad in the first signal pad group 221 smoothly can be bonded to substrate 400 by routing 300
On.Wherein, in order that the signal that routing 300 transmits preferably is transferred in soldered ball 500, the interior cabling 401 of substrate 400 can be increased
Width, be allowed to form a face, i.e. metal flat 402 (such as copper sheet face).
In addition, in the integrated circuit that Fig. 3 is provided, second source in each pad group ground pad group and first outgoing line side
The distance of secondary signal pad group and first outgoing line side that is more than or equal in pad group of distance, i.e., weld by second source
Disk group design inside arrange so that using flip-chip packaged power supply between pad and soldered ball transmission path it is most short, ensure power quality
Optimal, wherein the chip structure of flip-chip packaged form can be referring specifically to the description for Figure 17 hereinafter.
In the embodiment of the present invention, at least one pad group, at least one pad group are fixed with the active face of bare chip
In each pad group with including the first signal pad group, secondary signal pad group, the first power supply pad group and second source
Pad group, wherein, the first power supply the distance of pad in pad group and the first outgoing line side be less than or equal to the first signal pad
The distance of pad and the first outgoing line side in group, so that pad of the first power supply ground in pad group and the first signal pad group
Can meet the requirement of wire bond package, and second source pad in pad group and the first outgoing line side distance be more than or
Equal to the pad and the distance of the first outgoing line side in secondary signal pad group so that second source pad group and secondary signal weldering
Pad in disk group can meet the requirement of flip-chip packaged, therefore can use lead simultaneously using the integrated circuit of above-mentioned design
Bonding packaging, flip-chip packaged two ways are packaged, and avoid the pad of a function identical bare chip in the prior art
Position is needed by two secondary designs, making in two-stage, to meet the problem of different encapsulation require, is reduced the construction cycle, is saved
Manufacturing cost.
In embodiments of the present invention, the pad in each pad group can by row set, and each row with the pad group
Corresponding first outgoing line side is parallel, is easy to the design of pad and circuit；In other embodiments, power supply ground pad and signal pad
Other arrangement modes can also be used, it is of the invention without limitation.
Below in the embodiment of the present invention, exemplified by being in the pad group 200 on right side in integrated circuit in Fig. 3, to pad
The setting of pad in group illustrates：
In a kind of implementation of the embodiment of the present invention, with being provided only with power supply pad or signal pad in each row,
Including but not limited to following several specific implementations：
Fig. 5 is the enlarged drawing for the pad group 200 that right side is in the integrated circuit shown in Fig. 3, in the pad group 200,
Secondary signal pad group 222 is with being in second source between the signal pad group 221 of pad group 212 and first, the first signal pad
Group 221 between pad group 211 in secondary signal pad group 222 and the first power supply.
In the integrated circuit shown in Fig. 5, second source pad group 212 account for 2 rows, secondary signal pad group 222 accounts for 2
Row, the first signal pad group 221 account for 1 row, and the first signal pad group 221 accounts for 1 row.Certainly, the row shared by each pad here
And the row in the accompanying drawing that is related to hereinafter of embodiment shared by each pad is only for example, the embodiment of the present invention is without limitation.
Fig. 6 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, the first electricity
Source ground pad group 211 with being in the first signal pad group 221 and second source between pad group 212, second source ground pad group
212 in the first power supply between pad group 211 and secondary signal pad group 222.
In the pad group 200 that Fig. 5 and Fig. 6 are provided, the first power supply pad group 211, second source pad group 212,
Set independently of each other between first signal pad group 221 and secondary signal pad group 222, and for wire bond package pad with
For being independently arranged between the pad of flip-chip packaged.Such as in Figure 5, the first power supply pad group 211 and second source weld
The respective shared region of disk group 212 separates by a dotted line, does not interfere with each other.
Fig. 7 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, the first letter
Number pad group 221 is with being in second source between pad group 212 and secondary signal pad group 222, at secondary signal pad group 222
Between pad group 211 in the first signal pad group 221 and the first power supply.
Fig. 8 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, the second electricity
Source ground pad group 212 with being in the first signal pad group 221 and the first power supply between pad group 211, the first power supply ground pad group
211 in second source between pad group 212 and secondary signal pad group 222.
In the pad group 200 that Fig. 7 and Fig. 8 are provided, the first power supply pad group 211, second source pad group 212,
Set independently of each other between first signal pad group 221 and secondary signal pad group 222, pad and use for wire bond package
It is arranged at intervals in the pad of flip-chip packaged.
Fig. 9 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, the first letter
Number pad group 221 and secondary signal pad group 222 with being in the first power supply pad group 211 with second source pad group 212 it
Between, at least one pad in the first signal pad group 221 shares with least one pad in secondary signal pad group 222,
That is at least one pad in the first signal pad group 221 is same with least one pad in secondary signal pad group 222
Pad on individual position.For example, in fig.9, in a row signal pad of the first outgoing line side 110, the signal weldering of the top
Disk can both belong to the first signal pad group 221, belong to secondary signal pad group 222 again；I.e. when using wire bond package,
The signal pad is used, and when using flip-chip packaged, the signal pad is also used.
First signal pad group 221 is welded with secondary signal in pad group 200 in the integrated circuit provided due to Fig. 5 and Fig. 7
Disk group 222 is located proximate to, and the first signal pad group 221 will not use simultaneously with the pad in secondary signal pad group 222, therefore
On the basis of the pad group 200 that Fig. 7 is provided can to the first signal pad group 221 with secondary signal pad group 222 extremely
A few pad is shared, so as to obtain the integrated circuit of Fig. 9 offers, to reduce IC design complexity, simultaneously
Reduce material consumption and process time.
Figure 10 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, first
Power supply pad group 211 and second source pad group 212 be in the first signal pad group 221 and secondary signal pad group 222
Between, the first power supply ground at least one pad in pad group 211 at least one pad in pad group 212 with second source
Share, i.e. at least one pad in the pad group 211 at least one weldering in pad group 212 of the first power supply ground with second source
Disk is the pad on same position.
First power supply ground pad group 211 and second source in pad group 200 in the integrated circuit provided due to Fig. 6 and Fig. 8
Ground pad group 212 is located proximate to, and the first power supply pad of the pad group 211 in pad group 212 with second source will not be same
When use, therefore Fig. 8 provide pad group 200 on the basis of pad group 211 can weld to the first power supply with second source
At least one pad in disk group 212 is shared, and so as to obtain the integrated circuit of Figure 10 offers, is set to reduce integrated circuit
Complexity is counted, while reduces material consumption and process time.
In Fig. 9 and the pad group 200 provided with Figure 10, the shared mode of pad can include：
In one implementation, the pad in all first signal pad groups 221 is common with secondary signal pad group 222
With.For example, the pad for the distance requirement that all signal pads are designed to meet flip-chip packaged, the first signal pad group 221
In pad therefrom choose.
In another implementation, pad in all secondary signal pad groups 222 with the first signal pad group 221
Share.For example, do not consider the distance requirement of flip-chip packaged in modelled signal pad, and after the completion of design, letter is chosen at interval
Number pad is as the pad in secondary signal pad group 222.
Above two signal pad, which shares implementation, can improve the shared efficiency of signal pad, but above two is realized
Mode only as an example, is not intended as the limitation of the present invention.
Further, in embodiments of the present invention, in addition to it can carry out the pad in same pad group 200 to share,
Pad it can also be shared by the signal pad in two pad groups or power supply.As shown in figure 3, can be by the pad of top
The second source of the pad group 200 on group 200A and right side pad group 212 be designed into the center of bare chip 100 and be total to
With.
In another implementation of the embodiment of the present invention, pad and the signal weldering simultaneously in same row provided with power supply
Disk, including but not limited to following several specific implementations：
Figure 11 provides the structural representation of pad group 200 in another integrated circuit, shown in the pad group 200 and Fig. 3
Integrated circuit in the pad group 200A in top structure it is similar, in the pad group 200, simultaneously provided with the in a row
Pad of pad and the first power supply in one signal pad group 221 ground in pad group 211, second source pad group 212 with should
The distance of first outgoing line side 110 corresponding to pad group 200 with being more than the first power supply pad group 211 and first outgoing line side 110
Distance, the same row's setting of pad can save the position on bare chip surface, be advantageous to reduce bare chip by signal pad and power supply
Area.
The structural representation provided according to Figure 11, is readily apparent that, can also be provided with secondary signal pad simultaneously in a row
With organizing pad and the second source in 222 pad in pad group 212；Or it is provided with the first signal pad simultaneously in a row
With organizing pad and the first power supply in 221 pad in pad group 211, and it is provided with secondary signal pad group simultaneously in a row
Pad of pad and second source in 222 ground in pad group 212.But due to the pad in secondary signal pad group 222 and
Two power supplys pad in pad group 212 all need to meet the distance requirement of flip-chip packaged, therefore by secondary signal pad group 222
In pad and second source pad in pad group 212 position that can not save bare chip surface is set with row.
Figure 12 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, one
With being provided with the pad in the first signal pad group 221 and the first power supply in the row simultaneously pad in pad group 211, second source
The distance of first outgoing line side 110 corresponding with the pad group 200 of pad group 212 with being less than the first power supply pad group 211 with this
The distance of one outgoing line side 110, the same row's setting of pad can save the position on bare chip surface by signal pad and power supply, favorably
In reduction bare chip area.
The structural representation provided according to Figure 12, is readily apparent that, can also be provided with secondary signal pad simultaneously in a row
With organizing pad and the second source in 222 pad in pad group 212；Or it is provided with the first signal pad simultaneously in a row
With organizing pad and the first power supply in 221 pad in pad group 211, and it is provided with secondary signal pad group simultaneously in a row
Pad of pad and second source in 222 ground in pad group 212.But due to the pad in secondary signal pad group 222 and
Two power supplys pad in pad group 212 all need to meet the distance requirement of flip-chip packaged, therefore by secondary signal pad group 222
In pad and second source pad in pad group 212 position that can not save bare chip surface is set with row.
The pad group 200 that Figure 11 and Figure 12 is provided, it is the first signal weldering in the pad group that Fig. 5 and Fig. 6 are provided respectively
Pad and the first power supply in disk group 221 pad design in pad group 211 obtained in same row.
Be readily apparent that, in a row simultaneously setting signal pad and power supply pad implementation, especially suitable for weldering
The scene of disk negligible amounts.
Figure 13 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, extremely
Simultaneously provided with the pad in the pad in the first signal pad group 221 pad group 212 in a few row, and extremely with second source
With being provided with the pad in secondary signal pad group 222 and the first power supply in a few row simultaneously pad in pad group 211.
The structural representation provided according to Figure 13, is readily apparent that, can also be only in side pad and signal weldering by power supply
Disk is with arranging settings, such as the pad simultaneously in an at least row provided with the pad in the first signal pad group 221 and second source
Pad in group 212；Or in an at least row power supply provided with the pad in secondary signal pad group 222 and first simultaneously
Pad in pad group 211.
Pad sets the position that can save bare chip surface with row by signal pad and power supply, is advantageous to reduce naked core
Piece area.
Preferably, weldering of the pad in the first signal pad group 221 in same row and the second source ground in pad group 212
Disk is arranged at intervals, the pad in secondary signal pad group 222 and the first power supply in same row between pad in pad group 211
Every setting, the pad and second source that are arranged at intervals in the secondary signal pad group 222 that can cause to design ground pad group 212
In pad meet the required distance of flip-chip packaged, convenient design.
In addition, in the pad group 200, second source ground first outgoing line side corresponding with the pad group 200 of pad group 212
The distance of 110 distance with being more than the first power supply pad group 211 and first outgoing line side 110.
Figure 13 is obtained according to the malformation of pad group 200 in Fig. 7 and Fig. 8.
Figure 14 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, one
With being provided with the first power supply in the row simultaneously pad and signal pad in pad group 211, the signal pad can be the weldering of the first signal
The pad in pad or secondary signal pad group 222 in disk group 221, can also be the shared pad of the two.Second
Power supply the distance of first outgoing line side 110 corresponding with the pad group 200 of pad group 212 be more than the first power supply ground pad group 211
With the distance of first outgoing line side 110, at least one pad and secondary signal pad group 222 in the first signal pad group 221
In at least one pad be the pad on same position.What deserves to be explained is the pad in the integrated circuit that Figure 14 is provided
In group 200, during using flip-chip packaged, it can use simultaneously with row's setting unit and the non-signal pad with row's setting unit, and
When using wire bond package, it can only use with row's setting unit or the non-signal pad with row's setting unit.
The structural representation provided according to Figure 14, is readily apparent that, can also be provided with the first signal simultaneously in an at least row
Pad of pad and second source in pad group 221 ground in pad group 212；Or it is provided with the first power supply simultaneously in a row
Pad and signal pad in ground pad group 211, and simultaneously provided with the pad in the first signal pad group 221 in an at least row
Pad in pad group 212 with second source.
Pad sets the position that can save bare chip surface with row by signal pad and power supply, is advantageous to reduce naked core
Piece area.
Furthermore it is also possible to the pad simultaneously in a row provided with the pad in secondary signal pad group 222 and second source
Pad in group 212, or, the pad and signal pad provided with the first power supply in pad group 211 simultaneously in a row, and
With being provided with the pad in secondary signal pad group 222 and second source in the one row simultaneously pad in pad group 212.But due to
Pad and second source in binary signal pad group 222 pad in pad group 212 all need to meet the distance of flip-chip packaged
Demand, therefore the pad in pad group 212 is set not with row by the pad in secondary signal pad group 222 and second source
The position on bare chip surface can be saved.
Figure 15 provides the structural representation of pad group 200 in another integrated circuit, in the pad group 200, one
Simultaneously provided with the first signal pad group 221 and power supply ground pad in row, the power supply pad can be the first power supply ground pad group
Pad of pad or second source in 211 ground in pad group 212, can also be the shared pad of the two.First letter
The distance of number first outgoing line side 110 corresponding with the pad group 200 of pad group 221 be more than secondary signal pad group 222 with this
The distance of one outgoing line side 110, the first power supply ground at least one pad in pad group 211 in pad group 212 with second source
At least one pad be the pad on same position.What deserves to be explained is the pad group in the integrated circuit that Figure 15 is provided
In 200, during using flip-chip packaged, pad can be used simultaneously with row's setting unit and the non-power supply with row's setting unit, and
When using wire bond package, pad can only be used with row's setting unit or the non-power supply with row's setting unit.
The structural representation provided according to Figure 15, is readily apparent that, can also be provided with secondary signal simultaneously in an at least row
Pad of pad and the first power supply in pad group 222 ground in pad group 211；Or it is provided with the first signal simultaneously in a row
Pad and power supply in pad group 221 ground pad, and simultaneously provided with the pad in secondary signal pad group 222 in an at least row
Pad in pad group 211 with the first power supply.
Pad sets the position that can save bare chip surface with row by signal pad and power supply, is advantageous to reduce naked core
Piece area.
Furthermore it is also possible to the pad simultaneously in a row provided with the pad in secondary signal pad group 222 and second source
Pad in group 212；Or the pad simultaneously in a row, and provided with the pad in the first signal pad group 221 and power supply
With being provided with the pad in secondary signal pad group 222 and second source in the one row simultaneously pad in pad group 212.But due to
Pad and second source in binary signal pad group 222 pad in pad group 212 all need to meet the distance of flip-chip packaged
Demand, therefore the pad in pad group 212 is set not with row by the pad in secondary signal pad group 222 and second source
The position on bare chip surface can be saved.
Figure 14 and Figure 15 is obtained according to the malformation of pad group 200 in Fig. 9 and Figure 10 respectively.
It is readily apparent that, the structure for the pad group 200 that earlier figures 5- Figure 15 is provided is only for example, and can not be used as to the present invention
Limitation.
Figure 16 provides a kind of structural representation of wire bond package chip, referring to Figure 16, wire bond package chip
Including：
Substrate 601, intermediate layer 602, the integrated circuit 603 as corresponding to any width in Fig. 3~15, soldered ball 604 and routing
605；
The active face 100a of bare chip 100 is backwards to substrate 601 in integrated circuit 603, and intermediate layer 602 is located at substrate 601
Between side and integrated circuit 603, soldered ball 604 is arranged on the opposite side of substrate 601, is welded in integrated circuit 603 first power supply
Pad in the signal pad group 221 of disk group 211 and first is bonded in substrate 601 by routing 605, and by substrate 601
Cabling 606 and metal flat 607 (such as copper sheet face) be connected with soldered ball 604.
In the embodiment of the present invention, at least one pad group, at least one pad group are fixed with the active face of bare chip
In each pad group with including the first signal pad group, secondary signal pad group, the first power supply pad group and second source
Pad group, wherein, the first power supply the distance of pad in pad group and the first outgoing line side be less than or equal to the first signal pad
The distance of pad and the first outgoing line side in group, so that pad of the first power supply ground in pad group and the first signal pad group
Can meet the requirement of wire bond package, and second source pad in pad group and the first outgoing line side distance be more than or
Equal to the pad and the distance of the first outgoing line side in secondary signal pad group so that second source pad group and secondary signal weldering
Pad in disk group can meet the requirement of flip-chip packaged, therefore can use lead simultaneously using the integrated circuit of above-mentioned design
Bonding packaging, flip-chip packaged two ways are packaged, and avoid the pad of a function identical bare chip in the prior art
Position is needed by two secondary designs, making in two-stage, to meet the problem of different encapsulation require, is reduced the construction cycle, is saved
Manufacturing cost.
Figure 17 provides a kind of structural representation of flip-chip packaged chip, and referring to Figure 17, flip-chip packaged chip includes：
Substrate 701, intermediate layer 702, the integrated circuit 703 as corresponding to any width in Fig. 3~15, soldered ball 704 and metal are convex
Block 705 (such as copper pillar)；
The active face 100a of bare chip 100 is towards substrate 701 in integrated circuit 703, and intermediate layer 702 is located at substrate 701
Between side and integrated circuit 703, soldered ball 704 is arranged on the opposite side of substrate 701, and intermediate layer 702 is provided with through hole, and metal is convex
Block 705 in the through hole, in integrated circuit 703 second source the pad of pad group 212 and secondary signal pad group 222 pass through
Metal coupling 705 is connected to substrate 701, and is connected by the cabling 706 in substrate 701 and metal flat 707 with soldered ball 704.
In the embodiment of the present invention, at least one pad group, at least one pad group are fixed with the active face of bare chip
In each pad group with including the first signal pad group, secondary signal pad group, the first power supply pad group and second source
Pad group, wherein, the first power supply the distance of pad in pad group and the first outgoing line side be less than or equal to the first signal pad
The distance of pad and the first outgoing line side in group, so that pad of the first power supply ground in pad group and the first signal pad group
Can meet the requirement of wire bond package, and second source pad in pad group and the first outgoing line side distance be more than or
Equal to the pad and the distance of the first outgoing line side in secondary signal pad group so that second source pad group and secondary signal weldering
Pad in disk group can meet the requirement of flip-chip packaged, therefore can use lead simultaneously using the integrated circuit of above-mentioned design
Bonding packaging, flip-chip packaged two ways are packaged, and avoid the pad of a function identical bare chip in the prior art
Position is needed by two secondary designs, making in two-stage, to meet the problem of different encapsulation require, is reduced the construction cycle, is saved
Manufacturing cost.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (13)
- A kind of 1. integrated circuit, it is characterised in that including：Bare chip；AndAt least one pad group, at least one pad group is fixed on the active face of the bare chip, described at least one Each pad group in pad group with including the first signal pad group, secondary signal pad group, the first power supply pad group and second Power supply ground pad group, the first signal pad group and first power supply pad group be used for wire bond package, described Binary signal pad group and the second source pad group be used for flip-chip packaged；Wherein, the first signal pad group and the secondary signal pad group include at least one signal pad respectively, described First power supply ground pad group and the second source ground pad group with including at least one power supply respectively pad；First power supply the distance of pad in pad group and the first outgoing line side be less than or equal to first signal pad The distance of pad in group and first outgoing line side, first outgoing line side are first power supply ground pad group and described the One side of one signal pad group bare chip that the routing that connects is passed through in encapsulation, second source ground pad The pad that the distance of pad in group and first outgoing line side is more than or equal in the secondary signal pad group and described the The distance of one outgoing line side.
- 2. integrated circuit according to claim 1, it is characterised in that the pad in each pad group is set by row, and Each row is parallel with first outgoing line side.
- 3. integrated circuit according to claim 2, it is characterised in that the power supply is provided only with each row pad or institute State signal pad.
- 4. integrated circuit according to claim 3, it is characterised in that the secondary signal pad group is in the second source Between ground pad group and the first signal pad group, the first signal pad group is in the secondary signal pad group and institute With stating the first power supply between pad group；OrFirst power supply ground pad group with being in the first signal pad group and the second source between pad group, it is described Second source ground pad group with being in first power supply between pad group and the secondary signal pad group.
- 5. integrated circuit according to claim 3, it is characterised in that the first signal pad group is in the second source Between ground pad group and the secondary signal pad group, the secondary signal pad group is in the first signal pad group and institute With stating the first power supply between pad group；OrSecond source ground pad group with being in the first signal pad group and first power supply between pad group, it is described First power supply ground pad group with being in the second source between pad group and the secondary signal pad group.
- 6. integrated circuit according to claim 3, it is characterised in that the first signal pad group and secondary signal weldering Disk group with being in first power supply pad group and the second source between pad group, in the first signal pad group At least one pad is the pad on same position with least one pad in the secondary signal pad group；OrFirst power supply pad group and the second source pad group be in the first signal pad group and described the Between binary signal pad group, first power supply ground at least one pad in pad group in pad group with the second source At least one pad be the pad on same position.
- 7. integrated circuit according to claim 2, it is characterised in that be provided with the signal pad and institute simultaneously in same row With stating power supply pad.
- 8. integrated circuit according to claim 7, it is characterised in that be provided with the first signal pad group simultaneously in a row In pad in pad group of pad and first power supply ground, the second source ground pad group and first outgoing line side Apart from being more than first power supply pad group and the distance of first outgoing line side；OrWith being provided with the pad in the first signal pad group and first power supply simultaneously in the row pad in pad group, First power supply pad group and first outgoing line side distance with being more than second source pad group and described first The distance of outgoing line side.
- 9. integrated circuit according to claim 7, it is characterised in that welded simultaneously provided with first signal in an at least row Pad in the disk group pad in pad group with the second source；Or simultaneously provided with described second in an at least row Pad in the signal pad group pad in pad group with first power supply；Or it is provided with institute simultaneously in an at least row With stating pad and the second source in the first signal pad group pad in pad group, and be provided with simultaneously in an at least row Pad in the secondary signal pad group pad in pad group with first power supply；The second source pad group and first outgoing line side distance with being more than first power supply pad group with it is described The distance of first outgoing line side.
- 10. integrated circuit according to claim 7, it is characterised in that welded simultaneously provided with first power supply in a row Pad and the signal pad in disk group；Or simultaneously provided with the pad in the first signal pad group in an at least row Pad in pad group with the second source；Or simultaneously provided with first power supply in pad group in a row Pad and the signal pad, and simultaneously provided with the pad and described second in the first signal pad group in an at least row Pad of the power supply ground in pad group；The second source pad group and first outgoing line side distance with being more than first power supply pad group with it is described The distance of first outgoing line side, at least one pad in the first signal pad group with the secondary signal pad group extremely A few pad is the pad on same position.
- 11. integrated circuit according to claim 7, it is characterised in that be provided with first signal pad simultaneously in a row Pad and the power supply in group ground pad；Or simultaneously provided with the pad in the secondary signal pad group in an at least row Pad in pad group with first power supply；Or simultaneously provided with the weldering in the first signal pad group in a row Disk and the power supply ground pad, and simultaneously provided with the pad and described first in the secondary signal pad group in an at least row Pad of the power supply ground in pad group；The first signal pad group and the distance of first outgoing line side are more than the secondary signal pad group and described first The distance of outgoing line side, first power supply at least one pad in pad group with the second source in pad group extremely A few pad is the pad on same position.
- 12. a kind of wire bond package chip, it is characterised in that the wire bond package chip includes：Substrate, intermediate layer, integrated circuit, soldered ball and routing as described in claim any one of 1-11；The active face of the bare chip is backwards to the substrate, and the intermediate layer is located at the side of the substrate and the integrated circuit Between, the soldered ball is arranged on the opposite side of the substrate, pad of the ground of the first power supply in the integrated circuit in pad group Be bonded to the pad in the first signal pad group by the routing in the substrate, and by the cabling in the substrate and Metal flat is connected with the soldered ball.
- 13. a kind of flip-chip packaged chip, it is characterised in that the flip-chip packaged chip includes：Substrate, intermediate layer, integrated circuit, soldered ball and metal coupling as described in claim any one of 1-11；The active face of the bare chip is towards the substrate, and the intermediate layer is located at the side of the substrate and the integrated circuit Between, the soldered ball is arranged on the opposite side of the substrate, and the intermediate layer is provided with through hole, and the metal coupling is located at described In through hole, second source in the integrated circuit pad in pad and secondary signal pad group in pad group pass through institute State metal coupling and be connected to the substrate, and be connected by the cabling in the substrate and metal flat with the soldered ball.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510185457.9A CN104851863B (en) | 2015-04-17 | 2015-04-17 | A kind of integrated circuit, wire bond package chip and flip-chip packaged chip |
| PCT/CN2016/079053 WO2016165607A1 (en) | 2015-04-17 | 2016-04-12 | Integrated circuit, wire-bonding package chip and flip-chip package chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510185457.9A CN104851863B (en) | 2015-04-17 | 2015-04-17 | A kind of integrated circuit, wire bond package chip and flip-chip packaged chip |
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| CN104851863B true CN104851863B (en) | 2017-11-28 |
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| CN104851863B (en) * | 2015-04-17 | 2017-11-28 | 华为技术有限公司 | A kind of integrated circuit, wire bond package chip and flip-chip packaged chip |
| CN109003949A (en) * | 2018-08-01 | 2018-12-14 | 灿芯半导体(上海)有限公司 | A kind of interface that bonding line encapsulation is shared with flip-chip packaged |
| CN112736053A (en) * | 2019-10-14 | 2021-04-30 | 瑞昱半导体股份有限公司 | Chip packaging module |
| EP4084069A4 (en) * | 2020-01-23 | 2023-05-17 | Huawei Technologies Co., Ltd. | Chip device and wireless communication device |
| CN111739807B (en) * | 2020-08-06 | 2020-11-24 | 上海肇观电子科技有限公司 | Wiring design method, wiring structure and flip chip |
| CN113838815A (en) * | 2021-09-23 | 2021-12-24 | 西安紫光国芯半导体有限公司 | Substrate and chip assembly |
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| US6870273B2 (en) * | 2002-04-29 | 2005-03-22 | Pmc-Sierra, Inc. | High speed I/O pad and pad/cell interconnection for flip chips |
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| CN103366798B (en) * | 2013-07-10 | 2016-02-17 | 格科微电子（上海）有限公司 | Dynamic RAM and manufacture method, semiconductor package part and method for packing |
| CN104851863B (en) * | 2015-04-17 | 2017-11-28 | 华为技术有限公司 | A kind of integrated circuit, wire bond package chip and flip-chip packaged chip |
-
2015
- 2015-04-17 CN CN201510185457.9A patent/CN104851863B/en active Active
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2016
- 2016-04-12 WO PCT/CN2016/079053 patent/WO2016165607A1/en active Application Filing
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| US5952726A (en) * | 1996-11-12 | 1999-09-14 | Lsi Logic Corporation | Flip chip bump distribution on die |
| CN101261973A (en) * | 2007-03-06 | 2008-09-10 | 株式会社瑞萨科技 | Semiconductor device |
| CN103779338A (en) * | 2012-10-24 | 2014-05-07 | 瑞萨电子株式会社 | Electronic device and semiconductor device |
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| Publication number | Publication date |
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| CN104851863A (en) | 2015-08-19 |
| WO2016165607A1 (en) | 2016-10-20 |
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