CN209880601U - QFN frame-based packaging structure - Google Patents
QFN frame-based packaging structure Download PDFInfo
- Publication number
- CN209880601U CN209880601U CN201920911085.7U CN201920911085U CN209880601U CN 209880601 U CN209880601 U CN 209880601U CN 201920911085 U CN201920911085 U CN 201920911085U CN 209880601 U CN209880601 U CN 209880601U
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- CN
- China
- Prior art keywords
- chip
- frame
- pin bonding
- lead
- bonding pad
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model relates to a QFN frame-based packaging structure, which comprises a first frame and a second frame; the first frame comprises a plurality of first pin bonding pads which are arranged; the second frame comprises a plurality of second pin bonding pads which are arranged; the second pin bonding pad and the first pin bonding pad are arranged correspondingly and are bonded and conducted together through conductive adhesive; the size of the first pin bonding pad is larger than that of the second pin bonding pad, and part of the first pin bonding pad is exposed; the chip packaging structure further comprises a chip and a packaging layer for packaging the chip, the first frame and the second frame together. The utility model discloses an encapsulation structure switches on together through two-layer frame bonding, can rationally select suitable pin pad according to the wiring demand of chip.
Description
Technical Field
The utility model relates to an encapsulation structure of chip, more specifically, the utility model relates to an encapsulation structure based on QFN frame.
Background
QFN (Quad Flat No-lead Package), one of the surface mount packages, is known. QFN is a leadless package, square or rectangular, with a large area of exposed pads at the center of the bottom of the package for heat conduction, and conductive pads surrounding the large pads around the periphery of the package for electrical connection. QFN packages provide excellent electrical performance because they do not have gull-wing leads as do conventional SOIC and TSOP packages, the electrical path between the inner leads and the pads is short, the self-inductance, and the wiring resistance within the package is low.
In the existing QFN frame, the pin bonding pads are all positioned on the same side layer, and the requirement of cross wiring cannot be met. When a structural design in which two chips are stacked together is adopted, leads of the two chips are easily crossed and conducted together, and short circuit or open circuit is caused.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an encapsulation construction based on QFN frame.
According to an aspect of the present invention, there is provided a QFN frame-based package structure, comprising a first frame and a second frame; the first frame comprises a plurality of first pin bonding pads which are arranged; the second frame comprises a plurality of second pin bonding pads which are arranged; the second pin bonding pad and the first pin bonding pad are arranged correspondingly and are bonded and conducted together through conductive adhesive; the size of the first pin bonding pad is larger than that of the second pin bonding pad, and part of the first pin bonding pad is exposed;
the chip packaging structure further comprises a chip and a packaging layer for packaging the chip, the first frame and the second frame together.
Optionally, the outer end face of the first pin pad is exposed from the packaging layer; and/or the outer end face of the second pin pad is exposed from the packaging layer.
Optionally, the first frame includes a first connection portion that conducts the two first lead pads together; alternatively, the second frame includes a second connection portion that conducts the two second lead pads together.
Optionally, the first frame includes a first connection portion that conducts the two first lead pads together; the second frame includes a second connection portion that conducts the two second lead pads together; and the two first pin bonding pads conducted by the first connecting parts and the two second pin bonding pads conducted by the second connecting parts are staggered with each other.
Optionally, the chip is flip-chip mounted at a position where the first lead pad is exposed, and is electrically connected to the first lead pad.
Optionally, the first frame further comprises a base island; the chip is attached to the base island and connected with the exposed position of the first pin bonding pad through a lead or/and connected with the second pin bonding pad through a lead.
Optionally, the first frame further comprises a base island; the two chips are respectively marked as a first chip attached to the base island and a second chip attached to the first chip; the first chip is connected with the exposed position of the first pin bonding pad through a lead; the second chip is connected with the second pin bonding pad through a lead.
Optionally, the second pin pad of the second chip is connected by a wire, corresponding to the first pin pad of the first chip by a wire.
Optionally, the second pin pad connected to the second chip by a wire is staggered from the first pin pad connected to the first chip by a wire.
The utility model discloses an encapsulation structure switches on together through two-layer frame bonding, can rationally select suitable pin pad according to the wiring demand of chip.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic structural diagram of the frame of the present invention.
Fig. 2 is a top view of the first frame of fig. 1.
Fig. 3 is a top view of the second frame of fig. 1.
Fig. 4 is a schematic structural diagram of a first embodiment of the package structure of the present invention.
Fig. 5 is a schematic structural diagram of a second embodiment of the package structure of the present invention.
Fig. 6 is a schematic structural diagram of a third embodiment of the package structure of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless specifically stated otherwise, the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be considered a part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The utility model provides a packaging structure based on QFN frame, including frame, chip to and with chip and frame encapsulation layer 4 together.
The frame comprises a first frame 1 and a second frame 2 which are bonded together. Referring to fig. 1, 2 and 3, the first frame 1 may be a conventional QFN frame structure including a base island 12 located at a central region and a plurality of first lead pads 10 disposed around the base island 12. The base island 12 may be circular or rectangular, and in a specific embodiment of the present invention, the base island 12 is square. The first lead pads 10 are provided in four groups, respectively distributed at four sidewall positions of the base island 12, and have gaps with the base island 12. A plurality of first pin pads 10 are provided per set.
The second frame 2 includes a plurality of second lead pads 20 arranged, and the number and distribution positions of the second lead pads 20 may correspond to those of the first lead pads 10. For example, referring to fig. 3, the second lead pads 20 are provided in four sets distributed at four side wall positions of a rectangle.
The first frame 1 and the second frame 2 are bonded together, specifically, the corresponding first lead bonding pad 10 and the corresponding second lead bonding pad 20 are bonded together by conductive adhesive to realize the connection of the two frames, and the first lead bonding pad 10 is conducted with the corresponding second lead bonding pad 20, so that the electrical signal on the first lead bonding pad 10 can be led to the corresponding second lead bonding pad 20, or the electrical signal on the second lead bonding pad 20 is led to the corresponding first lead bonding pad 10, which is not described in detail herein.
Referring to fig. 1, the size of the first lead pad 10 is larger than that of the second lead pad 20, so that after the second lead pad 20 is bonded to the first lead pad 10, the second lead pad 20 does not cover the first lead pad 20 completely, and a part of the first lead pad 20 is exposed, so as to connect a lead or a chip.
The two frames are bonded together, and the pin bonding pads of the two frames are correspondingly conducted, so that two sides of the packaging structure can be used as external output pins.
For example, referring to fig. 4 and 5, after the chip is packaged by the package layer 4 with the first frame and the second frame, the bottom surface of the package may be ground flat to expose the outer end surface of the first lead pad 10 located at the bottom, so that the first lead pad 10 may serve as an output lead of the package.
Alternatively, the top surface of the package may be ground flat to expose the outer end surface of the second lead pad 20 located at the top, so that the second lead pad 20 may serve as an output lead of the package.
Alternatively, the top and bottom surfaces of the package may be ground flat to expose the outer end surface of the first lead pad 10 at the bottom and the outer end surface of the second lead pad 20 at the top. This allows both the first and second lead pads 10 and 20 of the package to serve as output leads of the package.
In addition, a structure of stacking two layers of frames is adopted, so that when the chip is conducted with the pin bonding pads through the leads, the first pin bonding pads 10 and/or the second pin bonding pads 20 can be selected to be connected according to the types and distribution positions of the pins of the chip, and the problem of crossed leads is avoided. Even if crossed wires are desired, the wires on the first pin pad 10 do not make contact with the wires on the second pin pad 20.
In an alternative embodiment of the present invention, referring to fig. 2, the first frame 1 further includes a first connection portion 11 for connecting the two first pin pads 10 together. The first connection 11 is part of the first frame 1 and may be made at the same time as the first lead pad 10 and the base island 12 are made. Two of the first lead pads 10 can be electrically connected through the first connection portion 11. The structural design is adopted, so that the chip can select the first pin bonding pad 10 at a close or reasonable position for connection. And for the whole package, the outward output pin is another first pin pad 10 or second pin pad 20. This avoids the use of crossing leads.
For the same reason, referring to fig. 3, the second frame 2 further includes a second connection portion 21 that conducts the two second lead pads 20 together. The second connection portion 21 is a part of the second frame 2, which may be formed at the same time as the second lead pad 20 is formed. Two of the second lead pads 20 can be conducted through the second connection portion 21. The structural design is adopted, so that the chip can select the second pin pad 20 at a closer or reasonable position to be connected. And for the whole package, the outward output pin is another second pin pad 20 or the first pin pad 10. This avoids the use of crossing leads.
In the package of the present invention, the first connection portion 11 may be provided in the first frame 1, or the second connection portion 21 may be provided in the second frame 2. It is also possible to provide the first connecting portion 11 in the first frame 1 and the second connecting portion 21 in the second frame 2. The specific design depends on the lead requirements of the chip and the design of the external output pins of the package, and will not be described in detail herein.
It should be noted that, when the two frames are both provided with the connecting portions to connect the respective lead pads, the two first lead pads 10 connected by the first connecting portion 11 and the two second lead pads 20 connected by the second connecting portion 21 need to be staggered with each other to avoid the connection between the first lead pads 10 and the second lead pads 20.
The present invention is not limited to the packaging structure, and the base island 12 in the first frame 1 is not essential. In the embodiment shown in fig. 4, the chip 3 is flip-chip mounted on the exposed first lead pad 10, and can be electrically connected to the first lead pad 10 by, for example, solder ball implantation or other methods known to those skilled in the art. In this embodiment, the second lead pad 20 at the top of the package structure is exposed from the package layer 4, and the first lead pad 10 at the bottom of the package structure is exposed from the package layer 4, so that both sides of the package structure can be used as external leads for connection.
In the embodiment shown in fig. 5, the chip 3 may be attached to the base island 12 by means well known to those skilled in the art, and the chip 3 may be connected to the exposed positions of the first lead pads 10 by wires or to the second lead pads 20 by wires. Alternatively, a plurality of pins arranged on the chip 3 need to be conducted to the outside. Part of the leads may be connected to the first lead pad 10 by a wire, and part of the leads may be connected to the second lead pad 20 by a wire.
In the embodiment illustrated in fig. 6, the chip is provided with two chips, respectively denoted as a first chip 3a attached to the base island 12, and a second chip 3b attached to the first chip 3 a.
The first chip 3a is connected to the exposed position of the first lead pad 10 by a wire; the second chip 3b is connected to the second lead pad 20 by a lead, and the problem of mutual contact of the leads caused by the sagging of the long leads can be avoided by adopting the design mode.
Wherein the second lead pad 20 of the second chip 3b is connected by wire, corresponding to the first lead pad 10 of the first chip 3a by wire. Since the first lead pad 10 and the second lead pad 20 at the corresponding positions are conducted together, the first chip 3a and the second chip 3b are conducted together. This structure is suitable for the situation that the stacked chips need to be connected and conducted together.
The second lead pads 20 connected to the second chip 3b by wire bonding may be offset from the first lead pads 10 connected to the first chip 3a by wire bonding. That is, the first chip 3a and the second chip are respectively led out through the respective pin pads, and will not be described in detail herein.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for purposes of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (9)
1. The utility model provides a packaging structure based on QFN frame which characterized in that: comprises a first frame and a second frame; the first frame comprises a plurality of first pin bonding pads which are arranged; the second frame comprises a plurality of second pin bonding pads which are arranged; the second pin bonding pad and the first pin bonding pad are arranged correspondingly and are bonded and conducted together through conductive adhesive; the size of the first pin bonding pad is larger than that of the second pin bonding pad, and part of the first pin bonding pad is exposed;
the chip packaging structure further comprises a chip and a packaging layer for packaging the chip, the first frame and the second frame together.
2. The package structure of claim 1, wherein: the outer end face of the first pin pad is exposed out of the packaging layer; and/or the outer end face of the second pin pad is exposed from the packaging layer.
3. The package structure of claim 1, wherein: the first frame comprises a first connecting part for conducting two first pin bonding pads together; alternatively, the second frame includes a second connection portion that conducts the two second lead pads together.
4. The package structure of claim 1, wherein: the first frame comprises a first connecting part for conducting two first pin bonding pads together; the second frame includes a second connection portion that conducts the two second lead pads together; and the two first pin bonding pads conducted by the first connecting parts and the two second pin bonding pads conducted by the second connecting parts are staggered with each other.
5. The package structure of claim 1, wherein: the chip is inversely installed at the position where the first pin bonding pad is exposed and is conducted with the first pin bonding pad.
6. The package structure of claim 1, wherein: the first frame further comprises a base island; the chip is attached to the base island and connected with the exposed position of the first pin bonding pad through a lead or/and connected with the second pin bonding pad through a lead.
7. The package structure of claim 1, wherein: the first frame further comprises a base island; the two chips are respectively marked as a first chip attached to the base island and a second chip attached to the first chip; the first chip is connected with the exposed position of the first pin bonding pad through a lead; the second chip is connected with the second pin bonding pad through a lead.
8. The package structure of claim 7, wherein: the second pin bonding pad of the second chip is connected through a lead wire, and corresponds to the first pin bonding pad of the first chip through a lead wire.
9. The package structure of claim 7, wherein: the second pin bonding pad of the second chip is connected through a lead, and the first pin bonding pad of the first chip is connected through a lead in a staggered mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920911085.7U CN209880601U (en) | 2019-06-17 | 2019-06-17 | QFN frame-based packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920911085.7U CN209880601U (en) | 2019-06-17 | 2019-06-17 | QFN frame-based packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209880601U true CN209880601U (en) | 2019-12-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920911085.7U Active CN209880601U (en) | 2019-06-17 | 2019-06-17 | QFN frame-based packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209880601U (en) |
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2019
- 2019-06-17 CN CN201920911085.7U patent/CN209880601U/en active Active
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