CN209880582U - Square flat pin-free package - Google Patents
Square flat pin-free package Download PDFInfo
- Publication number
- CN209880582U CN209880582U CN201920913202.3U CN201920913202U CN209880582U CN 209880582 U CN209880582 U CN 209880582U CN 201920913202 U CN201920913202 U CN 201920913202U CN 209880582 U CN209880582 U CN 209880582U
- Authority
- CN
- China
- Prior art keywords
- chip
- bonding pad
- metal cover
- cover plate
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model relates to a square flat pin-free package, the frame comprises a middle bonding pad positioned in the middle area, a conductive bonding pad arranged around the middle bonding pad, and a supporting bonding pad; the chip is arranged on the middle bonding pad; the metal cover plate is positioned above the chip and supported on the support bonding pad through support legs; the packaging structure further comprises a packaging layer which packages the frame, the chip and the metal cover plate together, and the packaging layer is filled in gaps among the frame, the chip and the metal cover body. In the packaging of the utility model, most of the heat emitted by the chip still radiates out through the middle bonding pad; part of heat emitted by the chip can be upwards emitted through the metal cover plate, so that the heat dissipation capacity of the whole package is improved.
Description
Technical Field
The utility model relates to a encapsulation of chip, more specifically, the utility model relates to an encapsulation of QFN mode.
Background
QFN (Quad Flat No-lead Package), one of the surface mount packages, is known. QFN is a leadless package, square or rectangular, with a large area of exposed pads at the center of the bottom of the package for heat conduction, and conductive pads surrounding the large pads around the periphery of the package for electrical connection. QFN packages provide excellent electrical performance because they do not have gull-wing leads as do conventional SOIC and TSOP packages, the electrical path between the inner leads and the pads is short, the self-inductance, and the wiring resistance within the package is low.
It provides the primary heat dissipation path through the exposed leadframe pad for dissipating heat within the package. The heat sink pad is typically soldered directly to the circuit board; a small portion of the heat is dissipated from the encapsulation layer.
In the QFN package with such a structure, for a high-power-consumption chip, the heat dissipation structure still cannot meet the working junction temperature requirement of the chip, so that the heat dissipation structure needs to be prioritized further.
SUMMERY OF THE UTILITY MODEL
It is an object of the present invention to provide a square flat leadless package.
According to one aspect of the present invention, a quad flat non-leaded package is provided, comprising a frame, a chip, a metal cover plate;
the frame comprises a middle bonding pad positioned in a middle area, a conductive bonding pad arranged around the middle bonding pad, and a support bonding pad;
the chip is arranged on the middle bonding pad; the metal cover plate is positioned above the chip and supported on the support bonding pad through support legs;
the packaging structure further comprises a packaging layer which packages the frame, the chip and the metal cover plate together, wherein the packaging layer is filled in gaps among the frame, the chip and the metal cover body.
Optionally, the support pad extends from the middle pad.
Optionally, the plurality of support pads are distributed in the circumferential direction of the middle pad; the supporting legs and the supporting pads are correspondingly arranged and distributed on the circumferential direction of the metal cover plate.
Optionally, the central bonding pad is rectangular, and four support bonding pads are provided, and extend from four corners of the central bonding pad respectively.
Optionally, the orthographic projection of the chip on the middle bonding pad is completely positioned in the orthographic projection of the metal cover plate on the middle bonding pad.
Optionally, an end face of the metal cover plate is exposed from a surface of the encapsulation layer.
Optionally, the bottom surface of the middle pad is exposed from the surface of the encapsulation layer.
Optionally, the metal cover plate is circular.
Optionally, the chip is electrically connected to the conductive pad through a wire.
In the packaging of the utility model, most of the heat emitted by the chip still radiates out through the middle bonding pad; part of heat emitted by the chip can be upwards emitted through the metal cover plate, so that the heat dissipation capacity of the whole package is improved.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a cross-sectional view of the package of the present invention.
Fig. 2 is a top view of the frame of fig. 1.
FIG. 3 is a top view of a metal cover plate and support legs.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless specifically stated otherwise, the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be considered a part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1, the present invention provides a quad flat non-leaded package (QFN) including a frame, a chip 2, a metal cover 4, and an encapsulation layer 5 encapsulating the chip 2, the metal cover 4 and the frame.
Referring to fig. 2, the frame of the present invention includes a middle pad 1 located in the middle region, and a conductive pad 7 disposed around the middle pad 1. Middle part pad 1 can adopt circular or rectangle, in the utility model discloses a specific embodiment, middle part pad 1 adopts the square. The conductive pads 7 are provided with four groups, which are respectively distributed at the four side wall positions of the middle pad 1, and a gap 6 is arranged between the conductive pads and the middle pad 1. The frame further comprises support pads 10, which support pads 10 may be independent of the middle pads 1, the conductive pads 7. In an alternative embodiment of the invention, the support pads 10 extend from the central pad 1.
The utility model discloses a package, chip 2 sets up on middle part pad 1. For example, the chip 2 may be attached to the middle pad 1 by a method known to those skilled in the art, and the leads of the chip 2 may be electrically connected to the conductive pads 7 through the leads 3 to lead out or in the electrical signals of the chip 2.
The metal cover plate 40 is located above the chip 2 and supported on the support pads 10 by support legs 41. The number and positions of the support legs 41 correspond to the support pads 10. The metal cover plate 4 may be circular or rectangular.
For example, when the central pad 1 has a square shape, four support pads 10 may be provided, extending outward from four corner positions of the central pad 1 to four corner positions of the frame, respectively. The support legs 41 are correspondingly provided in four numbers, and are distributed in the circumferential direction of the support cover 40. The metal cover plate 40 is supported above the chip 2 by four support legs 41.
The packaging layer 5 packages the metal cover plate, the chip and the frame together, and the packaging layer 5 is filled in a gap 6 between the metal cover plate, the chip and the frame.
The packaging adopts the structure, most of heat emitted by the chip is still dissipated through the middle bonding pad; part of heat emitted by the chip can be upwards emitted through the metal cover plate, so that the heat dissipation capacity of the whole package is improved.
Alternatively, the orthographic projection of chip 2 on middle pad 1 is entirely within the orthographic projection of metal cover 40 on middle pad 1, which causes metal cover 40 to completely cover chip 2. The heat emitted upwards by the chip 2 is guided out through the metal cover plate 40 as far as possible, and the upward heat radiation capability of the package is improved.
Optionally, the upper end surface of the metal cover plate 40 is exposed from the surface of the encapsulation layer 5, so that heat on the metal cover plate 40 can be quickly dissipated.
Alternatively, the bottom surface of the middle pad 1 is exposed from the bottom surface of the encapsulation layer 5, so that heat emitted from the chip can be quickly dissipated through the middle pad 1.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for purposes of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (9)
1. A quad flat non-leaded package, comprising: comprises a frame, a chip and a metal cover plate;
the frame comprises a middle bonding pad positioned in a middle area, a conductive bonding pad arranged around the middle bonding pad, and a support bonding pad;
the chip is arranged on the middle bonding pad; the metal cover plate is positioned above the chip and supported on the support bonding pad through support legs;
the packaging structure further comprises a packaging layer which packages the frame, the chip and the metal cover plate together, wherein the packaging layer is filled in gaps among the frame, the chip and the metal cover body.
2. The qfn package of claim 1, wherein: the support pad extends from the middle pad.
3. The qfn package of claim 1, wherein: the supporting welding pads are arranged in a plurality and distributed in the circumferential direction of the middle welding pad; the supporting legs and the supporting pads are correspondingly arranged and distributed on the circumferential direction of the metal cover plate.
4. The qfn package of claim 3, wherein: the middle bonding pad is rectangular, and the number of the supporting bonding pads is four, and the supporting bonding pads respectively extend out from four corner positions of the middle bonding pad.
5. The qfn package of claim 1, wherein: the orthographic projection of the chip on the middle bonding pad is completely positioned in the orthographic projection of the metal cover plate on the middle bonding pad.
6. The qfn package of claim 1, wherein: the end face of the metal cover plate is exposed out of the surface of the packaging layer.
7. The qfn package of claim 1, wherein: the bottom surface of the middle bonding pad is exposed out of the surface of the packaging layer.
8. The qfn package of claim 1, wherein: the metal cover plate is circular.
9. The qfn package of claim 1, wherein: the chip is conducted with the conductive pad through a lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920913202.3U CN209880582U (en) | 2019-06-17 | 2019-06-17 | Square flat pin-free package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920913202.3U CN209880582U (en) | 2019-06-17 | 2019-06-17 | Square flat pin-free package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209880582U true CN209880582U (en) | 2019-12-31 |
Family
ID=68947223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920913202.3U Active CN209880582U (en) | 2019-06-17 | 2019-06-17 | Square flat pin-free package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209880582U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111710668A (en) * | 2020-08-24 | 2020-09-25 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure, manufacturing method thereof and electronic equipment |
-
2019
- 2019-06-17 CN CN201920913202.3U patent/CN209880582U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111710668A (en) * | 2020-08-24 | 2020-09-25 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure, manufacturing method thereof and electronic equipment |
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