TW201947723A - Quad flat non-lead package and method for enabling it to be cut which can meet the user's customized requirement for the integrated circuit chip package with sensors and improve the adaptability of QFN and terminal - Google Patents

Quad flat non-lead package and method for enabling it to be cut which can meet the user's customized requirement for the integrated circuit chip package with sensors and improve the adaptability of QFN and terminal Download PDF

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TW201947723A
TW201947723A TW108116277A TW108116277A TW201947723A TW 201947723 A TW201947723 A TW 201947723A TW 108116277 A TW108116277 A TW 108116277A TW 108116277 A TW108116277 A TW 108116277A TW 201947723 A TW201947723 A TW 201947723A
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package
pad
integrated circuit
circuit chip
cuttable
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TW108116277A
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楊志
戴華東
張靖愷
劉亞雄
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開曼群島商敦泰電子有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a quad flat non-lead package (QFN) and a method for enabling it to be cut. The package includes an integrated circuit chip, a lead frame, a bonding pad, a metal wire for electrically connecting the integrated circuit chip with the bonding pad, and a package body for packaging the integrated circuit chip, the lead frame, the bonding pad and the metal wire. The integrated circuit chip is fixedly installed on the lead frame, and the bonding pad is disposed around the integrated circuit chip. The bonding pad includes non-cuttable pads and cuttable pads, both of which are electrically connected together. The non-cuttable pads are electrically connected to the integrated circuit chip via the metal wire. The cuttable pads are extended from the non-cuttable pad to the outside of the package body. The bonding pad packaged by the package body at least includes a conductive contact which can be electrically contacted by the electrical components outside the package. The position of the bonding pad is set so that the end of the cuttable pad that is not connected to the non-cuttable pad is arranged along the rectangular package boundary. The minimum cutting boundary of the package is the smallest circle that prevents the non-cuttable pad from being cut. The present invention increases the size of the bonding pad along the extension direction so that the bonding pad can be cut to meet the user's customized requirement for the integrated circuit chip packages with sensors. It is suitable for users to cut the integrated circuit chip package into the required external structure, and improve the adaptability of QFN and the terminal. The large QFN simplifies the manufacturing process, further reduces the manufacturing costs, facilitates the transportation and packaging, and makes it easier for users to customize the cutting to obtain the expected QFN.

Description

方形扁平無接腳封裝及使其能夠被切割的方法Square flat pinless package and method for enabling it to be cut

本發明涉及積體電路晶片,特別是涉及積體電路晶片的封裝及其實現方法。The present invention relates to an integrated circuit chip, and more particularly to a package of an integrated circuit chip and a method for implementing the same.

現有技術簡稱QFN的無接腳方形扁平封裝(Quad Flat Non-lead package, QFN)包括積體電路晶片,用於固定安裝積體電路晶片的引線框架,圍繞積體電路晶片設置的焊墊,用於將積體電路晶片與焊墊電性連接的金屬線,以及封裝積體電路晶片、引線框架、焊墊和金屬線的封裝體。焊墊通常沿著矩形邊線佈設。現有技術QFN具有體積小的特點,採用的引線框架和焊墊利於封裝散熱,引線框架吸濕性低且成本低,使封裝適用場合多、生產成本低、且生產週期短。但是,現有技術QFN由於採用無接腳設計,焊墊體積小且直接用作封裝的導電觸點,使封裝不能被切割,與用戶希望具有感測器的積體電路晶片封裝的外形結構能夠被定制的需求相矛盾,使現有技術QFN與終端適配性差。A quad flat non-lead package (QFN) known as QFN in the prior art includes an integrated circuit chip, a lead frame for fixedly mounting the integrated circuit chip, and a bonding pad provided around the integrated circuit chip. A metal wire for electrically connecting the integrated circuit chip and the bonding pad, and a package for packaging the integrated circuit chip, the lead frame, the bonding pad and the metal wire. Pads are usually routed along rectangular edges. The QFN of the prior art has the characteristics of small volume, and the adopted lead frame and bonding pads are beneficial to heat dissipation of the package. The lead frame has low hygroscopicity and low cost, which makes the package suitable for many applications, low production cost and short production cycle. However, because the prior art QFN uses a pinless design, the solder pads are small and directly used as the conductive contacts of the package, so that the package cannot be cut, and the user wants the external structure of the integrated circuit chip package with a sensor to be The need for customization is contradictory, making the existing technology QFN poorly adaptable to the terminal.

本發明要解決的技術問題在於避免現有技術的不足之處而提出能夠被切割的無引線方形扁平封裝QFN,以及使無引線方形扁平封裝QFN能夠被切割的方法,通過對焊墊的改進而提升QFN的適配性,滿足用戶定制需求。The technical problem to be solved by the present invention is to avoid the shortcomings of the prior art and propose a leadless square flat package QFN that can be cut, and a method for enabling the leadless square flat package QFN to be cut, which is improved by improving the pads. The adaptability of QFN meets user-defined requirements.

本發明解決所述技術問題可以通過採用以下技術方案來實現:The present invention can solve the technical problem by adopting the following technical solutions:

設計、製造一種能夠被切割的方形扁平無接腳封裝,包括至少一積體電路晶片,引線框架,至少一焊墊,用於電性連接積體電路晶片和焊墊的金屬線,以及封裝所述積體電路晶片、引線框架、焊墊和金屬線的封裝體。所述積體電路晶片固定安裝在引線框架上。所述焊墊圍繞積體電路晶片設置,包括電性連接在一起的不可切割焊墊和可切割焊墊。不可切割焊墊借助金屬線電性連接積體電路晶片。可切割焊墊由不可切割焊墊向封裝體外部方向延伸。被封裝體封裝的焊墊至少有一能夠被封裝外的電氣元件電性接觸的導電觸點。Design and manufacture a square flat pinless package that can be cut, including at least one integrated circuit chip, lead frame, at least one solder pad, metal wires for electrically connecting the integrated circuit chip and solder pad, and a package The package of the integrated circuit chip, the lead frame, the bonding pad and the metal wire is described. The integrated circuit chip is fixedly mounted on a lead frame. The solder pads are arranged around the integrated circuit wafer and include an uncuttable solder pad and a dicable solder pad which are electrically connected together. The non-cuttable solder pads are electrically connected to the integrated circuit chip via a metal wire. The dicing pad extends from the non-cutting pad to the outside of the package. At least one of the bonding pads encapsulated by the package body can be electrically contacted by electrical components outside the package.

具體地,所述焊墊設置的位置使可切割焊墊未連接不可切割焊墊的端部沿著矩形的封裝邊界設置。Specifically, the pad is disposed at a position where the end of the cuttable pad not connected to the non-cuttable pad is disposed along a rectangular package boundary.

從實現切割的角度,封裝的最小切割邊界是能夠使不可切割焊墊不被切割的最小環形。具體而言,不可切割焊墊與可切割焊墊連接點沿著矩形邊線圍成的佈設邊界設置,封裝的最小切割邊界就是矩形邊線圍成的佈設邊界。或者,不可切割焊墊與可切割焊墊連接點沿著矩形邊線圍成的佈設邊界設置,封裝的最小切割邊界是將所有不可切割焊墊圍在其中、且至少與兩不可切割焊墊邊緣內接的圓周線邊界。From the perspective of achieving cutting, the minimum cutting boundary of the package is the smallest ring shape that can prevent the non-cuttable pads from being cut. Specifically, the connection point of the non-cuttable pad and the dicable pad is set along a layout boundary surrounded by a rectangular border, and the minimum cutting boundary of the package is a layout boundary surrounded by a rectangular border. Alternatively, the connection points of the non-cuttable pads and the dicable pads are set along a layout boundary surrounded by a rectangular edge. The minimum cutting boundary of the package is to surround all the non-cuttable pads and at least with the edges of the two non-cuttable pads. Connected by the border of the circle.

為獲得可切割的區域,可切割焊墊向封裝體外延伸的延伸方向與封裝能夠被切割的切割方向的夾角大於0度且小於180度。進一步地,可切割焊墊向封裝體外延伸的延伸方向與封裝能夠被切割的切割方向的夾角不小於45度且不大於135度。較佳地,可切割焊墊向封裝體外延伸的延伸方向與封裝能夠被切割的切割方向垂直。In order to obtain a cuttable area, the angle between the extension direction of the cuttable pad extending outside the package and the cutting direction in which the package can be cut is greater than 0 degrees and less than 180 degrees. Further, the included angle between the extending direction of the dicing pad extending outside the package and the cutting direction in which the package can be cut is not less than 45 degrees and not more than 135 degrees. Preferably, the extending direction of the dicing pad extending outside the package is perpendicular to the cutting direction in which the package can be cut.

作為焊墊的導電觸點實現方案,焊墊的導電觸點包括第一導電觸點、第二導電觸點、第三導電觸點和第四導電觸點中的至少一個。第一導電觸點是沿封裝能夠被切割的切割方向設置在不可切割焊墊至少一端部的導電觸電。第二導電觸點是沿可切割焊墊向封裝體外部延伸的延伸方向設置在該可切割焊墊端部的導電觸點。第三導電觸點是切割後在可切割焊墊的端部形成的導電觸點。第四導電觸點是可切割焊墊被完全切除而在不可切割焊墊形成的導電觸點。As a solution for implementing the conductive contacts of the solder pad, the conductive contacts of the solder pad include at least one of a first conductive contact, a second conductive contact, a third conductive contact, and a fourth conductive contact. The first conductive contact is a conductive electric shock provided on at least one end portion of the non-cuttable pad along a cutting direction in which the package can be cut. The second conductive contact is a conductive contact provided at an end of the dicing pad in an extending direction in which the dicing pad extends to the outside of the package. The third conductive contact is a conductive contact formed at the end of the dicing pad after cutting. The fourth conductive contact is a conductive contact formed on the non-cuttable pad when the dicable pad is completely cut off.

具體而言,所述引線框架包括環柱狀的內框架,環柱狀的外框架,以及至少一連接筋。內框架被套在外框架內,內框架與外框架借助連接筋固定在一起。所述積體電路晶片固定安裝在內框架上。所述焊墊的可切割焊墊固定安裝在外框架上。Specifically, the lead frame includes a ring-column-shaped inner frame, a ring-column-shaped outer frame, and at least one connecting rib. The inner frame is sheathed in the outer frame, and the inner frame and the outer frame are fixed together by a connecting rib. The integrated circuit chip is fixedly mounted on the inner frame. The cuttable welding pad of the welding pad is fixedly installed on the outer frame.

進一步地,所述積體電路晶片借助晶粒粘合膜固定安裝在內框架上。Further, the integrated circuit wafer is fixedly mounted on the inner frame by a die-bonding film.

具體地,所述積體電路晶片包括積體電路晶片和積體電路晶粒。Specifically, the integrated circuit wafer includes an integrated circuit wafer and an integrated circuit die.

具體地,所述封裝體是環氧樹脂注塑化合物。Specifically, the package is an epoxy injection molding compound.

本發明解決所述技術問題又可以通過採用以下技術方案來實現:The present invention can solve the technical problems by adopting the following technical solutions:

設計、製造一種能夠被切割的方形扁平無接腳封裝大板,包括被平鋪封裝成板狀整體的至少兩方形扁平無接腳封裝。所述方形扁平無接腳封裝包括至少一積體電路晶片,引線框架,至少一焊墊,用於電性連接積體電路晶片和焊墊的金屬線,以及封裝所述積體電路晶片、引線框架、焊墊和金屬線的封裝體。所述積體電路晶片固定安裝在引線框架上。所述焊墊圍繞積體電路晶片設置,包括電性連接在一起的不可切割焊墊和可切割焊墊。不可切割焊墊借助金屬線電性連接積體電路晶片。可切割焊墊由不可切割焊墊向封裝體外部方向延伸。被封裝體封裝的焊墊至少有一能夠被封裝外的電氣元件電性接觸的導電觸點。Design and manufacture a large square flat no-pin package that can be cut, including at least two square flat no-pin packages that are tiled and packaged into a plate-shaped whole. The square flat pinless package includes at least one integrated circuit chip, a lead frame, at least one solder pad, a metal wire for electrically connecting the integrated circuit chip and the solder pad, and packaging the integrated circuit chip and leads. Encapsulation of frames, pads and wires. The integrated circuit chip is fixedly mounted on a lead frame. The solder pads are arranged around the integrated circuit wafer and include an uncuttable solder pad and a dicable solder pad which are electrically connected together. The non-cuttable solder pads are electrically connected to the integrated circuit chip via a metal wire. The dicing pad extends from the non-cutting pad to the outside of the package. At least one of the bonding pads encapsulated by the package body can be electrically contacted by electrical components outside the package.

本發明解決所述技術問題還可以通過採用以下技術方案來實現:The present invention can also solve the technical problems by adopting the following technical solutions:

提出一種使方形扁平無接腳封裝能夠被切割的方法,所述封裝包括至少一積體電路晶片,能夠固定安裝積體電路晶片的引線框架,至少一焊墊,用於電性連接積體電路晶片和焊墊的金屬線,以及封裝所述積體電路晶片、引線框架、焊墊和金屬線的封裝體。所述方法是,為焊墊設置可切割焊墊和不可切割焊墊;將焊墊圍繞積體電路晶片設置,不可切割焊墊借助金屬線電性連接積體電路晶片;可切割焊墊由不可切割焊墊向封裝體外部方向延伸;使封裝後的焊墊至少有一能夠被封裝外的電氣元件電性接觸的導電觸點。A method is provided for enabling a square flat pinless package to be cut. The package includes at least one integrated circuit chip, a lead frame capable of fixedly mounting the integrated circuit chip, and at least one solder pad for electrically connecting the integrated circuit. Metal wires for wafers and pads, and packages for packaging the integrated circuit wafer, lead frame, pads and metal wires. The method is to set dicable pads and non-cuttable pads for the pads; set the pads around the integrated circuit wafer, and the non-cuttable pads are electrically connected to the integrated circuit wafer by means of metal wires; The cutting pads extend toward the outside of the package body; at least one of the conductive pads that can be electrically contacted by electrical components outside the package is provided after the packaged pads.

同現有技術相比較,本發明“方形扁平無接腳封裝及使其能夠被切割的方法”的技術效果在於:Compared with the prior art, the technical effect of the “square flat contactless package and method for enabling it to be cut” of the present invention lies in:

沿著向封裝體外部的延伸方向增設可切割焊墊,增加了焊墊沿延伸方向的尺寸,使焊墊能夠被切割,而且不因被切割影響無接腳的導電觸點結構,滿足使用者對具有感測器的積體電路晶片封裝的客製化需求,適於使用者將積體電路晶片封裝切割成所需要的外形結構,提升QFN與終端的適配性;方形扁平無接腳封裝大板使製作製程簡化,更加降低成本,便於運輸包裝,更便於用戶定制切割獲取預期的QFN。The cutting pads are added along the extension direction to the outside of the package, which increases the size of the pads in the extension direction, so that the pads can be cut, and the conductive contact structure without pins is not affected by the cutting, which meets the needs of users. The customized requirements for integrated circuit chip packages with sensors are suitable for users to cut the integrated circuit chip packages into the required external structure to improve the adaptability of QFN and terminals; square flat no-pin package The large board simplifies the manufacturing process, further reduces costs, facilitates transportation and packaging, and makes it easier for users to customize cutting to obtain the expected QFN.

以下結合圖式所示較佳實施例作進一步詳述。The following further describes the preferred embodiment in combination with the drawings.

本發明提出一種能夠被切割的方形扁平無接腳封裝QFN 7,如圖1和圖2所示,包括至少一積體電路晶片4,引線框架2,至少一焊墊1,用於電性連接積體電路晶片4和焊墊1的金屬線3,以及封裝所述積體電路晶片4、引線框架2、焊墊1和金屬線3的封裝體5。所述積體電路晶片4包括積體電路晶圓(Wafer)和積體電路晶粒(Die)。所述積體電路晶片4固定安裝在引線框架2上。所述焊墊1圍繞積體電路晶片4設置,包括電性連接在一起的不可切割焊墊12和可切割焊墊11。不可切割焊墊12借助金屬線3電性連接積體電路晶片4。可切割焊墊11由不可切割焊墊12向封裝體5外部方向延伸。被封裝體5封裝的焊墊1至少有一能夠被QFN外的電氣元件電性接觸的導電觸點。The present invention proposes a square flat pinless package QFN 7 that can be cut. As shown in FIG. 1 and FIG. 2, the QFN 7 includes at least one integrated circuit chip 4, a lead frame 2, and at least one solder pad 1 for electrical connection. The integrated circuit wafer 4 and the metal wire 3 of the bonding pad 1, and the package 5 which encapsulates the integrated circuit wafer 4, the lead frame 2, the bonding pad 1 and the metal wire 3. The integrated circuit wafer 4 includes a integrated circuit wafer (Wafer) and an integrated circuit die (Die). The integrated circuit chip 4 is fixedly mounted on the lead frame 2. The solder pad 1 is disposed around the integrated circuit wafer 4 and includes an uncuttable solder pad 12 and a dicable solder pad 11 which are electrically connected together. The non-cuttable bonding pad 12 is electrically connected to the integrated circuit chip 4 through a metal wire 3. The dicing pad 11 extends from the non-cutting pad 12 to the outside of the package 5. At least one of the bonding pads 1 encapsulated by the package body 5 can be electrically contacted by electrical components outside the QFN.

可切割焊墊11向封裝體5外部方向延伸,增加了焊墊1沿延伸方向的尺寸,使焊墊1能夠被切割。由於金屬線3電性連接在不可切割焊墊12上,無論怎樣切割可切割焊墊11都不會影響QFN無接腳的導電觸點結構。本發明滿足了使用者對具有感測器的積體電路晶片封裝的客製化需求,適於使用者將積體電路晶片封裝切割成所需要的外形結構,提升QFN與終端的適配性。具有感測器的積體電路晶片例如指紋識別晶片、壓力檢測晶片、光電感測晶片等。The dicing pads 11 extend toward the outside of the package 5, increasing the size of the pads 1 in the extending direction, so that the pads 1 can be cut. Since the metal wire 3 is electrically connected to the non-cuttable solder pad 12, no matter how the cuttable solder pad 11 is cut, it will not affect the QFN non-pin conductive contact structure. The invention satisfies the user's customized needs for integrated circuit chip packages with sensors, and is suitable for users to cut the integrated circuit chip packages into the required external structure to improve the adaptability of QFN and terminals. Integrated circuit wafers with sensors such as fingerprint identification wafers, pressure detection wafers, photosensor wafers, and the like.

為使封裝具備矩形橫截面,或者扁四棱柱外形,本發明較佳實施例,所述焊墊1設置的位置使可切割焊墊11未連接不可切割焊墊12的端部沿著矩形的封裝邊界C5設置。也就是可切割焊墊11的端部沿著矩形邊線的封裝邊界C5設置,而不可切割焊墊12的佈設可以不受限定。本發明較佳實施例,從橫截面看,不可切割焊墊12也是沿一矩形邊線圍繞積體電路晶片2設置。In order to make the package have a rectangular cross-section or a flat quadrangular prism shape, in a preferred embodiment of the present invention, the pad 1 is disposed at a position where the end of the cuttable pad 11 which is not connected to the non-cuttable pad 12 is along the rectangular package. Border C5 is set. That is, the end of the cuttable solder pad 11 is disposed along the packaging boundary C5 of the rectangular border, and the layout of the non-cuttable solder pad 12 may not be limited. In a preferred embodiment of the present invention, the non-cuttable pads 12 are also arranged around the integrated circuit wafer 2 along a rectangular edge line when viewed from a cross section.

由於焊墊1圍繞積體電路晶片4設置,本發明QFN的切割範圍就是不可切割焊墊12的外部。從而本發明QFN封裝的最小切割邊界是能夠使不可切割焊墊12不被切割的最小環形。最小切割邊界的具體形狀由切割面決定。Since the bonding pad 1 is disposed around the integrated circuit wafer 4, the cutting range of the QFN of the present invention is the outside of the non-cutting bonding pad 12. Therefore, the minimum cutting boundary of the QFN package of the present invention is the smallest ring shape that can prevent the non-cuttable pad 12 from being cut. The specific shape of the minimum cutting boundary is determined by the cutting surface.

本發明較佳實施例,以具有矩形邊線橫截面的四面柱形切割面,以及具有圓周線形橫截面的圓柱面或者具有橢圓周線形橫截面的橢圓柱面切割面說明QFN的最小切割邊界。本發明較佳實施例,如圖1所示,不可切割焊墊12與可切割焊墊11連接點沿著矩形邊線圍成的佈設邊界C1設置,如果採用以具有矩形邊線橫截面的四面柱形作為切割面,本發明QFN的最小切割邊界就是矩形邊線圍成的佈設邊界C1。如果採用具有圓周線形橫截面的圓柱面或者具有橢圓周線形橫截面的橢圓柱面作為切割面時,本發明QFN的最小切割邊界是將所有不可切割焊墊12圍在其中、且至少與兩不可切割焊墊12邊緣內接的圓周線邊界C2。其邊緣內接於圓周線邊界C2的不可切割焊墊12越多,意味著圓周線邊界C2的範圍越小。In the preferred embodiment of the present invention, the minimum cutting boundary of the QFN is described by a four-sided cylindrical cutting surface with a rectangular sideline cross section, and a cylindrical surface with a circumferential linear cross section or an elliptic cylindrical cutting surface with an elliptical circumferential cross section. In the preferred embodiment of the present invention, as shown in FIG. 1, the connection point of the non-cuttable pad 12 and the cuttable pad 11 is set along a layout boundary C1 surrounded by a rectangular edge line. If a four-sided cylindrical shape having a rectangular edge line cross-section is used, As a cutting surface, the minimum cutting boundary of the QFN of the present invention is a layout boundary C1 surrounded by a rectangular edge. If a cylindrical surface with a circumferential cross-section or an elliptical cylinder with an elliptical cross-section is used as the cutting surface, the minimum cutting boundary of the QFN of the present invention is to enclose all the non-cuttable pads 12 and at least not A peripheral line boundary C2 inscribed in the edge of the bonding pad 12 is cut. The more non-cuttable pads 12 whose edges are inscribed on the peripheral line boundary C2, the smaller the range of the peripheral line boundary C2 is.

本發明可切割焊墊11向封裝體5外延伸的延伸方向e與QFN能夠被切割的切割方向s的夾角β大於0度且小於180度,也就是延伸方向e與切割方向s應當不共線或者不平行。The angle β between the extending direction e of the dicing pad 11 extending outside the package 5 and the cutting direction s in which the QFN can be cut is greater than 0 degrees and less than 180 degrees, that is, the extending direction e and the cutting direction s should not be in line. Or not parallel.

作為實用的設置方案,本發明可切割焊墊11向封裝體5外延伸的延伸方向e與QFN能夠被切割的切割方向s的夾角β不小於45度且不大於135度。As a practical arrangement, the included angle β between the extending direction e of the dicing pad 11 extending outside the package 5 and the cutting direction s in which the QFN can be cut is not less than 45 degrees and not more than 135 degrees.

作為更常用的設置方案,本發明較佳實施例,如圖2所示,可切割焊墊11向封裝體5外延伸的延伸方向e與QFN能夠被切割的切割方向s垂直,從而使QFN具有較大的可切割範圍。As a more commonly used arrangement, in the preferred embodiment of the present invention, as shown in FIG. 2, the extending direction e of the dicing pad 11 extending outside the package 5 is perpendicular to the cutting direction s in which the QFN can be cut, so that the QFN has Large cutting range.

本發明較佳實施例,如圖1和圖2所示,可切割焊墊11和不可切割焊墊12都呈柱狀,可切割焊墊11和不可切割焊墊12各自的一端部電性連接在一起。As shown in FIG. 1 and FIG. 2, in the preferred embodiment of the present invention, the cuttable pad 11 and the non-cuttable pad 12 are both columnar, and one end of each of the cuttable pad 11 and the non-cuttable pad 12 is electrically connected. Together.

通常焊墊1的導電觸點應當外露在封裝體5外而能夠被QFN外的電氣元件電性接觸,其實現方案有多種。本發明QFN由於能夠被切割,就使焊墊1的導電觸點可以在一個以上。本發明焊墊1的導電觸點包括第一導電觸點、第二導電觸點、第三導電觸點和第四導電觸點中的至少一個。如圖2所示,第一導電觸點121是沿QFN能夠被切割的切割方向s設置在不可切割焊墊12至少一端部的導電觸電。如圖2所示,第二導電觸點111是沿可切割焊墊11向封裝體5外部延伸的延伸方向e設置在該可切割焊墊11端部的導電觸點111。第三導電觸點是切割後在可切割焊墊11的端部形成的導電觸點。第四導電觸點是可切割焊墊被完全切除而在不可切割焊墊形成的導電觸點。第一導電觸點121和第二導電觸點111能夠在QFN封裝完成後就形成,而第三導電觸點和第四導電觸點應當是QFN被切割後形成。Generally, the conductive contacts of the bonding pad 1 should be exposed outside the package body 5 and can be electrically contacted by electrical components outside the QFN. There are various implementation schemes. Since the QFN of the present invention can be cut, the conductive contacts of the bonding pad 1 can be more than one. The conductive contacts of the solder pad 1 of the present invention include at least one of a first conductive contact, a second conductive contact, a third conductive contact, and a fourth conductive contact. As shown in FIG. 2, the first conductive contact 121 is a conductive electric shock provided at at least one end portion of the non-cuttable pad 12 in a cutting direction s in which the QFN can be cut. As shown in FIG. 2, the second conductive contact 111 is a conductive contact 111 provided at an end of the dicing pad 11 along an extending direction e of the dicing pad 11 extending to the outside of the package 5. The third conductive contact is a conductive contact formed at the end of the dicing pad 11 after cutting. The fourth conductive contact is a conductive contact formed on the non-cuttable pad when the dicable pad is completely cut off. The first conductive contact 121 and the second conductive contact 111 can be formed after the QFN package is completed, and the third conductive contact and the fourth conductive contact should be formed after the QFN is cut.

本發明較佳實施例,如圖1所示,所述引線框架2包括環柱狀的內框架21,環柱狀的外框架22,以及至少一連接筋23。內框架21被套在外框架22內,內框架21與外框架22借助連接筋23固定在一起。所述積體電路晶片4固定安裝在內框架21上。所述焊墊1的可切割焊墊11固定安裝在外框架22上。外框架22為封裝前佈設焊墊1提供支撐結構。本發明較佳實施例,外框架22是具有矩形邊線圍成的環形橫截面的四棱環柱,外框架22內面圍成的四棱柱面的橫截面是矩形邊線圍成的外邊界C4。當以具有矩形邊線橫截面的四面柱形作為切割面時,可將外邊界C4設置為最大切割方邊界。當以具有圓周線形橫截面的圓柱面或者具有橢圓周形橫截面的橢圓柱面作為切割面時,可將內切於外邊界C4的圓周線形或者橢圓周線形邊界C3設置為最大切割圓邊界。In a preferred embodiment of the present invention, as shown in FIG. 1, the lead frame 2 includes a ring-shaped inner frame 21, a ring-shaped outer frame 22, and at least one connecting rib 23. The inner frame 21 is sheathed in the outer frame 22, and the inner frame 21 and the outer frame 22 are fixed together by a connecting rib 23. The integrated circuit chip 4 is fixedly mounted on the inner frame 21. The dicing pads 11 of the pads 1 are fixedly mounted on the outer frame 22. The outer frame 22 provides a support structure for laying the bonding pads 1 before packaging. In the preferred embodiment of the present invention, the outer frame 22 is a quadrangular ring column having a circular cross section surrounded by a rectangular side line, and the cross section of the quadrangular column surface surrounded by the inner surface of the outer frame 22 is an outer boundary C4 surrounded by a rectangular side line. When a quadrilateral cylinder having a rectangular side-line cross section is used as the cutting surface, the outer boundary C4 can be set as the maximum cutting-side boundary. When a cylindrical surface with a circumferential cross-section or an elliptical cylinder with an oval cross-section is used as the cutting surface, the circumferential or elliptical circumferential boundary C3 inscribed at the outer boundary C4 may be set as the maximum cutting circle boundary.

本發明較佳實施例,如圖2所示,所述積體電路晶片4借助簡稱DAF的晶粒粘合膜(Die Attach Film) 6固定安裝在內框架21上。In a preferred embodiment of the present invention, as shown in FIG. 2, the integrated circuit wafer 4 is fixedly mounted on the inner frame 21 by means of a die attach film (Die Attach Film) 6 referred to as DAF.

本發明較佳實施例,如圖1和圖2所示,所述封裝體5是簡稱EMC的環氧樹脂注塑化合物(Epoxy Molding Compound)。In a preferred embodiment of the present invention, as shown in FIG. 1 and FIG. 2, the package 5 is an epoxy injection molding compound (EMC) for short.

基於本發明上述方案的能夠被切割的方形扁平無接腳封裝QFN 7,如圖3所示,本發明還提出一種能夠被切割的方形扁平無接腳封裝QFN大板8,包括被平鋪封裝成板狀整體的至少兩方形扁平無接腳封裝QFN 7。平鋪封裝是指將QFN 7基於同一基準面,互相邊界相鄰地平鋪佈設而形成的封裝結構。如圖1和圖2所示,QFN 7包括至少一積體電路晶片4,引線框架2,至少一焊墊1,用於電性連接積體電路晶片4和焊墊1的金屬線3,以及封裝所述積體電路晶片4、引線框架2、焊墊1和金屬線3的封裝體5。所述積體電路晶片4固定安裝在引線框架2上。所述焊墊1圍繞積體電路晶片4設置,包括電性連接在一起的不可切割焊墊12和可切割焊墊11。不可切割焊墊12借助金屬線3電性連接積體電路晶片4。可切割焊墊11由不可切割焊墊12向封裝體5外部方向延伸。被封裝體5封裝的焊墊1至少有一能夠被QFN外的電氣元件電性接觸的導電觸點。雖然構成QFN大板8的每個QFN 7都有各自的封裝體5,實質上各QFN 7的封裝體5都連接成一個整體。從實現製程上,應當將各引線框架2按預先設計的結構佈設,分別固定安裝積體電路晶片,將焊墊1圍繞各自所在QFN 7的積體電路晶片4設置並完成金屬線3的電性連接,最後以QFN大板8為單位,通過封裝體5的封裝製程一次性對所有QFN 7的積體電路晶片4、引線框架2、焊墊1和金屬線3進行整體封裝而製成QFN大板8。Based on the above solution of the present invention, a square flat pinless package QFN 7 that can be cut is shown in FIG. 3. The present invention also provides a square flat pinless package QFN large board 8 that can be cut, including a tiled package. At least two square flat contactless packages QFN 7 in a plate-shaped unit. Tiled package refers to the packaging structure formed by laying QFN 7 on the same reference plane and laying adjacent to each other. As shown in FIGS. 1 and 2, the QFN 7 includes at least one integrated circuit chip 4, a lead frame 2, at least one bonding pad 1, a metal wire 3 for electrically connecting the integrated circuit chip 4 and the bonding pad 1, and A package 5 that packages the integrated circuit wafer 4, the lead frame 2, the bonding pads 1 and the metal wires 3. The integrated circuit chip 4 is fixedly mounted on the lead frame 2. The solder pad 1 is disposed around the integrated circuit wafer 4 and includes an uncuttable solder pad 12 and a dicable solder pad 11 which are electrically connected together. The non-cuttable bonding pad 12 is electrically connected to the integrated circuit chip 4 through a metal wire 3. The dicing pad 11 extends from the non-cutting pad 12 to the outside of the package 5. At least one of the bonding pads 1 encapsulated by the package body 5 can be electrically contacted by electrical components outside the QFN. Although each QFN 7 constituting the QFN large board 8 has its own package 5, the package 5 of each QFN 7 is substantially connected as a whole. From the realization process, each lead frame 2 should be arranged according to a pre-designed structure, and the integrated circuit chip should be fixedly installed, and the bonding pad 1 should be set around the integrated circuit chip 4 of the QFN 7 and the electrical property of the metal wire 3 should be completed. Connect, and finally use the QFN large board 8 as a unit to package all the QFN 7 integrated circuit wafers 4, lead frames 2, pads 1 and metal wires 3 at a time through the packaging process of the package 5 to make a QFN large Plate 8.

現有技術QFN由於不可切割,採用QFN的積體電路晶片都製造成單片,用設置有晶片固定槽位元的托盤包裝,該托盤也被稱為Tray盤。而本發明QFN能夠被切割,可以被製成圖3所示更易於包裝運輸的QFN大板8。由於QFN大板8一次封裝即可形成多個QFN 7,製程實現相對于現有技術更容易,成本更低。本發明較佳實施例,如圖3所示,將QFN 7按陣列結構佈設,圖3所示QFN大板8將12片QFN 7按3列4行的陣列佈設,由使用者根據需要對QFN大板8進行切割而獲得符合用戶定制需求的單片積體電路晶片,不僅較現有技術節省了包裝成本,還利於滿足用戶的客製化需求。上述對於QFN 7的具體實現方案都適用於構成QFN大板8的QFN7,此處不再贅述。Due to the inability to cut the prior art QFN, the integrated circuit wafers using QFN are manufactured as a single piece, and are packaged in a tray provided with a wafer fixed slot, which is also called a Tray disk. The QFN of the present invention can be cut, and can be made into a QFN board 8 as shown in FIG. 3 which is easier to package and transport. Since the QFN large board 8 can form multiple QFNs 7 in a single package, the process realization is easier and the cost is lower than the existing technology. In the preferred embodiment of the present invention, as shown in FIG. 3, QFN 7 is arranged in an array structure. The QFN large board 8 shown in FIG. 3 is arranged with 12 QFN 7 in an array of 3 columns and 4 rows. The large board 8 is cut to obtain a single-chip integrated circuit wafer that meets user-customized requirements, which not only saves packaging costs compared to the prior art, but also helps meet user-customized needs. The above specific implementation solutions for QFN 7 are applicable to the QFN 7 constituting the QFN large board 8, and are not repeated here.

基於上述封裝結構,本發明還提出一種使方形扁平無接腳封裝QFN能夠被切割的方法,所述QFN 7包括至少一積體電路晶片4,能夠固定安裝積體電路晶片4的引線框架2,至少一焊墊1,用於電性連接積體電路晶片4和焊墊1的金屬線3,以及封裝所述積體電路晶片4、引線框架2、焊墊1和金屬線3的封裝體5。所述使QFN能夠被切割的方法是,為焊墊1設置可切割焊墊11和不可切割焊墊12。將焊墊1圍繞積體電路晶片4設置,不可切割焊墊12借助金屬線3電性連接積體電路晶片4。可切割焊墊11由不可切割焊墊12向封裝體5外部方向延伸,借助可切割焊墊11獲得QFN的可切割區域。使封裝後的焊墊1至少有一能夠被QFN外的電氣元件電性接觸的導電觸點。Based on the above-mentioned packaging structure, the present invention also proposes a method for enabling a square flat pinless package QFN to be cut. The QFN 7 includes at least one integrated circuit chip 4 and a lead frame 2 capable of fixedly mounting the integrated circuit chip 4. At least one bonding pad 1, a metal wire 3 for electrically connecting the integrated circuit chip 4 and the bonding pad 1, and a package 5 encapsulating the integrated circuit chip 4, the lead frame 2, the bonding pad 1 and the metal wire 3 . The method for enabling the QFN to be cut is to provide a dicing pad 11 and a non-cutting pad 12 for the bonding pad 1. The solder pad 1 is disposed around the integrated circuit wafer 4, and the non-cuttable solder pad 12 is electrically connected to the integrated circuit wafer 4 through the metal wire 3. The dicing pad 11 extends from the non-cutting pad 12 to the outside of the package 5, and the dicable area of the QFN is obtained by means of the dicing pad 11. The packaged solder pad 1 has at least one conductive contact capable of being electrically contacted by an electrical component outside the QFN.

1‧‧‧焊墊1‧‧‧ pad

2‧‧‧引線框架 2‧‧‧lead frame

3‧‧‧金屬線 3‧‧‧ metal wire

4‧‧‧積體電路晶片 4‧‧‧Integrated Circuit Chip

5‧‧‧封裝體 5‧‧‧ Package

6‧‧‧晶粒粘合膜 6‧‧‧ Grain Adhesive Film

7‧‧‧QFN 7‧‧‧QFN

8‧‧‧QFN大板 8‧‧‧QFN large board

11‧‧‧可切割焊墊 11‧‧‧ Cuttable pads

111‧‧‧導電觸點 111‧‧‧ conductive contacts

12‧‧‧不可切割焊墊 12‧‧‧Uncutable Pad

121‧‧‧導電觸點 121‧‧‧ conductive contacts

21‧‧‧內框架 21‧‧‧Inner frame

22‧‧‧外框架 22‧‧‧ Outer frame

23‧‧‧連接筋 23‧‧‧ Connecting rib

C1~C5‧‧‧邊界 C1 ~ C5‧‧‧ border

A-A、e、s‧‧‧方向 A-A, e, s‧‧‧ directions

圖1是本發明方形扁平無接腳封裝及使其能夠被切割的方法之一較佳實施例的正投影主視示意圖;FIG. 1 is a schematic front view of a square flat pinless package according to the present invention and a method for enabling it to be cut;

圖2是圖1所標A-A方向剖視示意圖; 2 is a schematic cross-sectional view in the direction of A-A marked in FIG. 1;

圖3是所述較佳實施例製成的方形扁平無接腳封裝QFN大板8的正投影主視示意圖。 FIG. 3 is a schematic front view of a square flat pinless package QFN large board 8 made by the preferred embodiment.

無。no.

Claims (6)

一種能夠被切割的方形扁平無接腳封裝,包括: 至少一積體電路晶片,引線框架,至少一焊墊,用於電性連接積體電路晶片和焊墊的金屬線,以及封裝該積體電路晶片、引線框架、焊墊和金屬線的封裝體; 該積體電路晶片固定安裝在引線框架上; 該焊墊圍繞積體電路晶片設置,包括電性連接在一起的不可切割焊墊和可切割焊墊;不可切割焊墊借助金屬線電性連接積體電路晶片;可切割焊墊由不可切割焊墊向封裝體外部方向延伸;以及 被封裝體封裝的焊墊至少有一能夠被封裝外的電氣元件電性接觸的導電觸點。A square flat pinless package that can be cut, including: At least one integrated circuit chip, lead frame, at least one solder pad, metal wires for electrically connecting the integrated circuit chip and solder pad, and a package for packaging the integrated circuit chip, lead frame, solder pad, and metal wire ; The integrated circuit chip is fixedly mounted on the lead frame; The solder pad is arranged around the integrated circuit chip, including an uncuttable pad and a dicable pad which are electrically connected together; the non-cuttable pad is electrically connected to the integrated circuit chip by means of a metal wire; The pad extends toward the outside of the package; and At least one of the bonding pads encapsulated by the package body can be electrically contacted by electrical components outside the package. 如請求項1所述之能夠被切割的方形扁平無接腳封裝,其中該焊墊設置的位置使可切割焊墊未連接不可切割焊墊的端部沿著矩形的封裝邊界設置。The square flat pinless package capable of being cut as described in claim 1, wherein the pad is disposed at a position where the end of the cuttable pad not connected to the non-cuttable pad is disposed along the rectangular package boundary. 如請求項1或者2所述之能夠被切割的方形扁平無接腳封裝,其中封裝的最小切割邊界是能夠使不可切割焊墊不被切割的最小環形。The square flat pinless package that can be cut as described in claim 1 or 2, wherein the minimum cutting boundary of the package is the smallest ring shape that can prevent the uncut pads from being cut. 如請求項3所述之能夠被切割的方形扁平無接腳封裝,其中不可切割焊墊與可切割焊墊連接點沿著矩形邊線圍成的佈設邊界設置,封裝的最小切割邊界就是該矩形邊線圍成的佈設邊界。The square flat, pinless package that can be cut as described in claim 3, wherein the connection point of the non-cuttable pad and the cuttable pad is set along a rectangular border line, and the minimum cutting boundary of the package is the rectangular border line A bounding layout. 如請求項3所述之能夠被切割的方形扁平無接腳封裝,其中不可切割焊墊與可切割焊墊連接點沿著矩形邊線圍成的佈設邊界設置,封裝的最小切割邊界是將所有不可切割焊墊圍在其中、且至少與兩不可切割焊墊邊緣內接的圓周線邊界。The square flat, pinless package that can be cut as described in claim 3, wherein the connection points of the uncuttable pads and the cuttable pads are set along a rectangular border line. The minimum cutting boundary of the package is to The cutting pad is enclosed by a circumferential line boundary which is at least inscribed with the edges of the two non-cutting pads. 如請求項1或者2所述之能夠被切割的方形扁平無接腳封裝,其中可切割焊墊向封裝體外延伸的延伸方向與封裝能夠被切割的切割方向的夾角大於0度且小於180度。The square flat pinless package capable of being cut as described in claim 1 or 2, wherein the included angle between the extending direction of the dicing pad extending outside the package and the cutting direction where the package can be cut is greater than 0 degrees and less than 180 degrees.
TW108116277A 2018-05-16 2019-05-10 Quad flat non-lead package and method for enabling it to be cut which can meet the user's customized requirement for the integrated circuit chip package with sensors and improve the adaptability of QFN and terminal TW201947723A (en)

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