KR100355797B1 - semiconductor package and its manufacturing method - Google Patents
semiconductor package and its manufacturing method Download PDFInfo
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- KR100355797B1 KR100355797B1 KR1019990044645A KR19990044645A KR100355797B1 KR 100355797 B1 KR100355797 B1 KR 100355797B1 KR 1019990044645 A KR1019990044645 A KR 1019990044645A KR 19990044645 A KR19990044645 A KR 19990044645A KR 100355797 B1 KR100355797 B1 KR 100355797B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
이 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 칩아웃(chip out) 현상을 억제하여 본딩 영역을 보호함은 물론 습기침투를 예방할 수 있도록, 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착된 칩탑재판과; 상기 칩탑재판의 모서리에서 외측으로 연장된 다수의 타이바와; 상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 내부리드와; 상기 반도체칩의 입출력패드와 내부리드를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 봉지재로 봉지하되, 상기 칩탑재판 및 내부리드의 저면과 측면은 외부로 노출되도록 봉지하여 형성된 패키지몸체로 이루어진 반도체패키지에 있어서, 상기 패키지몸체는 각각의 타이바 단부가 위치하는 모서리에 챔퍼가 형성된 것을 특징으로 함.The present invention relates to a semiconductor package and a method for manufacturing the same, comprising: a semiconductor chip having a plurality of input / output pads formed thereon to prevent chip out and protect a bonding area, and to prevent moisture infiltration; A chip mounting plate adhered to the bottom of the semiconductor chip with an adhesive; A plurality of tie bars extending outward from an edge of the chip mounting plate; A plurality of internal leads formed at a predetermined distance apart from an outer circumference of the chip mounting plate; Conductive wires electrically connecting the input / output pads and the internal leads of the semiconductor chip; In the semiconductor package comprising a package body formed by encapsulating the semiconductor chip, the conductive wire, the chip mounting plate and the inner lead with an encapsulant, the bottom and side surfaces of the chip mounting plate and the inner lead is exposed to the outside. The package body is characterized in that the chamfer is formed at the corner where each tie bar end is located.
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 칩아웃(chip out) 현상을 억제하여, 본딩 영역을 보호함은 물론 습기침투를 예방할 수 있는 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same, which can prevent chip out phenomena, protect bonding areas, and prevent moisture penetration. will be.
최근의 전자기기 예를 들면, 휴대폰, 셀룰러 폰, 노트북 등의 마더보드에는 많은 수의 반도체칩들이 패키징되어 최소시간내에 그것들이 다기능을 수행할 수 있도록 설계되는 동시에, 전자기기 자체가 초소형화 되어가는 추세에 있다. 이에 따라 반도체칩이 고집적화됨은 물론, 이를 패키징한 반도체패키지의 크기도 축소되고 있으며, 또한 실장밀도도 고밀도화되어 가고 있다.In modern electronic devices such as mobile phones, cellular phones, and notebooks, a large number of semiconductor chips are packaged and designed so that they can perform multifunction in a minimum amount of time. There is a trend. As a result, semiconductor chips are not only highly integrated, but also the size of the semiconductor package packaged therein is also being reduced, and the packaging density is also becoming higher.
이러한 추세에 따라 최근에는 반도체칩의 전기적 신호를 마더보드로 전달해줌은 물론 마더보드(mother board) 상에서 일정한 형태로 지지되도록 하는 반도체패키지의 크기가 대략 1×1mm ~ 10×10mm 내외로 개발되고 있으며, 이러한 반도체패키지의 예로서 MLF(Micro LeadFrame)형 패키지 등이 알려져 있다.Recently, the size of the semiconductor package that delivers electrical signals of semiconductor chips to the motherboard and is supported on the motherboard (mother board) in a certain shape has been developed to about 1 × 1mm ~ 10 × 10mm. As examples of such semiconductor packages, MLF (Micro LeadFrame) packages and the like are known.
여기서 상기 MLF형 반도체패키지(100')를 도1a 및 도1b에 도시하였다.The MLF type semiconductor package 100 'is shown in FIGS. 1A and 1B.
도시된 바와 같이 상면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면에는 접착제로 칩탑재판(4)이 접착되어 있다. 상기 칩탑재판(4)은 측면 둘레에 할프에칭부(4a)가 형성되어 있고 모서리에는 외측으로 연장되고 역시 할프에칭부(도시되지 않음)가 구비된 타이바(28)가 형성되어 있다. 상기 칩탑재판(4)의 외주연에는 방사상으로 배열되어 있으며 칩탑재판(4)을 향하는 단부에 할프에칭부(6a)가 형성된 다수의 내부리드(6)가 구비되어 있다. 상기 반도체칩(2)의 입출력패드(2a)와 내부리드(6)는 도전성와이어(8)에 의해 서로 전기적으로 접속되어 있다. 계속해서 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4) 및 내부리드(6)는 봉지재로 봉지되어 소정의 패키지몸체(10)를 형성하고 있으며, 상기 칩탑재판(4), 내부리드(6) 및 타이바(28)의 저면은 패키지몸체(10) 저면으로 노출되어 있다.As shown in the drawing, a semiconductor chip 2 having a plurality of input / output pads 2a formed thereon is provided, and a chip mounting plate 4 is attached to the bottom of the semiconductor chip 2 with an adhesive. The chip mounting plate 4 has a half etched portion 4a formed around the side, and a tie bar 28 extending outward at the corner and also provided with a half etched portion (not shown). The outer periphery of the chip mounting plate 4 is provided with a plurality of inner leads 6 which are arranged radially and have a half etching portion 6a formed at the end facing the chip mounting plate 4. The input / output pad 2a and the inner lead 6 of the semiconductor chip 2 are electrically connected to each other by conductive wires 8. Subsequently, the semiconductor chip 2, the conductive wire 8, the chip mounting plate 4 and the inner lead 6 are sealed with an encapsulant to form a predetermined package body 10. The chip mounting plate ( 4), the bottoms of the inner leads 6 and the tie bars 28 are exposed to the bottom of the package body 10.
한편, 상기와 같은 반도체패키지(100')의 제조 방법을 간단히 설명하면 다음과 같으며, 여기서는 도3a 내지 도3c를 참조하여 싱귤레이션 공정을 중심으로 설명한다.Meanwhile, the method of manufacturing the semiconductor package 100 ′ as described above will be briefly described as follows. Here, with reference to FIGS. 3A to 3C, the singulation process will be described.
먼저, 대략 판상의 프레임몸체(22)와, 상기 프레임몸체(22)의 모서리에서 내측으로 연장된 다수의 타이바(28)와, 상기 타이바(28)에 연결되어 차후 반도체칩(2)이 탑재되는 칩탑재판(4)과, 상기 칩탑재판(4)의 외주연에 일정거리 이격되어 방사상으로 형성된 다수의 내부리드(6)와, 상기 내부리드(6)에 연장되어 다시 프레임몸체(22)에 연결되는 외부리드(26) 및 상기 내부리드(6)와 외부리드(26) 사이에 형성되어 프레임몸체(22)에 연결되는 댐바(24)로 이루어진 리드프레임(20)을 구비한다.First, a substantially plate-shaped frame body 22, a plurality of tie bars 28 extending inwardly from the edge of the frame body 22, and the tie bars 28 are connected to the semiconductor chip 2 afterwards. The chip mounting plate 4 to be mounted, a plurality of inner leads 6 radially spaced apart from the outer periphery of the chip mounting plate 4, and extended to the inner lead 6, and again frame body ( And a lead frame 20 formed between an outer lead 26 connected to the 22 and a dam bar 24 formed between the inner lead 6 and the outer lead 26 and connected to the frame body 22.
여기서 상기 칩탑재판(4)의 측면 둘레, 상기 칩탑재판(4)을 향하는내부리드(6)의 단부 및 상기 칩탑재판(4)에 인접하는 타이바(28) 영역에는 할프에칭부(4a,6a)를 형성한다.Here, a half-etching portion is formed at a periphery of the side of the chip mounting plate 4, an end portion of the inner lead 6 facing the chip mounting plate 4, and an area of the tie bar 28 adjacent to the chip mounting plate 4. 4a, 6a).
이어서, 상기 리드프레임(20)의 칩탑재판(4)에 양품의 반도체칩(2)을 접착제로 접착한다.Subsequently, a good semiconductor chip 2 is bonded to the chip mounting plate 4 of the lead frame 20 with an adhesive.
이어서, 상기 반도체칩(2)의 입출력패드(2a)와 리드프레임(20)의 내부리드(6)를 골드와이어나 알루미늄와이어 등의 도전성와이어(8)를 이용하여 전기적으로 접속한다.Next, the input / output pad 2a of the semiconductor chip 2 and the inner lead 6 of the lead frame 20 are electrically connected using conductive wires 8 such as gold wires or aluminum wires.
이어서, 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4), 내부리드(6) 등을 봉지재로 봉지하여 패키지몸체(10)를 형성하되, 상기 칩탑재판(4)과 내부리드(6)의 저면 및 측면은 패키지몸체(10) 외측으로 노출되도록 한다. 이때, 상기 칩탑재판(4), 내부리드(6) 및 패키지몸체(10)의 저면은 동일평면이 되도록 하며, 상기 내부리드(6)의 상면 일부가 패키지몸체(10) 외측으로 노출될 수도 있다.Subsequently, the package body 10 is formed by encapsulating the semiconductor chip 2, the conductive wire 8, the chip mounting plate 4, the inner lead 6, and the like with an encapsulant, and the chip mounting plate 4 The bottom and side surfaces of the inner lead 6 are exposed to the outside of the package body 10. At this time, the bottom surface of the chip mounting plate 4, the inner lead 6 and the package body 10 to be the same plane, a portion of the upper surface of the inner lead 6 may be exposed to the outside of the package body (10). have.
상기와 같은 공정을 완료하면 도2a에 도시된 형상으로 되며, 이후에는 리드프레임(20)에서 낱개의 반도체패키지(100')로 싱귤레이션하는 공정에 리드프레임(20)이 투입된다.When the above process is completed, the shape shown in FIG. 2A is obtained. After that, the lead frame 20 is introduced into a process of singulating the lead frame 20 into individual semiconductor packages 100 '.
상기 싱귤레이션 공정은 상기 리드프레임(20)을 바텀클램프 및 탑클램프에 의해 클램핑한 상태에서 펀치 등을 이용하여 댐바(24), 내부리드(6)와 외부리드(26)의 경계 영역, 타이바(28) 및 봉지재로 감싸여져 형성된 패키지몸체(10)를 동시에 싱귤레이션함으로써 이루어진다.In the singulation process, the lead frame 20 is clamped by the bottom clamp and the top clamp, using a punch or the like, and a boundary area between the inner lead 6 and the outer lead 26 and a tie bar. It is made by singulation of the package body 10 formed by being wrapped with 28 and the sealing material at the same time.
이때, 상기 싱귤레이션 공정은 도2b에 도시된 바와 같이 먼저 2개의 X축 방향에 위치된 댐바(24), 내부리드(6)와 외부리드(26)의 경계 영역, 타이바(28) 및 패키지몸체(10)를 동시에 싱귤레이션한다.In this case, as illustrated in FIG. 2B, first, the dam bar 24 located in two X-axis directions, the boundary region between the inner lead 6 and the outer lead 26, the tie bar 28 and the package are shown in FIG. 2B. The body 10 is singulated at the same time.
그런후, 도2c에 도시된 바와 같이 2개의 Y축 방향에 위치된 댐바(24), 내부리드(6)와 외부리드(26)의 경계 영역, 타이바(28) 및 패키지몸체(10)를 동시에 싱귤레이션함으로써, 총2회에 걸쳐 이루어진다.Then, as shown in Fig. 2C, the dam bar 24 located in two Y-axis directions, the boundary region between the inner lead 6 and the outer lead 26, the tie bar 28 and the package body 10 are removed. By the singulation at the same time, a total of two times.
경우에 따라서 상기 싱귤레이션 공정을 1회로 즉, 모든 댐바(24), 모든 내부리드(6)와 외부리드(26)의 경계 영역, 패키지몸체(10) 등을 동시에 싱귤레이션하는 경우도 있다. 상기와 같은 싱귤레이션 공정이 완료된 후에는 도1b에 도시된 것과 같은 반도체패키지(100')가 얻어지며, 그 평면 형상은 대략 사각형 모양을 한다.In some cases, the singulation process is performed in one circuit, that is, all the dam bars 24, the boundary regions of all the inner leads 6 and the outer leads 26, the package body 10, and the like are simultaneously singulated. After the above singulation process is completed, the semiconductor package 100 ′ as shown in FIG. 1B is obtained, and the planar shape thereof has a substantially rectangular shape.
그러나, 상기와 같은 구조 및 제조 방법(또는 싱귤레이션 공정)에 의해 제조된 반도체패키지는 다음과 같은 문제점을 가지고 있다.However, the semiconductor package manufactured by the above structure and manufacturing method (or singulation process) has the following problems.
싱귤레이션 공정시 리드프레임이 2개의 X축 방향과 2개의 Y축 방향으로 각 1회씩, 총 2회에 걸쳐 싱귤레이션됨으로써, 사각 모서리에 위치한 타이바에 과도한 스트레스가 작용하여 그 타이바 근처의 패키지몸체에서 심각한 칩아웃 현상이 유발된다. 즉, 상기 싱귤레이션되는 타이바 근처의 패키지몸체가 크랙되거나 또는 일부가 떨어져 나감으로써 패키지몸체 외측으로 타이바의 측면이 노출되거나 또는 도전성와이어가 패키지몸체 외측으로 노출되는 경우도 있다. 이러한 칩아웃 현상은 내부리드 단부 근처에서도 자주 발생되며, 또한 상기 칩아웃된 부분으로는 수분이 침투되기 쉬어 반도체패키지의 신뢰성을 크게 저하시키는 문제점이 있다.During the singulation process, the lead frame is singulated twice each, once in the two X-axis and two Y-axis directions, so that excessive stress is applied to the tie bar located at the corners of the package and the package body near the tie bar is Severe chip-out occurs at That is, the side of the tie bar may be exposed to the outside of the package body or the conductive wire may be exposed to the outside of the package body by cracking or partially detaching the package body near the singulated tie bar. Such a chip out phenomenon occurs frequently near the inner lead end, and also has a problem in that the moisture is easily penetrated into the chip out portion, thereby greatly reducing the reliability of the semiconductor package.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 칩아웃 현상을 억제하여, 본딩 영역을 보호함은 물론 습기침투를 예방할 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and to provide a semiconductor package and a method of manufacturing the same, which can prevent chip out phenomenon, protect the bonding area and prevent moisture penetration.
도1a 및 도1b는 종래의 반도체패키지를 도시한 단면도 및 저면도이다.1A and 1B are a cross-sectional view and a bottom view showing a conventional semiconductor package.
도2a 내지 도2c는 종래 반도체패키지의 제조 방법중 싱귤레이션 공정을 도시한 저면도이다.2A to 2C are bottom views illustrating a singulation process in a conventional method for manufacturing a semiconductor package.
도3a 및 도3b는 본 발명에 의한 반도체패키지를 도시한 단면도 및 저면도이다.3A and 3B are a cross-sectional view and a bottom view showing a semiconductor package according to the present invention.
도4a 내지 도4c는 본 발명에 의한 반도체패키지의 제조 방법중 싱귤레이션 공정을 도시한 저면도이다.4A to 4C are bottom views illustrating a singulation process in a method of manufacturing a semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100; 반도체패키지 2; 반도체칩100; Semiconductor package 2; Semiconductor chip
2a; 입출력패드 4; 칩탑재판2a; Input / output pad 4; Chip board
4a; 칩탑재판의 할프에칭부 6; 내부리드4a; Half etching part 6 of a chip mounting board; Internal lead
6a; 내부리드의 할프에칭부 8; 도전성와이어6a; Half etching portion 8 of the inner lead; Conductive Wire
10; 패키지몸체 12; 챔퍼10; Package body 12; Chamfer
20; 리드프레임 22; 프레임몸체20; Leadframe 22; Frame
24; 댐바 26; 외부리드24; Dambar 26; External lead
28; 타이바 A; 1차 싱귤레이션 부분28; Tie bar A; Primary singulation section
B; 2차 싱귤레이션 부분 C; 3차 싱귤레이션 부분B; Secondary singulation portion C; 3rd singulation part
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착된 칩탑재판과; 상기 칩탑재판의 모서리에서 외측으로 연장된 다수의 타이바와; 상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 내부리드와; 상기 반도체칩의 입출력패드와 내부리드를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 봉지재로 봉지하되, 상기 칩탑재판 및 내부리드의 저면과 측면은 외부로 노출되도록 봉지하여 형성된 패키지몸체로 이루어진 반도체패키지에 있어서, 상기 패키지몸체는 각각의 타이바 단부가 위치하는 모서리에 챔퍼가 형성된 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention comprises a semiconductor chip having a plurality of input and output pads; A chip mounting plate adhered to the bottom of the semiconductor chip with an adhesive; A plurality of tie bars extending outward from an edge of the chip mounting plate; A plurality of internal leads formed at a predetermined distance apart from an outer circumference of the chip mounting plate; Conductive wires electrically connecting the input / output pads and the internal leads of the semiconductor chip; In the semiconductor package comprising a package body formed by encapsulating the semiconductor chip, the conductive wire, the chip mounting plate and the inner lead with an encapsulant, the bottom and side surfaces of the chip mounting plate and the inner lead is exposed to the outside. The package body is characterized in that a chamfer is formed at the corner where each tie bar end is located.
여기서, 상기 패키지몸체의 각 모서리에도 챔퍼가 형성되어 있다.Here, the chamfer is formed in each corner of the package body.
또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 대략 판상의 프레임몸체와, 상기 프레임몸체의 모서리에서 내측으로 연장된 다수의 타이바와, 상기 타이바에 연결되어 차후 반도체칩이 탑재되는 칩탑재판과, 상기 칩탑재판의 외주연에 일정거리 이격되어 방사상으로 형성된 다수의 내부리드와, 상기 내부리드에 연장되어 다시 프레임몸체에 연결되는 외부리드 및 상기 내부리드와 외부리드 사이에 형성되어 프레임몸체에 연결되는 댐바로 이루어진 리드프레임을 구비하는 단계와; 상기 칩탑재판에 반도체칩을 접착제로 접착하는 단계와; 상기 반도체칩의 입출력패드와 리드프레임의 내부리드를 전기적으로 접속하는 단계와; 상기 반도체칩, 도전성와이어, 칩탑재판, 내부리드 등을 봉지재로 봉지하되, 상기 칩탑재판과 내부리드의 저면 및 측면은 외부로 노출되도록 봉지하여 패키지몸체를 형성하는 단계와; 상기 리드프레임으로부터 반도체패키지를 분리하는 싱귤레이션 단계로 이루어진 반도체패키지의 제조 방법에 있어서, 상기 싱귤레이션 단계는 리드프레임에서 칩탑재판을 지지하는 각각의 타이바 및 패키지몸체를 상기 타이바의 길이 방향에 대해 수직 방향으로 절단하는 단계와; 상기 리드프레임에서 2개의 X축 방향에 위치된 댐바, 내부리드와 외부리드의 경계 영역을 절단하는 단계와; 상기 리드프레임에서 2개의 Y축 방향에 위치된 댐바, 내부리드와 외부리드의 경계 영역을 절단하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention in order to achieve the above object is a substantially plate-shaped frame body, a plurality of tie bars extending inwardly from the corner of the frame body, and is connected to the tie bars and subsequently mounted semiconductor chip A chip mounting plate which is spaced apart from the outer periphery of the chip mounting plate by a plurality of inner leads formed radially, and an outer lead extending to the inner lead and connected to the frame body again between the inner lead and the outer lead. Forming a lead frame formed of a dam bar connected to the frame body; Adhering a semiconductor chip to the chip mounting plate with an adhesive; Electrically connecting the input / output pad of the semiconductor chip and the inner lead of the lead frame; Encapsulating the semiconductor chip, the conductive wire, the chip mounting plate, and the inner lead with an encapsulant, wherein the bottom and side surfaces of the chip mounting plate and the inner lead are exposed to the outside to form a package body; In the method of manufacturing a semiconductor package comprising a singulation step of separating the semiconductor package from the lead frame, the singulation step is a tie bar and a package body for supporting the chip mounting plate in the lead frame in the longitudinal direction of the tie bar Cutting in a direction perpendicular to the; Cutting a boundary area between two dam bars, an inner lead and an outer lead positioned in two X-axis directions of the lead frame; And cutting the boundary regions of the dam bars, the inner leads and the outer leads positioned in two Y-axis directions in the lead frame.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 싱귤레이션 공정시 리드프레임이 총 3회에 걸쳐 싱귤레이션됨으로써, 즉 모든 타이바 영역 및 그 근처의 패키지몸체가 1차로 절단되고, 2개의 X축 방향인 댐바, 내부리드와 외부리드의 경계 영역 및 패키지몸체가 2차로 절단되며, 2개의 Y축 방향인 댐바, 내부리드와 외부리드의 경계 영역 및 패키지몸체가 3차로 절단됨으로써, 패키지몸체의 평면 모양이 사각의 네모서리에 챔퍼가 형성된 형태로 되고, 또한 상기와 같은 공정에 의해 상기 네모서리 부분의 칩아웃이 억제된다. 또한 3회에 걸쳐 싱귤레이션됨으로써 내부리드 근처에서도 칩아웃이 억제되며, 결국 상기와 같은 칩아웃의 억제는 와이어본딩영역을 보호함은 물론 수분침투 현상도 억제하게 된다.As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, the lead frame is singulated three times in total during the singulation process, that is, all tie bars and the package body in the vicinity thereof are cut first. The dam bar in two X-axis directions, the boundary region of the inner lead and the outer lead and the package body are cut secondarily, and the dam bar in the two Y-axis directions, the boundary region of the inner lead and the outer lead and the package body is cut third, The planar shape of the package body has a form in which a chamfer is formed in a square corner, and chipout of the corner portion is suppressed by the above process. In addition, since the singulation is performed three times, the chipout is suppressed even near the inner lead. As a result, the suppression of the chipout not only protects the wire bonding area, but also suppresses moisture penetration.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도3a 및 도3b는 본 발명에 의한 반도체패키지(100)를 도시한 단면도 및 저면도이다.3A and 3B are a cross-sectional view and a bottom view of a semiconductor package 100 according to the present invention.
도시된 바와 같이 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면에는 접착제로 칩탑재판(4)이 접착되어 있다. 또한, 상기 칩탑재판(4)의 네모서리에는 외측을 향해 연장된 타이바(28)가 형성되어 있다. 상기 칩탑재판(4)의 외주연에는 일정거리 이격되어 다수의 내부리드(6)가 방사상으로 형성되어 있다. 상기 반도체칩(2)의 입출력패드(2a)와 내부리드(6)는 골드와이어 또는 알루미늄와이어 등과 같은 도전성와이어(8)에 의해 전기적으로 접속되어 있다. 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4) 및 내부리드(6) 등은 에폭시몰딩컴파운드 또는 액상봉지재와 같은 봉지재로 봉지되어 있되, 상기 칩탑재판(4) 및 내부리드(6)의 저면과 측면은 외부로 노출되도록 봉지되어 패키지몸체(10)를 이루고 있다. 상기 내부리드(6)의 상면 일정영역은 패키지몸체(10) 외측으로 노출될 수도 있다. 이와 같은 구조는 종래와 동일하다.As illustrated, a semiconductor chip 2 having a plurality of input / output pads 2a is provided, and the chip mounting plate 4 is bonded to the bottom of the semiconductor chip 2 with an adhesive. In addition, a tie bar 28 extending outward is formed at the corner of the chip mounting plate 4. On the outer circumference of the chip mounting plate 4, a plurality of inner leads 6 are radially spaced apart by a predetermined distance. The input / output pad 2a and the inner lead 6 of the semiconductor chip 2 are electrically connected by conductive wires 8 such as gold wires or aluminum wires. The semiconductor chip 2, the conductive wire 8, the chip mounting plate 4 and the inner lead 6 are encapsulated with an encapsulant such as an epoxy molding compound or a liquid encapsulant, and the chip mounting plate 4 The bottom and side surfaces of the inner lead 6 are sealed to be exposed to the outside to form a package body 10. A predetermined region of the upper surface of the inner lead 6 may be exposed to the outside of the package body 10. This structure is the same as in the prior art.
다만 본 발명은 상기 패키지몸체(10)의 외측 네모서리 부분에 챔퍼(12)가 형성된 것이 특징이다. 즉, 도3b에 도시된 바와 같이 타이바(28)의 단부가 위치되는 패키지몸체(10)의 모서리 부분에 모두 챔퍼(12)가 형성되어 있다.However, the present invention is characterized in that the chamfer 12 is formed in the outer corner portion of the package body 10. That is, as shown in FIG. 3B, the chamfers 12 are formed in all corner portions of the package body 10 in which the ends of the tie bars 28 are located.
이와 같이 패키지몸체(10)의 사각 모서리에 챔퍼(12)가 형성된반도체패키지(100)의 제조 방법을 설명하면 다음과 같다.As described above, the manufacturing method of the semiconductor package 100 in which the chamfer 12 is formed at the square corners of the package body 10 is as follows.
먼저 대략 판상의 프레임몸체(22)와, 상기 프레임몸체(22)의 모서리에서 내측으로 연장된 다수의 타이바(28)와, 상기 타이바(28)에 연결되어 차후 반도체칩(2)이 탑재되는 칩탑재판(4)과, 상기 칩탑재판(4)의 외주연에 일정거리 이격되어 방사상으로 형성된 다수의 내부리드(6)와, 상기 내부리드(6)에 연장되어 다시 프레임몸체(22)에 연결되는 외부리드(26) 및 상기 내부리드(6)와 외부리드(26) 사이에 형성되어 프레임몸체(22)에 연결되는 댐바(24)로 이루어진 리드프레임(20)을 구비한다. 이때, 상기 칩탑재판(4)의 측면 둘레, 상기 칩탑재판(4)을 향하는 내부리드(6)의 단부 및 타이바(28) 저면에는 할프에칭부(4a,6a)를 각각 형성한다.First, a substantially plate-shaped frame body 22, a plurality of tie bars 28 extending inwardly from the corners of the frame body 22, and connected to the tie bars 28, and then the semiconductor chip 2 is mounted thereon. The chip mounting plate 4 and the plurality of inner leads 6 radially spaced apart from the outer periphery of the chip mounting plate 4 and the inner lead 6 and the frame body 22 again. And a lead frame 20 formed between the outer lead 26 and the inner lead 6 and the outer lead 26 and a dam bar 24 connected to the frame body 22. At this time, half-etching portions 4a and 6a are formed on the side circumference of the chip mounting plate 4, the end of the inner lead 6 facing the chip mounting plate 4, and the bottom of the tie bar 28, respectively.
상기 칩탑재판(4)에 양품의 반도체칩(2)을 접착제로 접착한다.The semiconductor chip 2 of good quality is adhere | attached on the said chip mounting board 4 with an adhesive agent.
상기 반도체칩(2)의 입출력패드(2a)와 리드프레임(20)의 내부리드(6)를 전기적으로 접속한다.The input / output pad 2a of the semiconductor chip 2 and the inner lead 6 of the lead frame 20 are electrically connected.
상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4), 내부리드(6) 등을 봉지재로 봉지하되, 상기 칩탑재판(4)과 내부리드(6)의 저면 및 측면은 외부로 노출되도록 봉지하여 패키지몸체(10)를 형성한다.The semiconductor chip 2, the conductive wire 8, the chip mounting plate 4, and the inner lead 6 are encapsulated with an encapsulant, and the bottom and side surfaces of the chip mounting plate 4 and the inner lead 6 are encapsulated. The encapsulation is exposed to the outside to form a package body (10).
상기 리드프레임(20)으로부터 반도체패키지(100)를 싱귤레이션한다.The semiconductor package 100 is singulated from the lead frame 20.
이상의 단계는 종래와 동일하며, 본 발명의 특징은 상기 싱귤레이션 공정에 있다.The above steps are the same as in the prior art, and the feature of the present invention lies in the singulation process.
즉, 도4a 내지 도4c에 도시된 바와 같이 먼저 리드프레임(20)의 칩탑재판(4)을 지지하는 각각의 타이바(28) 및 패키지몸체(10)를 상기 타이바(28)의 길이 방향에 대해 수직 방향으로 절단한다. 다른 말로 하면 봉지재로 형성된 패키지몸체(10)의 네모서리에 위치된 타이바(28) 및 그 타이바(28) 근처의 패키지몸체(10)를 1차로 제거하되, 상기 타이바(28)의 길이 방향에 대하여 대략 수직한 방향으로 싱귤레이션한다.That is, as shown in FIGS. 4A to 4C, first, the tie bars 28 and the package body 10 supporting the chip mounting plate 4 of the lead frame 20 have the length of the tie bars 28. Cut in the direction perpendicular to the direction. In other words, the tie bar 28 located at the corners of the package body 10 formed of the encapsulant and the package body 10 near the tie bar 28 are first removed, but the tie bar 28 It singulates in a direction approximately perpendicular to the longitudinal direction.
다음으로 상기 리드프레임(20)에서 2개의 X축 방향에 위치된 댐바(24), 내부리드(6)와 외부리드(26)의 경계 영역을 2차로 동시에 싱귤레이션한다.Next, at the lead frame 20, the boundary regions of the dam bars 24, the inner leads 6, and the outer leads 26 positioned in two X-axis directions are simultaneously second-regulated.
계속해서, 상기 리드프레임(20)에서 2개의 Y축 방향에 위치된 댐바(24), 내부리드(6)와 외부리드(26)의 경계 영역을 3차로 동시에 싱귤레이션한다.Subsequently, the boundary regions of the dam bar 24, the inner lead 6, and the outer lead 26 located in two Y-axis directions in the lead frame 20 are simultaneously synchronized in three orders.
여기서 상기 1차,2차 및 3차의 싱귤레이션은 주지된 바와 같이, 패키지몸체(10)가 형성된 리드프레임(20)을 바텀클램프와 탑클램프로 클램핑한 상태에서 소정의 펀치로 펀칭하여 실시된다.Here, the primary, secondary and tertiary singulation is performed by punching the lead frame 20 having the package body 10 with a bottom punch and a top clamp with a predetermined punch, as is well known. .
도면중 미설명 부호 A는 1차 싱귤레이션 부분을, B는 2차 싱귤레이션 부분을, C는 3차 싱귤레이션 부분을 의미한다.In the figure, reference numeral A denotes a primary singulation portion, B denotes a secondary singulation portion, and C denotes a third singulation portion.
상기 X축 방향 및 Y축 방향의 싱귤레이션 순서는 당업자에 의해 순서가 바뀔수도 있으며, 이를 제한하는 것은 아니다.The order of singulation in the X-axis direction and the Y-axis direction may be changed by those skilled in the art, but is not limited thereto.
상기와 같이 싱귤레이션 공정을 3차에 걸쳐 실시하게 되면 도3b에 도시된 바와 같이 패키지몸체(10)의 네모서리 부분에 챔퍼(12)가 형성된 반도체패키지(100)를 얻게 되는 것이다.When the singulation process is performed three times as described above, as shown in FIG. 3B, the semiconductor package 100 having the chamfer 12 formed on the four corners of the package body 10 is obtained.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 싱귤레이션 공정시 리드프레임이 총 3회에 걸쳐 싱귤레이션됨으로써, 즉 모든 타이바 영역 및 그 근처의 패키지몸체가 1차로 절단되고, 2개의 X축 방향인 댐바, 내부리드와 외부리드의 경계 영역 및 패키지몸체가 2차로 절단되며, 2개의 Y축 방향인 댐바, 내부리드와 외부리드의 경계 영역 및 패키지몸체가 3차로 절단됨으로써, 패키지몸체의 평면 모양이 사각의 네모서리에 챔퍼가 형성된 형태로 되고, 또한 상기와 같은 공정에 의해 싱귤레이션 공정시 리드프레임에 가해지는 스트레스가 적절히 분배되어 상기 패키지몸체의 네모서리 부분(챔퍼)에서의 칩아웃이 억제되는 효과가 있다.Therefore, according to the semiconductor package and the manufacturing method thereof according to the present invention, the lead frame is singulated three times in the singulation process, that is, all tie bars and the package body in the vicinity thereof are cut first, and two X The dam bar in the axial direction, the boundary area between the inner lead and the outer lead, and the package body are cut in two steps, and the dam bar in the two Y axis directions, the boundary area between the inner lead and the outer lead and the package body are cut in three ways, thereby Chamfer is formed in the square of the square shape in the flat shape, and the stress applied to the lead frame during the singulation process by the above-described process is appropriately distributed, so that the chip out at the corners (chamfers) of the package body. This has the effect of being suppressed.
또한, 상기와 같이 싱귤레이션 공정시 스트레스가 적절히 분배됨으로써 내부리드 근처에서도 칩아웃 현상이 억제되며, 결국 상기와 같은 칩아웃의 억제는 와이어본딩영역을 보호함은 물론 수분침투 현상도 억제하는 효과가 있다.In addition, since the stress is properly distributed during the singulation process as described above, the chip-out phenomenon is suppressed even near the inner lead. As a result, the suppression of the chip-out may not only protect the wire bonding area but also suppress the moisture penetration. have.
Claims (3)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990044645A KR100355797B1 (en) | 1999-10-15 | 1999-10-15 | semiconductor package and its manufacturing method |
| JP2000015004A JP2001077278A (en) | 1999-10-15 | 2000-01-24 | Semiconductor package, lead frame thereof, manufacture of semiconductor package and mold thereof |
| US09/687,049 US6525406B1 (en) | 1999-10-15 | 2000-10-13 | Semiconductor device having increased moisture path and increased solder joint strength |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990044645A KR100355797B1 (en) | 1999-10-15 | 1999-10-15 | semiconductor package and its manufacturing method |
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| KR20010037241A KR20010037241A (en) | 2001-05-07 |
| KR100355797B1 true KR100355797B1 (en) | 2002-10-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9768129B2 (en) | 2015-11-02 | 2017-09-19 | Samsung Electronics Co., Ltd. | Semiconductor device including three-dimensional crack detection structure |
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| CN110391144B (en) * | 2019-07-31 | 2024-03-19 | 江阴康强电子有限公司 | Lead frame production line |
| CN118508116B (en) * | 2024-07-18 | 2024-09-24 | 国网安徽省电力有限公司临泉县供电公司 | Grounding wire clamp structure convenient to hang and detach and grounding wire |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9768129B2 (en) | 2015-11-02 | 2017-09-19 | Samsung Electronics Co., Ltd. | Semiconductor device including three-dimensional crack detection structure |
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