CN201000885Y - Lead wire-free integrated circuit chip encapsulation - Google Patents

Lead wire-free integrated circuit chip encapsulation Download PDF

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Publication number
CN201000885Y
CN201000885Y CN 200620165288 CN200620165288U CN201000885Y CN 201000885 Y CN201000885 Y CN 201000885Y CN 200620165288 CN200620165288 CN 200620165288 CN 200620165288 U CN200620165288 U CN 200620165288U CN 201000885 Y CN201000885 Y CN 201000885Y
Authority
CN
China
Prior art keywords
integrated circuit
chip
interconnection line
circuit chip
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 200620165288
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Chinese (zh)
Inventor
景为平
孙玲
金丽
徐炜炜
孙海燕
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Nantong University
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Nantong University
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Publication date
Application filed by Nantong University filed Critical Nantong University
Priority to CN 200620165288 priority Critical patent/CN201000885Y/en
Application granted granted Critical
Publication of CN201000885Y publication Critical patent/CN201000885Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a integrate circuit chip capsulation without lead wire, which comprises a base plate, a integrate circuit chip, a plurality of bonding wire and a resin bed, the face side and the reverse side of the base plate are respectively distributed a plurality of positive interconnection line and a plurality of inverted interconnection line, the integrate circuit chip is arranged on the face side of the base plate, a bonding pad on the integrate circuit chip is bonding with a goldfinger of one end of the positive interconnection line through the bonding wire, the other end of the positive interconnection line is connected with one end of the corresponding inverted interconnection line through a metalized through hole, the other end of the inverted interconnection line is the bonding pad, the resin bed is sealed on the face side of the base plate and the integrate circuit chip. The utility model has the advantages that the utility model has no need of the lead frame and the professional capsulation equipment, the technological process is simple and easy to achieve, the cost of manufacture is low; the figuration of the capsulation has no pin, thus the chip after the capsulation can has a better frequency characteristic, and the utility model is indicated for the capsulation of a single chip or a plurality of chips.

Description

A kind of leadless integrated circuit Chip Packaging
Technical field
The utility model relates to a kind of leadless integrated circuit Chip Packaging.
Background technology
Integrated circuit encapsulation is laid, fixes, seals, is protected the chip except plaing a part, and also provides current path with the circuit on the drive integrated circult chip, the signal on the distribution integrated circuit (IC) chip, and the heat that produces during with chip operation is taken away.Along with the increase of operating rate, add increasing sharply of low-work voltage and chip pin, electric capacity and inductance parasitic couplings effect increase sharply, and the uncared-for electric effect of some scripts has begun to influence the operate as normal of circuit in the encapsulation.Therefore the requirement of integrated circuit encapsulation is except satisfying basic being electrically connected the function, also wants to solve the problems of Signal Integrity that high frequency/high speed that the development because of the ic core chip technology proposes and number of pins increase cause.
Therefore, integrated circuit encapsulation is increasing to the influence of device performance, and the restriction that the performance of some integrated circuit is subjected to encapsulation technology and the restriction that is subjected to the ic core piece performance are much at one, and be even bigger.The integrated circuit encapsulation is the indivisible part of development of electronic devices, and it relates to multi-disciplinary technology such as material, electronics, heat, mechanics, chemistry, machinery and reliability, more and more receives the extensive attention and the concern of academia and industrial quarters.
The PLCC type that connects is drawn in DIP type, surface-pasted QFP type and Plastic Package side that integrated circuit package type commonly used at present has pin to insert, sees also Fig. 6～8.They all need lead frame, during making chip are placed on the lead frame, and the pad on the chip is connected to the front end of pin by the method for spun gold or aluminium wire bonding, links to each other with external circuit by pin then.DIP type pin 11 is long and thick, has both influenced the frequency characteristic of encapsulation back chip, is difficult for making the encapsulation miniaturization again.Continuous development along with integrated circuit technique, what raising that high frequency/electrical characteristics such as high speed is required and number of pins increased adds, the pin insert type develops into surface attaching type and the type of connecing 12,13 is drawn in the side, and the general weak point of their pin (line) also has frequency characteristic preferably.But because they all need lead frame, for guaranteeing the intensity and the globality of lead frame, each lead-in wire on the framework connects with same metal, must cut off the connecting line of the key that respectively goes between before encapsulation respectively more simultaneously.This will need special equipment on the one hand, increase processing step, can increase the consumption of electric conducting material simultaneously, will inevitably increase production cost.Recently, the BGA type integrated circuit encapsulation that pin is ball grid array occurs, seen also Fig. 9.Though pin shortens greatly and has frequency characteristic preferably, the connection of spherical leg need have special equipment and corresponding process, can make production efficiency reduce cost up relatively equally.
Summary of the invention
The purpose of this utility model is to design a kind of leadless integrated circuit Chip Packaging that a kind of production technology is simple, cost is low and frequency characteristic is good, and it is realized by following technical scheme:
Comprise substrate, integrated circuit (IC) chip, some bonding lines and capping layer, the obverse and reverse that it is characterized in that described substrate is furnished with some positive interconnection lines and anti-interconnection line respectively, integrated circuit (IC) chip places substrate front side, pad on it is by bonding line and positive interconnection line one end golden finger bonding, the other end of positive interconnection line is communicated with pairing anti-interconnection line one end by the metallization via hole, the other end of anti-interconnection line is a pad, and capping layer is sealed on substrate front side and the integrated circuit (IC) chip.
The pad of some anti-interconnection line one ends of some golden fingers of described substrate front side and substrate reverse side distributes in the form of a ring around the integrated circuit (IC) chip periphery.
Two or more independently integrated circuit (IC) chip tile on the described substrate.
Described capping layer preferentially adopts epoxide resin material.
Beneficial effect of the present utility model really is: do not need lead frame, do not need professional sealed in unit, technological process is simple and easy to realize low cost of manufacture; The outline no-lead of encapsulation, the chip after the encapsulation can have better frequency characteristic, is applicable to the encapsulation of single chip even a plurality of chips.
Description of drawings
One of Fig. 1 structural representation of the present utility model.
Fig. 2 substrate front side structure chart.
Fig. 3 substrate reverse side structure chart.
The A-A of Fig. 4 Fig. 1 analyses and observe intention.
Two of Fig. 5 structural representation of the present utility model.
The DIP type integrated circuit (IC) chip encapsulation that Fig. 6 pin inserts.
The encapsulation of the surface-pasted QFP type of Fig. 7 integrated circuit (IC) chip.
Fig. 8 draws the side PLCC type integrated circuit (IC) chip encapsulation that connects.
Fig. 9 pin is the integrated circuit encapsulation of ball grid array.
Among the figure, 1 substrate among the figure, 2 bonding lines, 3 integrated circuit (IC) chip, 4 positive interconnection lines, 5 golden fingers, 6 metallic vias, the pad of 7 substrate reverse side, 8 anti-interconnection lines, 9 epoxy resin capping layers, 10 place chip center's district's 11,12 pins, and 13 outside line pass meet the place, 14 soldered balls,
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is described further.
Contrast Fig. 1, integrated circuit (IC) chip 3 places in the placement chip center district in substrate 1 front, and epoxy resin capping layer 9 is sealed on substrate front side and the integrated circuit (IC) chip 3.
Contrast Fig. 2, the periphery of the front center portion 10 of substrate 1 is distributed with some golden fingers 5, and they surround a straight-flanked ring, and each golden finger 5 connects positive interconnection line 4, and an end of this interconnection line is connected with metallic vias.
Contrast Fig. 3, the reverse side of substrate 1 is distributed with some anti-interconnection lines 8, their end is the pad 7 that is used to connect external circuit, and these pads also surround into a straight-flanked ring on substrate, and the other end of anti-interconnection line 8 is connected with the other end of the metallic vias of passing substrate thickness.
The contrast Fig. 4 with and refer again to Fig. 1, pad on aluminium wire (bonding line 2) the bonding circuit chip 3 and the golden finger on the substrate are electrically connected both.The positive interconnection line of substrate front side is communicated with by the metallic vias 6 that is fixed on the substrate thickness direction with the anti-interconnection line of substrate reverse side.
Contrast Fig. 5, two integrated circuit (IC) chip 3 that can tile on the substrate 1, more polylith chip also can tile.At that time, the circuit of the positive and negative on the substrate 1 (comprising interconnection line 4,8, golden finger 5, pad 7) will be done suitable adjustment, but interconnected relationship is constant.

Claims (4)

1. leadless integrated circuit Chip Packaging, comprise substrate, integrated circuit (IC) chip, some bonding lines and capping layer, the obverse and reverse that it is characterized in that described substrate is furnished with some positive interconnection lines and anti-interconnection line respectively, integrated circuit (IC) chip places substrate front side, pad on it is by bonding line and positive interconnection line one end golden finger bonding, the other end of positive interconnection line is communicated with pairing anti-interconnection line one end by the metallization via hole, the other end of anti-interconnection line is a pad, and capping layer is sealed on substrate front side and the integrated circuit (IC) chip.
2. a kind of leadless integrated circuit Chip Packaging according to claim 1 is characterized in that the some golden fingers of described substrate front side and the pad of some anti-interconnection line one ends of substrate reverse side distribute in the form of a ring around the integrated circuit (IC) chip periphery.
3. a kind of leadless integrated circuit Chip Packaging according to claim 1 is characterized in that two or more independently integrated circuit (IC) chip that tile on the described substrate.
4. a kind of leadless integrated circuit Chip Packaging according to claim 4 is characterized in that described capping layer adopts epoxide resin material.
CN 200620165288 2006-12-25 2006-12-25 Lead wire-free integrated circuit chip encapsulation Expired - Fee Related CN201000885Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200620165288 CN201000885Y (en) 2006-12-25 2006-12-25 Lead wire-free integrated circuit chip encapsulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200620165288 CN201000885Y (en) 2006-12-25 2006-12-25 Lead wire-free integrated circuit chip encapsulation

Publications (1)

Publication Number Publication Date
CN201000885Y true CN201000885Y (en) 2008-01-02

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Country Status (1)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100433322C (en) * 2006-12-25 2008-11-12 南通大学 The encapsulation of integrated circuit chip without lead
CN104795379A (en) * 2015-04-30 2015-07-22 南通大学 Differential coplanar transmission line encapsulation pin inside and outside cascade structure
WO2019072090A1 (en) * 2017-10-11 2019-04-18 爱创达应用卡工程有限公司 Contact ic module pcb carrier, ic module made thereof and manufacturing process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100433322C (en) * 2006-12-25 2008-11-12 南通大学 The encapsulation of integrated circuit chip without lead
CN104795379A (en) * 2015-04-30 2015-07-22 南通大学 Differential coplanar transmission line encapsulation pin inside and outside cascade structure
CN104795379B (en) * 2015-04-30 2017-06-27 南通大学 Cascade structure inside and outside difference coplanar transmission packaging pin
WO2019072090A1 (en) * 2017-10-11 2019-04-18 爱创达应用卡工程有限公司 Contact ic module pcb carrier, ic module made thereof and manufacturing process
CN109661103A (en) * 2017-10-11 2019-04-19 爱创达应用卡工程有限公司 Contact IC module PCB support plate, the module of the IC it made of and manufacture craft

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C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee