CN110223960A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN110223960A
CN110223960A CN201810219248.5A CN201810219248A CN110223960A CN 110223960 A CN110223960 A CN 110223960A CN 201810219248 A CN201810219248 A CN 201810219248A CN 110223960 A CN110223960 A CN 110223960A
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substrate
antenna
supporter
packing piece
electronic packing
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CN110223960B (zh
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陈汉宏
黄俊益
林长甫
林荣政
余国华
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法,通过于具有第一天线布设区的第一基板上形成阻层及支撑体,再将具有第二天线布设区的第二基板压合于该阻层及支撑体上,之后移除该阻层,以借由该支撑体使该第一基板与第二基板之间的距离保持不变,确保该第一天线布设区与第二天线布设区之间的天线传输功能正常。

Description

电子封装件及其制法
技术领域
本发明关于一种电子封装件,特别是关于一种具有天线结构的电子封装件及其制法。
背景技术
目前无线通讯技术已广泛应用于各式各样的消费性电子产品(如手机、平板电脑等),以利接收或发送各种无线讯号,而为满足消费性电子产品的便于携带性及上网便利性(如观看多媒体内容),无线通讯模组的制造与设计朝轻、薄、短、小的需求作开发,其中,平面天线(Patch Antenna)因具有体积小、重量轻与制造容易等特性而广泛利用在电子产品的无线通讯模组中。
目前的多媒体内容因画质的提升而造成其档案资料量变得更大,故无线传输的频宽也需变大,因而产生第五代的无线传输(5G),且5G因传输频率较高,其相关无线通讯模组的尺寸的要求也较高。
如图1所示,其为现有无线通讯模组1的剖面示意图。该无线通讯模组1于设有半导体晶片10的线路板11上侧借由多个焊锡凸块13堆叠一具有第二天线结构(图略)的天线板12,且该线路板11具有接地片(图略)及天线回馈线路(antenna feed lines)(图略),并于该线路板11下方形成多个焊球15,其中,该线路板11与该天线板12之间需于特定区域定义为天线作用区A(即该些焊锡凸块13环绕的区域,其内部不可有点胶或模压填入物),且需控制该线路板11与该天线板12之间的距离L,以确保该天线板12的第二天线结构与该半导体晶片10之间的传接讯号品质;若该距离L不符合所需高度,则该线路板11与该天线板12之间的天线讯号传输将无法准确传输。
此外,现有无线通讯模组1中,因借由该些焊锡凸块13堆叠该线路板11与该天线板12,故该些焊锡凸块13于回焊后的体积及高度的公差大,使该些焊锡凸块13所排列成的栅状阵列(grid array)容易产生共面性(coplanarity)不良,导致接点应力(stress)不平衡而容易造成该线路板11与该天线板12之间呈倾斜接置,导致该线路板11与该天线板12之间的距离L产生变化(如其中一侧变大),因而造成该天线板12的天线功能不良,进而造成产品的良率下降。
因此,如何克服上述现有技术的问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失,本发明提供一种电子封装件及其制法,以确保该第一天线布设区与第二天线布设区之间的天线传输功能正常。
本发明的电子封装件,包括:第一基板,其具有第一天线布设区;支撑体,其设于该第一基板上;以及第二基板,其压合至该支撑体上,使该第一基板与该第二基板借由该支撑体相互堆叠并控制该第一基板与该第二基板之间的距离,且该第二基板具有对应该第一天线布设区的第二天线布设区。
本发明还提供一种电子封装件的制法,包括:形成阻层于一具有第一天线布设区的第一基板上,且该阻层形成有至少一外露部分该第一基板的开口;形成支撑体于该开口中,使该支撑体接触该第一基板;压合一具有第二天线布设区的第二基板于该阻层上,使该第二基板接触该支撑体,其中,该第二基板具有对应该第一天线布设区的第二天线布设区;以及移除该阻层,使该第一基板与该第二基板借由该支撑体相互堆叠。
前述的制法中,构成该阻层的材质为可蚀刻材料。
前述的制法中,该开口未外露该第一天线布设区。
前述的电子封装件及其制法中,该第一天线布设区与该第二天线布设区之间为天线作用区。例如,该天线作用区呈现空旷空间。
前述的电子封装件及其制法中,该构成支撑体的材质为导电材或绝缘材。
前述的电子封装件及其制法中,该支撑体未电性连接该第一天线布设区及/或第二天线布设区。
前述的电子封装件及其制法中,该支撑体未电性连接该第一基板及/或第二基板。
前述的电子封装件及其制法中,该支撑体电性连接该第一基板及/或第二基板。
前述的电子封装件及其制法中,该支撑体上形成有包覆材。
前述的电子封装件及其制法中,还包括设置电子元件于该第一基板上。于一实施例中,该电子元件位于该第一基板与第二基板之间。
由上可知,本发明的电子封装件及其制法中,借由将该第二基板压合至该阻层及支撑体的方式以控制该第一基板与第二基板之间的距离,且令该支撑体堆叠该第一基板与该第二基板,而无需使用焊锡材料,使该第一与第二基板之间的距离几乎保持不变,故相比于现有技术,本发明的电子封装件不会因该第一与第二基板之间的距离变化过大而影响天线功能,因而能避免产品良率下降的问题。
附图说明
图1为现有无线通讯模组的剖面示意图;以及
图2A至图2E为本发明的电子封装件的制法的第一实施例的剖面示意图;
图2C’为图2C的另一实施例;
图2D’为图2D的另一实施例;
图2E’为图2E的另一实施例;以及
图3A至图3C为本发明的电子封装件的制法的第二实施例的剖面示意图。
符号说明:
1 无线通讯模组
10 半导体晶片
11 线路板
12 天线板
13 焊锡凸块
15 焊球
2 电子封装件
20 电子元件
200 导电凸块
21 第一基板
21a 第一表面
21b 第二表面
210 第一天线结构
211 第一线路层
212 第一电性接点
213 植球垫
22 第二基板
220 第二天线结构
221 第二线路层
222 第二电性接点
23,24 支撑体
23c 侧面
25 导电元件
26 开孔
29 阻层
290 开口
390 开口区
30 包覆材
A,S 天线作用区
A1 第一天线布设区
A2 第二天线布设区
H 高度
L,D 距离。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“第一”、“第二”、及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2E为本发明的电子封装件2的制法的第一实施例的剖面示意图。
如图2A所示,提供一第一基板21,其具有相对的第一表面21a与第二表面21b。
于本实施例中,该第一基板21为线路板,其定义有相对的第一表面21a与第二表面21b,并于该第一表面21a定义有第一天线布设区A1,并配置有第一天线结构210,且该第一基板21还包含有第一线路层211,其中,该第一天线结构210为线路型天线,其可选择性电性连接或电性隔绝该第一线路层211,且该第一线路层211包含至少一第一电性接点212与多个植球垫213。应可理解地,该第一基板21也可为其它承载晶片的承载件,并不限于上述。
如图2B所示,形成一阻层29于该第一基板21的第一表面21a上,且该阻层29具有多个外露部分该第一基板21的开口290,以形成支撑体23于该开口290中,使该支撑体23直接接触该第一基板21。
于本实施例中,该阻层29的材质为可蚀刻材料,如绝缘材或如镍、铜的金属材,其压合至该第一基板21上,且该开口290未外露该第一天线布设区A1。
此外,构成该支撑体23的材质可为导电材、绝缘材或其二者组合。于一实施例中,该支撑体23为如铜或镍的导电柱,其接合该第一电性接点212,以电性连接该第一基板21,使该第一基板21与该支撑体23以金属对金属接合(metal-to-metal bonding)的方式接合。或者,于一实施例中,如图2E’所示,该支撑体24为绝缘柱,其接合该第一基板21的第一表面21a而未电性连接该第一基板21,使该第一基板21与该支撑体24以绝缘材对绝缘材接合的方式接合,也就是说,本案的基板与支撑体的接合方式可为基板制程的压合(lamination)方式接合或金属与金属接合或绝缘材与绝缘材接合,但不依此为限。抑或,于一实施例中,该支撑体23,24可为绝缘材包覆导电核心的实施例、或导电材包覆绝缘核心的实施例。
又,应可理解地,该支撑体23虽为导电柱,但其仍可能未电性导通该第一基板21。换言之,该支撑体23也可仅作为支撑用,即该第一基板21与该支撑体23非电性导通,例如,该第一电性接点212作为无电性功能的虚垫(dummy pad),使该支撑体23无法电性导通该第一线路层211。
另外,该阻层29的材质不同于该支撑体23,24的材质。例如,该阻层29的第一金属材为镍材,而该支撑体23的第二金属材为铜材。或者,该阻层29的第一金属材为铜材,而该支撑体23的第二金属材为镍材。
如图2C所示,将一第二基板22压合至该阻层29上,并令该第二基板22直接接触该些支撑体23。
于本实施例中,该第二基板22为天线板,其定义有对应该第一天线布设区A1的第二天线布设区A2,使该第一天线布设区A1与第二天线布设区A2之间作为天线作用区S,并于该第二天线布设区A2上配置有第二天线结构220,且该第二基板22还具有第二线路层221,其中,该第二天线结构220为线路型天线,其可选择性电性连接或电性隔绝该第二线路层221,且该第二线路层221包含至少一第二电性接点222。应可理解地,该第二基板22也可为其它类型的天线板,并不限于上述。
此外,该支撑体23直接接合于该第一电性接点212与第二电性接点222之间,以电性连接该第一基板21与该第二基板22。或者,该第二电性接点222作为无电性功能的虚垫,使该支撑体23无法电性导通该第二线路层221。
又,该第二天线结构220感应该第一天线结构210,以讯号传输于该第一天线布设区A1与该第二天线布设区A2之间。
另外,该第一电性接点212或第二电性接点222作为无电性功能的虚垫,使该支撑体23无法电性导通该第二天线结构220及第一天线结构210。
如图2D所示,以蚀刻方式移除该阻层29,使该第一基板21与该第二基板22借由该些支撑体23相互堆叠。
于本实施例中,该些支撑体23位于该天线作用区S周围,使该天线作用区S呈空旷空间。
此外,于一生产版面上配置有多个天线作用区S时,如图2C’所示,可于该第二基板22上形成至少一开孔26,以将蚀刻液体由该开孔26填入该第一基板21与该第二基板22之间而蚀刻移除该阻层29。进一步,可依需求于后续切单制程中,将该开孔26作为切割路径以移除该开孔26。
又,于另一实施例中,于该第一基板21的同一单位面积上可依数量需求形成该支撑体23,如图2D’所示的数量较少的支撑体23且该支撑体23的宽度大于图2D的支撑体的宽度。
如图2E所示,可将该第一基板21与该第二基板22的位置上、下翻转,再于该第一基板21的第二表面21b上设置至少一电子元件20,且于多个该植球垫213上形成多个如焊球的导电元件25,进而制得电子封装件2。后续可回焊该些导电元件25以供接置如电路板或另一线路板的电子结构(图未示)。
此外,该电子元件20为主动元件、被动元件或其二者组合等,其中,该主动元件例如为半导体晶片,且该被动元件例如为电阻、电容及电感。例如,该电子元件20借由多个如焊锡材料的导电凸块200以覆晶方式电性连接该第一线路层211;或者,该电子元件20可借由多个焊线(图略)以打线方式电性连接该第一线路层211;抑或,该电子元件20可直接接触该第一线路层211以电性连接该第一线路层211。然而,有关该电子元件20电性连接该第一基板21的方式不限于上述。
又,有关该电子元件20的配置方式繁多(如设于该第一基板21的第一表面21a,使该电子元件20位于该第一基板21与第二基板22之间),并不限于上述。
本发明的电子封装件2的制法主要借由将该第二基板22直接压合至该阻层29上的方式以控制该第一基板21与第二基板22之间的距离D(如图2C所示的阻层29的高度H),且令该支撑体23,24堆叠该第一基板21与该第二基板22,而无需使用焊锡材料,使该第一基板21与该第二基板22之间的距离D几乎保持不变(如该第一基板21与该第二基板22不会相互倾斜),即能控制该距离D的公差小于10um。
因此,相比于现有技术,本发明的电子封装件2能精确控制该第一基板21与第二基板22之间的距离D,使该距离D不会因变化过大而影响该第一天线结构210与第二天线结构220的功能,因而能有效控制天线品质,进而能提高产品良率。
图3A至图3C为本发明的电子封装件3的制法的第二实施例的剖面示意图。本实施例与上述实施例的差异在于新增包覆材,其它制程大致相同,故不再赘述相同处。
如图3A所示,其接续图2B的制程,于形成该支撑体23于该开口290中后,移除该些支撑体23周围的阻层29的材质以形成开口区390,使该些支撑体23的侧面23c没有接触该阻层29。
如图3B所示,形成包覆材30于该开口区390中以接触及包覆该些支撑体23的侧面23c,其中,该包覆材30为绝缘材。
如图3C所示,其依照图2C至图2E的制程依序进行设置第二基板22、移除该阻层29及设置电子元件20与导电元件25等制程,以获得一具有包覆材30的电子封装件3。
本发明还提供一种电子封装件2,3,其包括:一第一基板21、一第二基板22以及至少一支撑体23,24。
所述的第一基板21具有第一天线布设区A1。
所述的支撑体23,24设于该第一基板21上。
所述的第二基板22直接压合至该支撑体23,24上,使该第一基板21与该第二基板22借由该支撑体23,24相互堆叠,且该第二基板22具有对应该第一天线布设区A1的第二天线布设区A2。
于一实施例中,该第一天线布设区A1与该第二天线布设区A2之间为天线作用区S。例如,该支撑体23,24位于该天线作用区S周围,使该天线作用区S呈空旷空间。
于一实施例中,该支撑体23,24为导电材或绝缘材。
于一实施例中,该支撑体23,24未电性连接该第一天线布设区A1及/或第二天线布设区A2。
于一实施例中,该支撑体23,24未电性连接该第一基板21及/或第二基板22。
于一实施例中,该支撑体23电性连接该第一基板21及/或第二基板22。
于一实施例中,该些支撑体23的侧面23c上形成有包覆材30,且该包覆材30未形成于该天线作用区S上。
于一实施例中,所述的电子封装件2还包括至少一电子元件20,其设于该第一基板21上。抑或,该电子元件20位于该第一基板21与第二基板22之间。
综上所述,本发明的电子封装件及其制法,透过阻层及支撑体的设置并借由压合该第二基板的设计,而无需使用焊锡材料接合支撑体与基板,使该第一与第二基板之间的距离能符合所需的大小,故本发明的电子封装件能确保该天线作用区的天线传输功能正常,因而能确保产品良率符合预期。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。

Claims (22)

1.一种电子封装件,其特征为,该电子封装件包括:
第一基板,其具有第一天线布设区;
支撑体,其设于该第一基板上;以及
第二基板,其压合至该支撑体上,使该第一基板与该第二基板借由该支撑体相互堆叠并控制该第一基板与该第二基板之间的距离,且该第二基板具有对应该第一天线布设区的第二天线布设区。
2.根据权利要求1所述的电子封装件,其特征为,该第一天线布设区与该第二天线布设区之间为天线作用区。
3.根据权利要求2所述的电子封装件,其特征为,该天线作用区呈空旷空间。
4.根据权利要求1所述的电子封装件,其特征为,构成该支撑体的材质为导电材或绝缘材。
5.根据权利要求1所述的电子封装件,其特征为,该支撑体未电性连接该第一天线布设区及/或第二天线布设区。
6.根据权利要求1所述的电子封装件,其特征为,该支撑体未电性连接该第一基板及/或第二基板。
7.根据权利要求1所述的电子封装件,其特征为,该支撑体电性连接该第一基板及/或第二基板。
8.根据权利要求1所述的电子封装件,其特征为,该支撑体上形成有包覆材。
9.根据权利要求1所述的电子封装件,其特征为,该电子封装件还包括电子元件,其设于该第一基板上。
10.根据权利要求9所述的电子封装件,其特征为,该电子元件位于该第一基板与第二基板之间。
11.一种电子封装件的制法,其特征为,该制法包括:
形成阻层于一具有第一天线布设区的第一基板上,且该阻层形成有至少一外露部分该第一基板的开口;
形成支撑体于该开口中,使该支撑体接触该第一基板;
压合一具有第二天线布设区的第二基板于该阻层上,使该第二基板接触该支撑体,其中,该第二基板具有对应该第一天线布设区的第二天线布设区;以及
移除该阻层,使该第一基板与该第二基板借由该支撑体相互堆叠。
12.根据权利要求11所述的电子封装件的制法,其特征为,该第一天线布设区与该第二天线布设区之间为天线作用区。
13.根据权利要求12所述的电子封装件的制法,其特征为,该天线作用区呈现空旷空间。
14.根据权利要求11所述的电子封装件的制法,其特征为,构成该阻层的材质为可蚀刻材料。
15.根据权利要求11所述的电子封装件的制法,其特征为,该开口未外露该第一天线布设区。
16.根据权利要求11所述的电子封装件的制法,其特征为,构成该支撑体的材质为导电材或绝缘材。
17.根据权利要求11所述的电子封装件的制法,其特征为,该支撑体未电性连接该第一天线布设区及/或第二天线布设区。
18.根据权利要求11所述的电子封装件的制法,其特征为,该支撑体未电性连接该第一基板及/或第二基板。
19.根据权利要求11所述的电子封装件的制法,其特征为,该支撑体电性连接该第一基板及/或第二基板。
20.根据权利要求11所述的电子封装件的制法,其特征为,该支撑体上形成有包覆材。
21.根据权利要求11所述的电子封装件的制法,其特征为,该制法还包括设置电子元件于该第一基板上。
22.根据权利要求21所述的电子封装件的制法,其特征为,该电子元件位于该第一基板与第二基板之间。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700801B (zh) * 2019-09-16 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI705549B (zh) * 2019-12-31 2020-09-21 矽品精密工業股份有限公司 電子封裝件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118406A (en) * 1998-12-21 2000-09-12 The United States Of America As Represented By The Secretary Of The Navy Broadband direct fed phased array antenna comprising stacked patches
US20090289852A1 (en) * 2008-05-23 2009-11-26 Agc Automotive Americas R&D, Inc. Multi-layer offset patch antenna
US20120013007A1 (en) * 2010-07-15 2012-01-19 Hyun-Ik Hwang Package-on-package semiconductor package having spacers disposed between two package substrates
CN107078405A (zh) * 2014-10-20 2017-08-18 株式会社村田制作所 无线通信模块
TWI601219B (zh) * 2016-08-31 2017-10-01 矽品精密工業股份有限公司 電子封裝件及其製法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639558B2 (en) * 2002-02-06 2003-10-28 Tyco Electronics Corp. Multi frequency stacked patch antenna with improved frequency band isolation
US8269671B2 (en) * 2009-01-27 2012-09-18 International Business Machines Corporation Simple radio frequency integrated circuit (RFIC) packages with integrated antennas
US9153542B2 (en) * 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8866292B2 (en) * 2012-10-19 2014-10-21 Infineon Technologies Ag Semiconductor packages with integrated antenna and methods of forming thereof
TWI520289B (zh) * 2012-12-28 2016-02-01 財團法人工業技術研究院 三維波導元件
TWI543438B (zh) * 2014-04-30 2016-07-21 耀登科技股份有限公司 晶片式天線裝置及封裝晶片結構
TWM511729U (zh) * 2014-12-02 2015-11-01 Unimicron Technology Corp 線路板結構
US9881903B2 (en) * 2016-05-31 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with epoxy flux residue

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118406A (en) * 1998-12-21 2000-09-12 The United States Of America As Represented By The Secretary Of The Navy Broadband direct fed phased array antenna comprising stacked patches
US20090289852A1 (en) * 2008-05-23 2009-11-26 Agc Automotive Americas R&D, Inc. Multi-layer offset patch antenna
US20120013007A1 (en) * 2010-07-15 2012-01-19 Hyun-Ik Hwang Package-on-package semiconductor package having spacers disposed between two package substrates
CN107078405A (zh) * 2014-10-20 2017-08-18 株式会社村田制作所 无线通信模块
TWI601219B (zh) * 2016-08-31 2017-10-01 矽品精密工業股份有限公司 電子封裝件及其製法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700801B (zh) * 2019-09-16 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法

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