CN110211942A - 一种芯片封装用的铜夹和芯片封装结构 - Google Patents

一种芯片封装用的铜夹和芯片封装结构 Download PDF

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CN110211942A
CN110211942A CN201910620453.7A CN201910620453A CN110211942A CN 110211942 A CN110211942 A CN 110211942A CN 201910620453 A CN201910620453 A CN 201910620453A CN 110211942 A CN110211942 A CN 110211942A
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杨建伟
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Guangdong Style Science And Technology Ltd
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Abstract

本发明涉及一种芯片封装用的铜夹和芯片封装结构，所述芯片封装结构包括芯片和铜夹，所述芯片上设有焊接材料，所述铜夹通过所述焊接材料焊接在芯片上，所述铜夹包括铜夹本体，所述铜夹本体的焊接面上设有至少一个凸台，所述凸台周围还开设有通孔。本发明所述铜夹采用了特殊的结构，在铜夹本体的焊接面上设有凸台，还在凸台周围开设有通孔，凸台在焊接中起到支撑的作用，有效防止铜夹焊接过程中倾斜；在焊接时，焊接材料中的空气在热力和浮力作用下从通孔处逸出，有效解决了气泡问题，提高了焊接质量，改善了产品的电性能、导热性能和可靠性。

Description

一种芯片封装用的铜夹和芯片封装结构
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种芯片封装用的铜夹和芯片封装结构。
背景技术
本申请人在专利申请号为201811512267.3、发明名称为“一种铜夹堆叠芯片结构及其封装方法”中提供一种了铜夹堆叠芯片结构及其封装方法，弥补了传统金属线连接的低电流，散热差的缺点，可广泛用于大功率、高电流、低功耗、高散热要求的芯片封装产品。但是在实现生产过程中存在以下问题：一是在铜夹焊接中，由于焊接材料和铜夹的特性(面积大)，由于空气无法有效逸出，会有大量气孔出现在铜夹与芯片之间的焊接层里，气孔的面积也随着铜夹和芯片的焊接面积增大而增大，焊接层气孔会导致产品的导热性能降低，电信号也受影响，产品的质量和可靠性下降，对于高导热、高导电要求的铜夹封装芯片产品，影响会更大，亟待解决气孔问题；二是在进行回流焊接过程中，焊接材料会熔化成为液态状，无法给放置在其上部的铜夹提供稳定的支撑，铜夹受重力作用会出现整体位置倾斜，高低不平，在回流冷却时出现铜夹焊接倾斜，铜夹与芯片之间焊接材料厚度不均匀，这又会导致铜夹电输出、热传导不均匀，影响产品的性能，满足不了产品的高性能要求。
发明内容
本发明的目的在于提供一种芯片封装用的铜夹和芯片封装结构，有效解决在焊接层里产生气孔和铜夹焊接倾斜的技术问题。
本发明是这样实现的：一种芯片封装用的铜夹，包括铜夹本体，所述铜夹本体的焊接面上设有至少一个凸台，所述凸台周围还开设有通孔。
其中，所述凸台为上宽下窄的锥台结构。
其中，所述凸台为圆形锥台或条形锥台或弧形锥台。
其中，所述通孔为围绕所述凸台的多段式或单段式的通孔。
其中，所述通孔为条形通孔或弧形通孔。
其中，所述通孔的宽度为100-500μm。
其中，所述凸台高度为30-60μm，凸台根部的直径为50-100μm，或者凸台根部的宽度为50-100μm。
本发明提供的另一种技术方案为：一种芯片封装结构，包括芯片和上面所述的铜夹，所述芯片上设有焊接材料，所述铜夹通过所述焊接材料焊接在芯片上。
本发明的有益效果为：本发明所述铜夹采用了特殊的结构，在铜夹本体的焊接面上设有凸台，还在凸台周围开设有通孔，所述凸台的高度需要根据产品的焊接层厚度来确定，所述凸台和通孔的大小、位置及数量要与铜夹与芯片之间焊接层的形状和尺寸要做相应的匹配或调整，首先，凸台在焊接中起到支撑的作用，当焊接材料变成液态时，铜夹受重力作用，凸台会先与芯片焊接面接触，形成稳定的支撑，有效防止铜夹焊接过程中倾斜；在把铜夹放置到芯片上时，对平稳度要求降低，因为即使铜夹具有一定程度的倾斜，在通过回流焊时，利用铜夹的重力和凸台的支撑作用，可以把铜夹的倾斜角度进行校正，达到产品要求；其次，凸台周围开设有通孔，在焊接时，焊接材料中的空气在热力和浮力作用下，从通孔处逸出，而且通孔对压扣在铜夹下面的焊接材料(一般为锡膏，可以为点胶方式，也可以印刷方式)具有收聚的效果(爬锡现象)，进一步帮助挤压排出熔化的液态焊接材料中的空气，保证了铜夹与芯片之间的焊接层无气泡或很少气泡，有效解决了气泡问题，提高了焊接质量，改善了产品的电性能、导热性能和可靠性，通孔对液态焊接材料的收聚作用还能防止液态焊接材料在铜夹、芯片边缘位置外溢流出，解决焊接时因焊接材料溢出造成的短路、沾污等问题；在后序的塑封时，塑封料会进入通孔内，对铜夹起到锁紧作用，加强铜夹表面和塑封料这两种材料之间的结合力，降低了铜夹表面和塑封料分层的风险，提高产品的可靠性，尤其对于在高温度工作环境(200度以上)的产品，质量和可靠性优势更加明显。
附图说明
图1是本发明所述芯片封装结构实施例的剖面结构图；
图2是本发明所述铜夹与芯片焊接后的状态示意图；
图3是本发明所述铜夹实施例一的仰视图；
图4是本发明所述铜夹实施例一阶梯剖的剖面示意图；
图5是本发明所述铜夹实施例二的仰视图；
图6是本发明所述铜夹实施例三的仰视图；
图7是本发明所述铜夹实施例四的仰视图；
图8是本发明所述铜夹实施例五的仰视图。
为了区分凸台和通孔，图3、图5至图8中阴影部分为凸台。
其中，1、铜夹本体；2、凸台；3、通孔；4、芯片；5、焊接材料；6、塑封料；7、引线框。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
作为本发明所述芯片封装结构和铜夹的实施例一，如图1至图4所示，所述芯片封装结构包括芯片4和铜夹，所述芯片4上设有焊接材料5，所述铜夹通过所述焊接材料5焊接在芯片4上，所述铜夹包括铜夹本体1，所述铜夹本体1的焊接面上设有至少一个凸台2，所述凸台2周围还开设有通3孔。所述凸台2体积较小时，也可以称为凸点。
本发明所述铜夹采用了特殊的结构，在铜夹本体1的焊接面上设有凸台2，还在凸台2周围开设有通孔3，所述凸台2的高度需要根据产品的焊接层厚度来确定，所述凸台2和通孔3的大小、位置及数量要与铜夹与芯片之间焊接层的形状和尺寸要做相应的匹配或调整，首先，凸台2在焊接中起到支撑的作用，当焊接材料5变成液态时，铜夹受重力作用，凸台2会先与芯片4焊接面接触，形成稳定的支撑，有效防止铜夹焊接过程中倾斜；在把铜夹放置到芯片4上时，对平稳度要求降低，因为即使铜夹具有一定程度的倾斜，在通过回流焊时，利用铜夹的重力和凸台2的支撑作用，可以把铜夹的倾斜角度进行校正，达到产品要求；其次，凸台2周围开设有通孔3，在焊接时，焊接材料5中的空气在热力和浮力作用下，从通孔3处逸出，而且通孔3对压扣在铜夹下面的焊接材料5(一般为锡膏，可以为点胶方式，也可以印刷方式)具有收聚的效果(爬锡现象)，进一步帮助挤压排出熔化的液态焊接材料5中的空气，保证了铜夹与芯片4之间的焊接层无气泡或很少气泡，有效解决了气泡问题，提高了焊接质量，改善了产品的电性能、导热性能和可靠性，通孔3对液态焊接材料5的收聚作用还能防止液态焊接材料在铜夹、芯片边缘位置外溢流出，解决焊接时因焊接材料溢出造成的短路、沾污等问题；在后序的塑封时，塑封料6会进入通孔3内，对铜夹起到锁紧作用，加强铜夹表面和塑封料6这两种材料之间的结合力，降低了铜夹表面和塑封料6分层的风险，提高产品的可靠性，尤其对于在高温度工作环境(200度以上)的产品，质量和可靠性优势更加明显。
在本实施例中，所述凸台2为如图3所示的圆形锥台，当然也可以为如图7所示的条形锥台，又或者为如图8所示的弧形锥台，仅仅在形状上有所不同，但起到的作用是一致的。相应地，所述通孔3也可以为如图3和图8所示的弧形通孔，也可以为如图7所示的条形通孔。
在本实施例中，所述凸台2为上宽下窄的锥台结构，倾斜的侧面对气体具有引导作用，利于焊接材料中的空气沿着凸台侧面移动，并从凸台2周围的通孔3处逸出。
在本实施例中，所述凸台2高度为30-60μm，凸台2高度需要根据产品的焊接层厚度来确定，凸台2不能太高，太高会造成只有凸台2与芯片4焊接，其它位置没有被焊接(焊接锡不足)，出现严重的不充分焊接；凸台2高度不能太小，若焊接时接触不到芯片4，起不到稳定支撑的作用，铜夹仍然会有焊接倾斜。当凸台2为圆形锥台时，凸台2根部的直径优选值为50-100μm，或者当凸台2为条形或弧形时，凸台根部的宽度优选值为50-100μm。
在本实施例中，所述通孔3为围绕所述凸台2的单段式通孔，当然也可以为如图6所示的多段式通孔，效果也基本一致。
在本实施例中，所述通孔3的宽度也要合适，优选值为100-500μm。通孔3太窄，对塑封料6的颗粒尺寸要求也高，容易出现不充分填充，通孔3太宽，对产品整体的散热性有很大影响，不利于散热。
在本发明中，所述凸台和通孔的大小、位置及数量要与铜夹与芯片之间焊接层的形状和尺寸要做相应的匹配或调整，可以灵活采用各种阵列方式。适用于不同尺寸的芯片，对于焊接面积大的芯片排气和改善倾斜效果更明显。所述凸台主要通过冲压方式制作出来，所述通孔可以用冲压、刻蚀或激光开孔等方式制作出来。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (8)

1.一种芯片封装用的铜夹，其特征在于，包括铜夹本体，所述铜夹本体的焊接面上设有至少一个凸台，所述凸台周围还开设有通孔。
2.根据权利要求1所述芯片封装用的铜夹，其特征在于，所述凸台为上宽下窄的锥台结构。
3.根据权利要求2所述芯片封装用的铜夹，其特征在于，所述凸台为圆形锥台或条形锥台或弧形锥台。
4.根据权利要求1所述芯片封装用的铜夹，其特征在于，所述通孔为围绕所述凸台的多段式或单段式的通孔。
5.根据权利要求4所述芯片封装用的铜夹，其特征在于，所述通孔为条形通孔或弧形通孔。
6.根据权利要求4所述芯片封装用的铜夹，其特征在于，所述通孔的宽度为100-500μm。
7.根据权利要求1所述芯片封装用的铜夹，其特征在于，所述凸台高度为30-60μm，凸台根部的直径为50-100μm，或者凸台根部的宽度为50-100μm。
8.一种芯片封装结构，其特征在于，包括芯片和权利要求1至7任一项所述的铜夹，所述芯片上设有焊接材料，所述铜夹通过所述焊接材料焊接在芯片上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116072647A (zh) * 2023-03-28 2023-05-05 深圳市深鸿盛电子有限公司 一种mos芯片封装结构及其封装方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456655A (zh) * 2010-10-15 2012-05-16 三垦电气株式会社 半导体模块
CN204144243U (zh) * 2014-10-17 2015-02-04 常州银河世纪微电子有限公司 一种贴片式二极管的结构
CN104979320A (zh) * 2014-04-07 2015-10-14 恩智浦有限公司 用于与半导体器件的连接的引线
CN109494205A (zh) * 2018-12-11 2019-03-19 广东气派科技有限公司 一种铜夹堆叠芯片结构及其封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456655A (zh) * 2010-10-15 2012-05-16 三垦电气株式会社 半导体模块
CN104979320A (zh) * 2014-04-07 2015-10-14 恩智浦有限公司 用于与半导体器件的连接的引线
CN204144243U (zh) * 2014-10-17 2015-02-04 常州银河世纪微电子有限公司 一种贴片式二极管的结构
CN109494205A (zh) * 2018-12-11 2019-03-19 广东气派科技有限公司 一种铜夹堆叠芯片结构及其封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116072647A (zh) * 2023-03-28 2023-05-05 深圳市深鸿盛电子有限公司 一种mos芯片封装结构及其封装方法

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