CN110209625B - 一种基于低频参考信号的片上同步自修复系统 - Google Patents
一种基于低频参考信号的片上同步自修复系统 Download PDFInfo
- Publication number
- CN110209625B CN110209625B CN201910289884.XA CN201910289884A CN110209625B CN 110209625 B CN110209625 B CN 110209625B CN 201910289884 A CN201910289884 A CN 201910289884A CN 110209625 B CN110209625 B CN 110209625B
- Authority
- CN
- China
- Prior art keywords
- input
- dual
- pll
- chip
- common
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims abstract description 47
- 230000008878 coupling Effects 0.000 claims abstract description 40
- 238000010168 coupling process Methods 0.000 claims abstract description 40
- 238000005859 coupling reaction Methods 0.000 claims abstract description 40
- 230000010355 oscillation Effects 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 12
- 239000000872 buffer Substances 0.000 claims description 40
- 229920000729 poly(L-lysine) polymer Polymers 0.000 claims description 32
- 101100350613 Arabidopsis thaliana PLL1 gene Proteins 0.000 claims description 13
- 101100082028 Arabidopsis thaliana PLL2 gene Proteins 0.000 claims description 13
- 101100350628 Arabidopsis thaliana PLL3 gene Proteins 0.000 claims description 9
- 230000009977 dual effect Effects 0.000 claims description 9
- 230000010363 phase shift Effects 0.000 claims description 9
- 101100033865 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA1 gene Proteins 0.000 claims description 8
- 101100524516 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA2 gene Proteins 0.000 claims description 8
- 101100296075 Arabidopsis thaliana PLL4 gene Proteins 0.000 claims description 7
- 101100381996 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) BRO1 gene Proteins 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000003491 array Methods 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0045—Correction by a latch cascade
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- Software Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Radar Systems Or Details Thereof (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (5)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910289884.XA CN110209625B (zh) | 2019-04-11 | 2019-04-11 | 一种基于低频参考信号的片上同步自修复系统 |
US17/043,667 US11705908B2 (en) | 2019-04-11 | 2020-04-09 | On-chip synchronous self-repairing system based on low-frequency reference signal |
PCT/CN2020/084002 WO2020207443A1 (zh) | 2019-04-11 | 2020-04-09 | 一种基于低频参考信号的片上同步自修复系统 |
JP2020558604A JP7240010B2 (ja) | 2019-04-11 | 2020-04-09 | 低周波基準信号に基づくオンチップの同期自己修復システム |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910289884.XA CN110209625B (zh) | 2019-04-11 | 2019-04-11 | 一种基于低频参考信号的片上同步自修复系统 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110209625A CN110209625A (zh) | 2019-09-06 |
CN110209625B true CN110209625B (zh) | 2020-08-11 |
Family
ID=67785287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910289884.XA Active CN110209625B (zh) | 2019-04-11 | 2019-04-11 | 一种基于低频参考信号的片上同步自修复系统 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11705908B2 (zh) |
JP (1) | JP7240010B2 (zh) |
CN (1) | CN110209625B (zh) |
WO (1) | WO2020207443A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110209625B (zh) | 2019-04-11 | 2020-08-11 | 浙江大学 | 一种基于低频参考信号的片上同步自修复系统 |
WO2023159649A1 (zh) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | 一种相控阵装置、通信设备及控制方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105790760A (zh) * | 2015-01-14 | 2016-07-20 | 英飞凌科技股份有限公司 | 通过使用减小的频率信号传输使多个振荡器同步的系统和方法 |
CN107251319A (zh) * | 2015-02-26 | 2017-10-13 | 特拉维夫大学拉莫特有限公司 | 用于改进片上天线的效率的技术 |
CN109375182A (zh) * | 2018-10-30 | 2019-02-22 | 浙江大学 | 雷达接收机幅相一致性校正系统 |
US10243573B1 (en) * | 2018-03-27 | 2019-03-26 | Texas Instruments Incorporated | Phase syncronizing PLL output across reference and VCO clock domains |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8513607B2 (en) * | 2011-04-12 | 2013-08-20 | Texas Instruments Incorporated | Analog baseband circuit for a terahertz phased array system |
JP5634343B2 (ja) | 2011-07-05 | 2014-12-03 | 三菱電機株式会社 | 注入同期発振装置 |
JP5811863B2 (ja) | 2012-01-26 | 2015-11-11 | 富士通株式会社 | クロック分配器、及び、電子装置 |
JP6102346B2 (ja) * | 2013-03-01 | 2017-03-29 | 富士通株式会社 | 電子回路、レーダ装置、及びレーダ装置の自己診断方法 |
US9225507B1 (en) * | 2013-06-04 | 2015-12-29 | Pmc-Sierra Us, Inc. | System and method for synchronizing local oscillators |
JP6263906B2 (ja) | 2013-08-28 | 2018-01-24 | 富士通株式会社 | 電子回路および制御方法 |
US9270289B2 (en) | 2014-02-13 | 2016-02-23 | Fujitsu Limited | Monolithic signal generation for injection locking |
US9602587B2 (en) * | 2014-06-26 | 2017-03-21 | Altera Corporation | Multiple plane network-on-chip with master/slave inter-relationships |
US9825694B2 (en) * | 2015-08-18 | 2017-11-21 | Maxlinear, Inc. | Transceiver array with adjustment of local oscillator signals based on phase difference |
US9735793B2 (en) | 2015-12-08 | 2017-08-15 | Nxp Usa, Inc. | Low-power clock repeaters and injection locking protection for high-frequency clock distributions |
US10439623B2 (en) | 2017-05-30 | 2019-10-08 | Globalfoundries Inc. | Injection locked oscillator system and processes |
US10680623B2 (en) * | 2018-04-17 | 2020-06-09 | Huawei Technologies Co., Ltd. | System for coherent distribution of oscillator signal |
US10374558B1 (en) * | 2018-04-30 | 2019-08-06 | Speedlink Technology Inc. | Wideband distributed power amplifier utilizing metamaterial transmission line conception with impedance transformation |
CN109379102A (zh) * | 2018-12-06 | 2019-02-22 | 西南电子技术研究所(中国电子科技集团公司第十研究所) | 多通道捷变频收发装置 |
CN110209625B (zh) * | 2019-04-11 | 2020-08-11 | 浙江大学 | 一种基于低频参考信号的片上同步自修复系统 |
-
2019
- 2019-04-11 CN CN201910289884.XA patent/CN110209625B/zh active Active
-
2020
- 2020-04-09 US US17/043,667 patent/US11705908B2/en active Active
- 2020-04-09 WO PCT/CN2020/084002 patent/WO2020207443A1/zh active Application Filing
- 2020-04-09 JP JP2020558604A patent/JP7240010B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105790760A (zh) * | 2015-01-14 | 2016-07-20 | 英飞凌科技股份有限公司 | 通过使用减小的频率信号传输使多个振荡器同步的系统和方法 |
CN107251319A (zh) * | 2015-02-26 | 2017-10-13 | 特拉维夫大学拉莫特有限公司 | 用于改进片上天线的效率的技术 |
US10243573B1 (en) * | 2018-03-27 | 2019-03-26 | Texas Instruments Incorporated | Phase syncronizing PLL output across reference and VCO clock domains |
CN109375182A (zh) * | 2018-10-30 | 2019-02-22 | 浙江大学 | 雷达接收机幅相一致性校正系统 |
Non-Patent Citations (2)
Title |
---|
Calibration of a Digital Phased Array by Using NCO Phase Increasing Algorithm;Yang, Lijie等;《IEICE TRANSACTIONS ON COMMUNICATIONS》;20190401;第E102B卷(第4期);第948-955页 * |
用于海洋监测的宽带数字相控阵关键技术;杨李杰等;《科技导报》;20171028;第35卷(第20期);第119-125页 * |
Also Published As
Publication number | Publication date |
---|---|
US11705908B2 (en) | 2023-07-18 |
JP7240010B2 (ja) | 2023-03-15 |
US20220052695A1 (en) | 2022-02-17 |
JP2021520744A (ja) | 2021-08-19 |
CN110209625A (zh) | 2019-09-06 |
WO2020207443A1 (zh) | 2020-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7499513B1 (en) | Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit | |
CN105703767B (zh) | 一种高能效低抖动的单环路时钟数据恢复电路 | |
EP3098967B1 (en) | Crystal-based oscillator for use in synchronized system | |
US4119796A (en) | Automatic data synchronizer | |
US7619451B1 (en) | Techniques for compensating delays in clock signals on integrated circuits | |
US7590211B1 (en) | Programmable logic device integrated circuit with communications channels having sharing phase-locked-loop circuitry | |
CN101309079B (zh) | 一种用于锁相环电路(pll)的电荷泵结构 | |
CN110209625B (zh) | 一种基于低频参考信号的片上同步自修复系统 | |
US8228102B1 (en) | Phase-locked loop architecture and clock distribution system | |
US8665928B1 (en) | Circuit for generating an output clock signal synchronized to an input clock signal | |
KR20080038777A (ko) | 클럭 데이터 복원장치. | |
CN104836573B (zh) | 一种超大面阵cmos相机多路高速信号的同步时钟系统 | |
JP2012527044A (ja) | チャネルに対するクロック分配技法 | |
US11777475B2 (en) | Multiple adjacent slicewise layout of voltage-controlled oscillator | |
US8611379B2 (en) | Resonant clock amplifier with a digitally tunable delay | |
KR100317679B1 (ko) | 링 발진기 출력파형간의 위상 오프셋을 보정하기 위한자기 보정회로 및 방법 | |
EP4012948A1 (en) | Software-controlled clock synchronization of network devices | |
US20220021394A1 (en) | Zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization | |
US8269533B2 (en) | Digital phase-locked loop | |
US6910144B2 (en) | Method and configuration for generating a clock pulse in a data processing system having a number of data channels | |
TWI765825B (zh) | 注入鎖定鎖頻迴路振盪單元 | |
US20220200610A1 (en) | Clocking system and a method of clock synchronization | |
US10659059B2 (en) | Multi-phase clock generation circuit | |
Lin et al. | Phase interpolation technique based on high-speed SERDES chip CDR | |
US6990162B2 (en) | Scalable clock distribution for multiple CRU on the same chip |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20230329 Address after: 316000 Room 202, 11 Baichuan Road, Lincheng street, Dinghai District, Zhoushan City, Zhejiang Province (centralized office) Patentee after: ZHEJIANG JISU HEXIN TECHNOLOGY CO.,LTD. Address before: 310058 Yuhang Tang Road, Xihu District, Hangzhou, Zhejiang 866 Patentee before: ZHEJIANG University |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20230629 Address after: Plant 1, No. 13, Guiyang Avenue, Yantai Economic and Technological Development Zone, Shandong Province, 264000 Patentee after: Yantai Xin Yang Ju Array Microelectronics Co.,Ltd. Address before: 316000 Room 202, 11 Baichuan Road, Lincheng street, Dinghai District, Zhoushan City, Zhejiang Province (centralized office) Patentee before: ZHEJIANG JISU HEXIN TECHNOLOGY CO.,LTD. |
|
TR01 | Transfer of patent right |