US10439623B2 - Injection locked oscillator system and processes - Google Patents
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- US10439623B2 US10439623B2 US15/801,735 US201715801735A US10439623B2 US 10439623 B2 US10439623 B2 US 10439623B2 US 201715801735 A US201715801735 A US 201715801735A US 10439623 B2 US10439623 B2 US 10439623B2
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- 238000002347 injection Methods 0.000 title claims abstract description 42
- 239000007924 injection Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000008569 process Effects 0.000 title abstract description 13
- 238000005070 sampling Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 238000012937 correction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
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- 238000001228 spectrum Methods 0.000 description 2
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- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
Definitions
- the present disclosure relates to an injection locked oscillator system and processes and, more particularly, to structures and processes for generating an inductor-less frequency multiplier using injection locking and histogram calibration with a back-gate process.
- a structure comprises an injection locked oscillator (ILO) system which is structured to provide a local oscillator (LO) and a Digitally Controlled Oscillator (DCO) or Voltage Controlled Oscillator (VCO) frequency which is not harmonically related by an integer multiple to an output frequency.
- ILO injection locked oscillator
- DCO Digitally Controlled Oscillator
- VCO Voltage Controlled Oscillator
- a method comprises calibrating a free running frequency of an ILO using a calibration counter to compare a frequency of the ILO with a desired frequency output from a frequency control word (FCW).
- FCW frequency control word
- FIG. 1 shows a block diagram of a mixer with an injection locked oscillator (ILO) system and its connection to a PLL DCO via a programmable input divider in accordance with aspects of the present disclosure.
- ILO injection locked oscillator
- FIG. 2 shows a graph depicting different modes of operation according to aspects of the present disclosure.
- FIG. 3 shows a block diagram containing the ILO configured for startup calibration in accordance with aspects of the present disclosure.
- FIG. 4 shows a pictorial representation of a state machine used within background calibration and the effects of the free running frequency of the ILO to assess a direction to calibrate the ILO in accordance with aspects of the present disclosure.
- FIG. 5 shows a schematic enabling background calibration in accordance with aspects of the present disclosure.
- the present disclosure relates to an injection locked oscillator system and processes and, more particularly, to structures and processes for generating an inductor-less frequency multiplier (non-integer frequency multiplier) using injection locking and histogram calibration with a back-gate process. More specifically, the present disclosure provides a low power system capable of providing a local oscillator (LO) and a Digitally Controlled Oscillator (DCO) or Voltage Controlled Oscillator (VCO) frequency which is not harmonically related by a rational multiple. The use of DCO or VCO is interchangeable in this description.
- the structures and processes described herein can be used for ultra-low power designs with integrated power amplifiers, which can be implemented in Fully Depleted Silicon on Insulator (FDSOI) technology.
- FDSOI Fully Depleted Silicon on Insulator
- the structures described herein do not include inductors with co-existence of an on-chip power amplifiers and DCO.
- an on-chip power amplifier requires that a fractional, preferably non-integer numbers, frequency multiplication of a DCO be performed to move the local oscillator (LO) frequency away from the DCO center frequency and hence avoid corruption of the phase accuracy during transmit conditions.
- technologies with good electrical isolation e.g., FDSOI
- FDSOI FDSOI
- further measures of isolation are required such as making the DCO frequency and power amplifier output frequency non-integer harmonically related. In accordance with the disclosure, this can be accomplished by multiplying the DCO frequency by a ratio of rational numbers (non-integers) using the structures and processes described herein.
- FIG. 1 shows a block diagram of a mixer with an injection locked oscillator (ILO) system 16 and its connection to a PLL DCO 12 via a programmable input divider 14 .
- the ILO system 16 can be duplicated several times (n+1).
- the ILO system 16 can be split into two parts: (i) the input divider 14 and (ii) the remaining components within the block labeled with reference numeral 16 , e.g., ILO 18 , ILO calibration 28 , post divider 20 , quadrature generation 22 , etc. This allows the system 16 to minimize clock distribution current.
- the lowest frequency clock of the system 16 at the output of the input divider 14 , can be distributed and the higher speed clocks, at the output of the ILO 18 , can be generated locally (within the ILO system 16 ). This minimizes errors in the quadrature clocks 22 due to clock mismatch. Also, it is possible for the low speed clock from the input divider 14 to be distributed to both the TX and RX, where individual clocks of the correct frequency are generated.
- the PLL DCO 12 (external to the ILO system 16 ) supplies an input clock signal to the input divider 14 .
- the input divider 14 (which may be part of the ILO system 16 ) divides the PLL output clock to generate the input clock to the ILO system 16 .
- the input divider 14 takes a differential clock from the PLL DCO 12 and divides it by a number between, e.g., 2 and 16, and generates a differential output clock for injection into the ILO system 16 , e.g. ILO 18 . Note that division ratios that are multiples of 3 should be avoided so that the overall system can generate non-integer ratios after the ILO 18 multiples the input by 3 ⁇ .
- the input divider 14 is enabled or disabled by the ILO calibration 28 and its divide ratio can be set by a N_PRE_DIV input.
- the ILO 18 is a three stage ring oscillator capable of generating output frequencies from 2 GHz to 6 GHz, as illustrative examples, under the control of its supply voltage and back gate voltages.
- the ILO 18 can generate an output signal three times (3 ⁇ ) the frequency of its input signal.
- no injection clock is supplied from the input divider 14
- the ILO 18 will free run to allow a startup calibration to set an initial frequency as described with reference to FIG. 4 .
- a clock is supplied from the input divider 14 , that is within the lock range (for that free running frequency)
- the ILO 18 will lock to generate a frequency three times the input frequency as described further herein.
- the Vdd and back gate voltages of the ILO 18 are determined by the ILO calibration 28 as described below.
- a post divider 20 divides the output of the ILO 18 by an integer, e.g., 2, 4, 8, 16 or 32, to generate a quadrature output clock with four (4) phases separated by approximately 90 degrees. The output phases are determined by the rising and falling edges in the ILO output clock.
- a quadrature generator 22 (which may be part of the post divider 20 ) generates four phases of a quadrature clock.
- a phase correction 24 adjusts the output phases of the quadrature generator 22 to be within 1 degree of their target values. More specifically, the phase correction 24 is used to tune the output of the quadrature generator 22 to have an optimal relation between the in phase and quadrature clocks.
- This phase correction 24 can adjust the input phase difference by up to, e.g., ⁇ 5 ps in ⁇ 250 fs steps. And, it should be noted that the range may increase if required.
- the phase steps are guaranteed to be monotonic, but will have significant differences between steps.
- the output of the phase correction circuit 24 provides a 1.5 ⁇ frequency multiplication of the input to the ILO system 16 and does so in the I/Q domain.
- the phase change is controlled by a PH_ADJUST signal. Increasing the value of the PH_ADJUST signal makes the quadrature phase later.
- This input is intended to be generated by the phase correction 24 receiving the quadrature clock which can use internal measures to optimize this phase relationship. This phase correction range is sufficient to correct internal mismatch, plus an allowance for wiring mismatch within the target circuit.
- the ILO calibration 28 tunes the ILO frequency by adjusting the codes (signals) controlling an ILO regulator 38 and ILO back gate 40 , based on inputs from the ILO time to digital converter (TDC) 30 and calibration counter 34 as described herein.
- TDC time to digital converter
- the ILO calibration 28 sets the free running frequency of the ILO 18 to minimize modulation by the incoming clock and maximize the jitter transfer bandwidth.
- the ILO TDC 30 measures the modulation of the ILO clock by the input clock to allow the ILO calibration 28 to tune the free running frequency of the ILO 18 , thereby minimizing modulation.
- the ILO TDC 30 should accept clock signals from the ILO 18 up to 6 GHz.
- An ILO GRO 32 supplies a low speed clock that is unsynchronized to the ILO output or reference clock input which, in turn, is used by the ILO TDC 30 .
- a cali(bration) counter 34 (e.g., three state counter) counts the three ILO clock cycles per injection clock and a sampler 36 samples this count using the clock from the ILO GRO 32 to achieve a sampling that is unsynchronized to the ILO clock. Unsynchronized sampling means that the probability of a sample being captured is proportional to the probability of being in that state.
- the ILO calibration 28 can determine the difference in period caused to the ILO 18 by the injection pulse and act to minimize this period difference by tuning the free running frequency of the ILO to match its locked value.
- the counter 34 and the sampler 36 can be combined into a single module.
- the counter 34 and sampler 36 can also be the same one used in a PLL feedback counter.
- the counter 34 and sampler 36 are used to measure the ratio of the reference clock frequency to the ILO frequency to allow the ILO calibration 28 to set the free running frequency as accurately as possible before the ILO 18 is locked.
- the counter 34 is used by the ILO calibration 28 to determine the ratio between the frequencies of the ILO clock and the reference clock to allow the ILO clock to be set to a desired multiple.
- the counter 34 should operate with input frequencies between 2 and 6 GHz, as illustrative examples.
- the counter 34 increments a counter on each incoming clock from the ILO 18 , and presents a value that will be sampled (by the sampler 36 ) reliably, even near the time when the output is changing. This may require taking different samples or controlling the timing of sampling.
- the sampler 36 captures this value on the rising edge of the reference clock.
- the ILO regulator 38 is controlled by the ILO calibration 28 to coarsely set the ILO output frequency by controlling its Vdd. That is, the ILO regulator 38 supplies the Vdd for the ILO 18 , under the control of the ILO calibration 28 , which is used for coarse tuning of the ILO frequency during startup.
- the ILO regulator 38 should have a tuning step that is less than 10 mV across all PVT. For example, its range should span 200 mV to 600 mV.
- the ILO regulator 38 should also supply 300 ⁇ A to the ILO 18 .
- the input voltage is 800 mV+ ⁇ 5% and the supply voltages will be 800 mV.
- the input reference voltage from the bandgap will be 200 mV.
- the output stage can be NFET or PFET.
- the ILO back gate 40 is controlled by the ILO calibration 28 to set the ILO free running frequency more finely, e.g., fine tuning of the ILO frequency during startup and background calibration.
- the ILO back gate 40 supplies the back gate voltages (for both NFETs and PFETs in FDSOI) for the ILO 18 , under the control of the ILO calibration 28 .
- the ILO back gate 40 should have a tuning step that is less than 2 mV across all PVT, with a range span of at least ⁇ 1V.
- a bandgap 42 provides a reference for the ILO regulator 38 and ILO back gate 40 .
- FIG. 2 shows a graph depicting different modes of operation according to aspects of the present disclosure.
- FIG. 2 shows a free running mode (labeled free running), which is calculated during start up, an injection locked mode where F ERR is approximately equal to ⁇ F L , and an injection locked mode where F ERR is approximately equal to “0”.
- F ERR is the drift in output frequency without any calibration.
- Barr represents the frequency output due to injection from the PLL/DCO.
- a difference in injected cycle appears as a spur at the injection frequency (400 MHz-1 GHz).
- Calibrating the free running frequency of the ILO 18 minimizes the spur.
- calibrated ILO output spectrum is most like injection signal spectrum and reduces the phase noise at the output.
- FIG. 3 shows a block diagram containing the ILO configured for startup calibration.
- the output of the PLL/DCO 12 is set into free running mode by isolating the ILO 18 , e.g., disabling the injection.
- the isolation of the ILO 18 is provided by disabling the pre-divider 14 indicated by the open switch 15 .
- the free running frequency of the ILO 18 can be calibrated using the calibration counter 34 and the sampler 36 (not shown) to compare the ILO frequency with a desired frequency output from a frequency control word (FCW) 51 (which is constant for a given output frequency). In this manner, the output from the counter 34 can be used to determine whether the ILO 18 is running fast or slow.
- FCW frequency control word
- the edges of the frequencies, e.g., different states, are accumulated at reference numeral 53 .
- the binary search 43 then performs binary searches on the coarse (Vdd) and fine (back gate) controls to set the optimal frequency.
- the binary search 43 can generate digital codes that are used to control the Vdd and back gate voltage, e.g., VDD DACs 40 (e.g., ILO regulator and ILO back gate shown in FIG. 1 ).
- the binary search 43 can be a calibration algorithm that calibrates the ILO 18 to have the correct Vdd and back gate voltages with an optimum free running oscillation frequency and hence minimum phase noise when locked. This can be independent of the PLL/DCO while the PLL/DCO is locked.
- the injection of the input signal of the PLL/DCO is enabled via the input divider 14 (see, e.g., FIG. 5 ).
- the counter 34 (which can also include the sampler 36 of FIG. 1 ) then samples the output of the ILO 18 periodically and generates a histogram of how much time is spent in the injection cycle or free running cycles as shown in FIG. 4 .
- FIG. 4 shows a pictorial representation of a histogram to assess a direction to calibrate the ILO 18 .
- the cycles are the natural oscillation frequency of the ILO 18 , with the number of clock cycles counted in each state being roughly equal (e.g., state 0 , 1 , 2 being equal). But, in the case when the PLL/DCO is enabled, the frequency of oscillation may be incorrect.
- injection of a signal at 1 ⁇ 3 the ILO frequency can be used to lengthen or shorten the time of one state (e.g., state 0 ) to make the average frequency correct as shown in FIG. 4 .
- state 0 can be shortened when free running is slow; whereas, state 0 can be lengthened when free running is fast.
- the desired frequency is known and is represented by the Frequency Control Word (FCW) as shown in the first row of the histogram, labeled calibration.
- the objective is, based on the histogram data about these states, to control the frequency of the ILO 18 to ensure that the time in all states is equal. This will result in a difference between the injected cycle period and free running periods when the ILO 18 is not fully calibrated.
- FIG. 5 shows a schematic enabling background calibration in accordance with aspects of the present disclosure.
- the injection from the PLL/DCO 12 is enabled via the input divider 14 .
- the post divider, quadrature generation and phase correction shown in FIG. 1 are active but not in the loop shown in FIG. 5 .
- the ILO regulator output remains fixed at the startup value.
- the output of the PLL/DCO is provided to the divider 14 , which is then injected as an input to the ILO 18 .
- the ILO output is 3 ⁇ its input frequency, which is used to clock the TDC 3 state counter 30 (e.g., ILO TDC of FIG. 1 ).
- the ILO TDC 30 samples the output periodically and generates a histogram (as shown in FIG. 4 ) of how much time is spent in the injection cycle or free running cycles.
- the output of the counter 30 is sampled by the output of the gated ring oscillator (GRO) 32 (e.g., ILO GRO of FIG.
- GRO gated ring oscillator
- the ILO TDC sampling clock is uncorrelated with the ILO clock (noise helps to randomize the TDC samples) by using the internal GRO 45 .
- the sample number in each state is the same by tuning the fine control (back-gate) 40 (e.g., ILO back gate of FIG. 1 ).
- Row 7 shows the input frequency is from 6.160 GHz to 7.84 GHz. This is driven into a divide by 8 resulting in an output frequency of 0.770 GHz to 0.980 GHz. This then is passed to the ILO which generates a X3 output, taking the frequency from 2.310 GHz to 2.940 GHz, which is then followed by a divide by 1 to the output.
- the resulting division of the DCO frequency from 7.840 GHz to 2.940 GHz for example, is a number of 2.6666 recurring.
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Abstract
Description
TABLE 1 | ||||||||
Min | Max | Min | Max | Min | Max | |||
(Ghz) | (GHz) | Divide | (Ghz) | (GHz) | Multiply | (Ghz) | (GHz) | |
6.160 | 7.840 | 8 | 0.770 | 0.980 | 3 | 2.310 | 2.940 | |
6.160 | 7.840 | 10 | 0.616 | 0.784 | 3 | 1.848 | 2.352 | |
6.160 | 7.840 | 11 | 0.560 | 0.713 | 3 | 1.680 | 2.138 | |
6.160 | 7.840 | 13 | 0.474 | 0.603 | 3 | 1.422 | 1.809 | |
6.160 | 7.840 | 14 | 0.440 | 0.560 | 3 | 1.320 | 1.680 | |
6.160 | 7.840 | 8 | 0.770 | 0.980 | 3 | 2.310 | 2.940 | |
6.160 | 7.840 | 10 | 0.616 | 0.784 | 3 | 1.848 | 2.352 | |
6.160 | 7.840 | 11 | 0.560 | 0.713 | 3 | 1.680 | 2.138 | |
6.160 | 7.840 | 13 | 0.474 | 0.603 | 3 | 1.422 | 1.809 | |
6.160 | 7.840 | 14 | 0.440 | 0.560 | 3 | 1.320 | 1.680 | |
Post | ||||||||
Divide | Review | |||||||
Min | Max | Min | Max | Multi- | ||||
(Ghz) | (GHz) | Divide | (Ghz) | (GHz) | MOD | plication | Overlap | |
6.160 | 7.840 | 1 | 2.310 | 2.940 | 0.667 | 2.667 | ||
6.160 | 7.840 | 1 | 1.848 | 2.352 | 0.333 | 3.333 | 42.000 | MHz |
6.160 | 7.840 | 1 | 1.680 | 2.138 | 0.667 | 3.667 | 290.182 | MHz |
6.160 | 7.840 | 1 | 1.422 | 1.809 | 0.333 | 4.333 | 129.231 | MHz |
6.160 | 7.840 | 1 | 1.320 | 1.680 | 0.667 | 4.667 | 258.462 | MHz |
6.160 | 7.840 | 2 | 1.155 | 1.470 | 0.333 | 5.333 | 150.000 | MHz |
6.160 | 7.840 | 2 | 0.924 | 1.176 | 0.667 | 6.667 | 21.000 | MHz |
6.160 | 7.840 | 2 | 0.840 | 1.069 | 0.333 | 7.333 | 145.091 | MHz |
6.160 | 7.840 | 2 | 0.711 | 0.905 | 0.667 | 8.667 | 64.615 | MHz |
6.160 | 7.840 | 2 | 0.660 | 0.840 | 0.333 | 9.333 | 129.231 | MHz |
Claims (19)
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US15/801,735 US10439623B2 (en) | 2017-05-30 | 2017-11-02 | Injection locked oscillator system and processes |
TW107106797A TWI653832B (en) | 2017-05-30 | 2018-03-01 | Injection locked oscillator system and processes |
DE102018203378.1A DE102018203378A1 (en) | 2017-05-30 | 2018-03-07 | Injection synchronized oscillator system and processes |
CN201810311075.XA CN108988855B (en) | 2017-05-30 | 2018-04-09 | Injection locked oscillator system and method |
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US201762512391P | 2017-05-30 | 2017-05-30 | |
US15/801,735 US10439623B2 (en) | 2017-05-30 | 2017-11-02 | Injection locked oscillator system and processes |
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US (1) | US10439623B2 (en) |
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CN110209625B (en) * | 2019-04-11 | 2020-08-11 | 浙江大学 | On-chip synchronous self-repairing system based on low-frequency reference signal |
CN110635801B (en) * | 2019-10-26 | 2023-02-10 | 复旦大学 | Injection locking clock frequency multiplier for suppressing reference stray |
CN110784178B (en) * | 2019-10-28 | 2021-05-11 | 东南大学 | Broadband injection locking frequency multiplier |
US10797683B1 (en) * | 2020-03-06 | 2020-10-06 | Faraday Technology Corp. | Calibration circuit and associated calibrating method capable of precisely adjusting clocks with distorted duty cycles and phases |
WO2022026549A1 (en) * | 2020-07-29 | 2022-02-03 | Sync Computing Corp. | Optimization processing unit utilizing digital oscillators |
CN112688685B (en) * | 2020-12-24 | 2022-03-15 | 深圳市中承科技有限公司 | Voltage controlled oscillator frequency calibration device, method and storage medium |
US11967966B2 (en) * | 2021-10-14 | 2024-04-23 | Zhejiang University | Circuit and method for expanding lock range of injection-locked oscillators |
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- 2018-03-01 TW TW107106797A patent/TWI653832B/en not_active IP Right Cessation
- 2018-03-07 DE DE102018203378.1A patent/DE102018203378A1/en not_active Withdrawn
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Title |
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P. Park, J. Park, H. Park and S. Cho, "An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS," 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2012, 2 pages. |
Taiwanese Notice of Allowance in related TW Application No. 107106797 dated Jan. 19, 2019, 4 pages. |
Taiwanese Office Action in related TW Application No. 107106797 dated Oct. 2, 2018, 8 pages. |
Also Published As
Publication number | Publication date |
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TWI653832B (en) | 2019-03-11 |
CN108988855B (en) | 2022-09-09 |
US20180351563A1 (en) | 2018-12-06 |
CN108988855A (en) | 2018-12-11 |
DE102018203378A1 (en) | 2018-12-06 |
TW201902128A (en) | 2019-01-01 |
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