CN110199579A - 电子模块以及电子模块的制造方法 - Google Patents

电子模块以及电子模块的制造方法 Download PDF

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Publication number
CN110199579A
CN110199579A CN201780084128.2A CN201780084128A CN110199579A CN 110199579 A CN110199579 A CN 110199579A CN 201780084128 A CN201780084128 A CN 201780084128A CN 110199579 A CN110199579 A CN 110199579A
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Prior art keywords
substrate
union body
electronic component
electronic module
union
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CN201780084128.2A
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CN110199579B (zh
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松嵜理
池田康亮
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Abstract

电子模块具有:第一基板11;电子元件13、23,设置在所述第一基板11的一侧;第二基板21,设置在所述电子元件13、23的一侧;第一连结体210,设置在所述第一基板11与所述第二基板21之间;第二连结体220,设置在所述第一基板11与所述第二基板21之间,且长度比所述第一连结体210更短;以及封装部90,至少封装所述电子元件,其中,所述第一连结体210未与所述电子元件电连接,所述第二连结体220与所述电子元件13、23电连接。

Description

电子模块以及电子模块的制造方法
技术领域
本发明涉及电子模块以及电子模块的制造方法,该电子模块具有第一基板与第二基板、以及设置在第一基板与第二基板之间的电子元件。
背景技术
以往,在封装树脂内设置有多个电子元件的电子模块已被普遍认知(例如,参照特开2014-45157号)。对于这种电子模块,行业普遍希望能将其小型化。
但是包含在电子模块中的电子元件的数量一旦变多,电子模块的第一基板以及与第一基板相向设置的第二基板在面方向上的大小就会变大。因此,一旦第一基板以及第二基板的大小变大,那么在焊接工序、回流工序等热处理工序中,该第一基板以及第二基板有时就会翘曲变形。
此外,在将电子模块通过封装树脂等进行封装的情况下,第一基板以及第二基板会被模具按压。由于在包含第一基板以及第二基板的构件中存在有公差,因此在组装电子模块的部件时的厚度方向上的厚度有时也会变得大于模具的厚度方向上的大小。在这种情况下一旦受到来自模具的强按压力,会有发生电气故障的可能性。
鉴于上述课题,本发明的目的,是提供一种能够防止第一基板以及第二基板产生翘曲或变形,此外还能够降低发生电气故障可能性的电子模块以及电子模块的制造方法。
发明内容
本发明涉及的电子模块的特征在于,包括:
第一基板;
电子元件,设置在所述第一基板的一侧;
第二基板,设置在所述电子元件的一侧;
第一连结体,设置在所述第一基板与所述第二基板之间;
第二连结体,设置在所述第一基板与所述第二基板之间,且长度比所述第一连结体更短;以及
封装部,至少封装所述电子元件,
其中,所述第一连结体未与所述电子元件电连接,
所述第二连结体与所述电子元件电连接。
在本发明涉及的电子模块中,
所述第二连结体具有弹性构造。
在本发明涉及的电子模块中,
所述第一连结体具有主体部以及横截面积比所述主体部更小的结合部。
在本发明涉及的电子模块中,
所述第一连结体具有横截面积为连续变小的倾斜部。
在本发明涉及的电子模块中,
所述第一连结体被设置多个,
所述第二连结体也被设置多个。
在本发明涉及的电子模块中,
所述第一连结体与所述第二连结体构成一对的组合。
在本发明涉及的电子模块中,
所述第一连结体与所述第二连结体被设置为相同的数量。
在本发明涉及的电子模块中,
所述第一连结体通过导电性粘合剂与设置在所述第一基板上的第一导体层或所述第一基板相连结,且所述第一连结体通过导电性粘合剂与设置在所述第二基板上的第二导体层或所述第二基板相连结,
所述第二连结体通过导电性粘合剂与设置在所述第一基板上的所述第一导体层或所述第一基板相连结,且所述第二连结体通过导电性粘合剂与设置在所述第二基板上的所述第二导体层或所述第二基板相连结,
与所述第二连结体接触的所述导电性粘合剂的厚度比接触于所述第一连结体的所述导电性粘合剂的厚度更厚。
在本发明涉及的电子模块中,
所述第二连结体被设置在:所述电子元件与所述第二基板之间、所述电子元件与所述第一基板之间、或设置在所述第一基板侧的第一电子元件与设置在所述第二基板侧的第二电子元件之间。
在本发明涉及的电子模块中,
所述第二连结体相比所述第一连结体是被配置在边缘内侧。
本发明涉及的电子模块的制造方法的特征在于,包括:
在第一基板的一侧设置电子元件的工序;
在所述第一基板与第二基板之间设置未与所述电子元件电连接的第一连结体的工序;
在所述第一基板与所述第二基板之间设置长度比所述第一连结体更短且与所述电子元件电连接的第二连结体的工序;以及
在所述第一基板与所述第二基板之间提供封装树脂,并将所述电子元件、所述第一连结体以及所述第二连结体以所述封装树脂进行封装的工序。
发明效果
根据本发明的一种形态,由于设置有第一连结体以及第二连结体,所以能够防止第一基板以及第二基板产生翘曲或变形。此外,未与电子元件电连接的第一连结体比与电子元件电连接的第二连结体的长度更长。因此,即使是在受到来自模具的按压力的情况下,也能够以第一连结体来承受按压力。这样一来,就能够防止在与电子元件电连接的且发挥电气功能的第二连结体中发生故障,进而能够在电子模块中降低发生电气故障的可能性。
附图说明
图1是在本发明的第一实施方式中所使用的电子模块的纵截面图。
图2是在本发明的第一实施方式中所使用的电子模块的另一个纵截面图。
图3是展示在本发明的第一实施方式中所使用的第一连结体以及第二连结体的平面图。虽然实际上无法看见封装部内的第一连结体以及第二连结体,但是在图3中展示了位于封装部内的第一连结体以及第二连结体。
图4是展示在本发明的第一实施方式中所使用的第一连结体以及第二连结体的另一个平面图。虽然实际上无法看见封装部内的第一连结体以及第二连结体,但是在图4中也展示了位于封装部内的第一连结体以及第二连结体。
图5是展示在本发明的第一实施方式中所使用的第一连接体、第一电子元件以及第二电子元件的平面图。
图6(a)-(e)是展示在本发明的第一实施方式中所使用的芯片模块的制造工序的纵截面图。
图7(a)-(c)是展示在本发明的第一实施方式中所使用的电子模块的制造工序的纵截面图。图7(a)-(c)展示了与图1对应的纵截面。
图8是在本发明的第二实施方式中所使用的电子模块的纵截面图。
图9(a)-(d)是在本发明的第二实施方式中所使用的第二连结体的纵截面图。
图10(a)(b)是在本发明的第三实施方式中所使用的第二连结体的纵截面图。
图11(a)(b)是在本发明的第四实施方式中所使用的第二连结体的纵截面图。
图12是展示在本发明的第五实施方式中所使用的第一连接体、第一电子元件以及第二电子元件的平面图。
图13是用于展示在本发明的第六实施方式中所使用的第一连接体以及第二连接体的纵截面图。
图14是在本发明的第八实施方式中所使用的电子模块的纵截面图。
图15是在本发明的第八实施方式中所使用的另一种形态下的电子模块的纵截面图。
图16是在本发明的第九实施方式中所使用的电子模块的纵截面图。
具体实施方式
第一实施方式
《构成》
在本实施方式中,“一侧”是指图1的上端侧,“另一侧”是指图1的下端侧。将图1的上下方向称为“第一方向”,将左右方向称为“第二方向”,将纸面的表里方向称为“第三方向”。将包含第二方向以及第三方向的面内方向称为“面方向”,将从一侧进行观看的情况称为“平面观看”。
本实施方式的电子模块具有第一电子单元以及第二电子单元。
如图1所示,第一电子单元具有:第一基板11、设置在第一基板11的一侧的多个第一导体层12、以及设置在第一导体层12的一侧的第一电子元件13。第一电子元件13可以是开关元件,也可以是控制元件。当第一电子元件13是开关元件时,第一电子元件13可以是MOSFET或IGBT。此外,也能够使用二极管、晶体管、闸流管等来作为第一电子元件13。第一电子元件13以及后述的第二电子元件23可以各自由半导体元件所构成,作为半导体材料可以是硅、碳化硅、氮化镓等。第一电子元件13可以通过焊锡等导电性粘合剂5与第一导体层12相连接。
如图2所示,在第一电子元件13的一侧设置有第一连接体60。第一连接体60通过焊锡等导电性粘合剂5(在图2中没有进行展示)与第一电子元件13相连接。
如图1所示,第二电子单元具有第二基板21以及设置在第二基板21的另一侧的第二导体层22。第二电子元件23通过焊锡等导电性粘合剂5设置在第二基板21上。
如图2所示,第一连接体60的一侧设置有第二电子元件23。第二导体层22的另一侧设置有第二连接体70。第二连接体70通过焊锡等导电性粘合剂5与第二电子元件23以及第二导体层22相连接。
第二电子元件23可以是开关元件,也可以是控制元件。当第二电子元件23是开关元件时,第二电子元件23可以是MOSFET或IGBT。此外,也能够使用二极管、晶体管、闸流管等来作为第二电子元件23。
如图2所示,第一连接体60具有第一头部61以及从第一头部61向另一侧延伸的第一柱部62。第二连接体70具有第二头部71以及从第二头部71向另一侧延伸的第二柱部72。第一连接体60的截面大致呈T字形,第二连接体70的截面也是大致呈T字形。
作为第一基板11以及第二基板21,能够采用陶瓷基板、绝缘树脂层等。作为导电性粘合剂5,除了焊锡以外也能够使用将Ag或Cu作为主成分的材料。作为第一连接体60以及第二连接体70的材料能够使用Cu等金属。此外,作为基板11、21也能够使用例如是施加过电路图案的金属基板,这时,基板11、21兼作为导体层12、22。另外,作为金属基板与导体层12、22,能够使用铜、铝,钼等。
电子模块具有由封装树脂等构成的封装部90,该封装部90封装:所述过的第一电子元件13、第二电子元件23、第一连接体60、第二连接体70、第一导体层12、第二导体层22等。
如图1所示,端子部110、120具有与第一电子元件13电连接的第一端子部110以及与第二电子元件23电连接的第二端子部120。
第一导体层12可以通过导电性粘合剂5与第一端子部110相连接,第一端子部110的前端侧在向封装部90的外侧露出后,也能够与外部装置相连接。第二导体层22可以通过导电性粘合剂5与第二端子部120相连接,第二端子部120的前端侧在向封装部90的外侧露出后,也能够与外部装置相连接。第一端子部110的前端以及第二端子部120的前端还可以向一侧或另一侧弯曲。
在图1中,虽然展示了第一端子部110以及第二端子部120是呈直线形的形态,但也不限于此,第一端子部110也可以具有:与第一导体层12相连接的第一端子基端部、向封装部90的外侧露出后的第一端子外侧部、以及设置在第一端子基端部与第一端子外侧部之间的且在第一端子基端部侧向另一侧弯曲的第一弯曲部。第一端子基端部可以通过导电性粘合剂5与第一导体层12相连接。
第二端子部120可以具有:与第二导体层22相连接的第二端子基端部、向封装部90的外侧露出后的第二端子外侧部、以及设置在第二端子基端部与第二端子外侧部之间的且在第二端子基端部侧向一侧弯曲的第二弯曲部。第二端子基端部可以通过导电性粘合剂5与第二导体层22相连接。
在第一基板11与第二基板21之间设置有第一连结体210以及长度比第一连结体210更短的第二连结体220。第一连结体210未与电子元件13、23电连接,第二连结体220与电子元件13、23电连接。第一连结体210例如可以通过导体层12、22与电子元件13、23电连接。此外,也可以不限于这种形态,还能够采用第一连结体210与第二连结体220是成为实质性相同长度的形态。此处的成为实质性相同长度是指:第一连结体210与第二连结体220的长度差在两者中的长度为较长一方的5%以内。因此,在将第一连结体210与第二连结体220中的长度为较长一方的长度作为L1,将较短一方的长度作为L0的情况下,在成为L1-L0≦L1×0.05时,就可以说在本实施方式中的第一连结体210与第二连结体220是实质性相同的长度。
第一连结体210在第一方向上的长度可以是与第一基板11以及第二基板21的设计高度(在第一方向上的间隔)相对应的长度。此处的“与设计高度相对应的长度”是指:在设计高度的±5%以内。此外,在将成为封装部90的封装树脂注入于模具内时,第一基板11以及第二基板21或后述的第一散热板151以及第二散热板152会被模具从一侧进行按压。
第一连结体210可以由圆柱形、角柱形等柱形所构成。第二连结体220也同样可以由圆柱形、角柱形等柱形所构成。第一连结体210与第二连结体220的形状可以无需相同,第一连结体210可以由圆柱形所构成而第二连结体220则可以由角柱形所构成,还可以第一连结体210是由角柱形所构成而第二连结体220则是由圆柱形所构成。
第一连结体210可以只设置一个,也可以如图3以及图4所示般设置多个。同样地,第二连结体220也可以只设置一个,还可以如图3以及图4所示般设置多个。如图3所示,第一连结体210与第二连结体220可以设置为相同数量且构成一对的组合。此处的“构成一对的组合”是指:在面方向上设置一个相对于第一连结体210是位于最短距离的第二连结体220,从而第一连结体210与第二连结体220成为一对。
第二连结体220相比第一连结体210可以被配置在边缘内侧。当采用多个第二连结体220时,第二连结体220相比第一连结体210可以各自被定位在边缘内侧。只是,也可以不限于这种形态,第二连结体220相比第一连结体210还可以被配置在边缘外侧。此外,边缘内侧是指:在面方向上相距封装部90的边缘端部的距离较远,第二连结体220相比第一连结体210被配置在边缘内侧是指:从第二连结体220观看到的到达封装部90的边缘端部的距离比从第一连结体210观看到的到达封装部90的边缘端部的距离更远。
至少一个第一连结体210通过导电性粘合剂5与设置在第一基板11上的第一导体层12或由金属基板所构成的第一基板11相连结,且也可以通过导电性粘合剂5与设置在第二基板21上的第二导体层22或由金属基板所构成的第二基板21相连结。
至少一个第二连结体220通过导电性粘合剂5与设置在第一基板11上的第一导体层12或由金属基板所构成的第一基板11相连结,且也可以通过导电性粘合剂5与设置在第二基板21上的第二导体层22或由金属基板所构成的第二基板21相连结。
如图1所示,与第一连结体210接触的导电性粘合剂5的厚度比接触于第二连结体220的导电性粘合剂5的厚度更薄。此外,在当第一连结体210以及第二连结体220是以同样的形态通过导电性粘合剂5与第一导体层12或由金属基板所构成的第一基板11相连结,且通过导电性粘合剂5与第二导体层22或由金属基板所构成的第二基板21相连结的情况下,由于第二连结体220的长度比第一连结体210更短,因此几乎必然地就能够将与第二连结体220相接触的导电性粘合剂5的厚度设为比接触于第一连结体210的导电性粘合剂5的厚度更厚。由于第二连结体220与电子元件电连接,因此通过这样充分持有导电性粘合剂5的厚度,从而就能够实现较高的可靠性。
如图5所示,在第一头部61的一侧的面上设置有第一沟部64。虽然第一沟部64在平面上观看(面方向)是设置在第一柱部62的边缘外侧,但是其也可以设置在边缘外侧的一部分上,还可以设置在第一柱部62的整个边缘外侧上。在第一头部61的一侧的面上的第一沟部64的边缘内侧设置有焊锡等导电性粘合剂5,且可以通过导电性粘合剂5来设置第二电子元件23。
如图5所示,在平面上观看时第一电子元件13是从第一头部61向外侧露出的形态。当第一电子元件13是MOSFET等开关元件时,可以在从外侧露出后的部分上设置第一栅极端子13g等。同样地,当第二电子元件23是MOSFET等开关元件时,可以在一侧的面上设置第二栅极端子23g等。图5所示的第一电子元件13在一侧的面上具有第一栅极端子13g与第一源极端子13s,第二电子元件23在一侧的面上具有第二栅极端子23g与第二源极端子23s。这时,第二连接体70通过导电性粘合剂5与第二电子元件23的第二源极端子23s相连接,且未图示的连接件也可以通过导电性粘合剂5与第二电子元件23的第二栅极端子23g相连接。此外,第一连接体60可以通过导电性粘合剂5将第一电子元件13的第一源极端子13s与设置在第二电子元件23的另一侧的第二漏极端子相连接。设置在第一电子元件13的另一侧的第一漏极端子可以通过导电性粘合剂5与第一导体层12相连接。第一电子元件13的第一栅极端子13g通过导电性粘合剂5与未图示的连接件相连接,且该连接件95也可以通过导电性粘合剂5与第一导体层12相连接。
当仅是第一电子元件13以及第二电子元件23中的任意一方为开关元件的情况下,也可以考虑将放置在第一连接体60上的第二电子元件23作为发热性较低的控制元件,将第一电子元件13设为开关元件。还可以考虑相反地将放置在第一连接体60上的第二电子元件23作为开关元件,将第一电子元件13设为发热性较低的控制元件。
端子部110、120与导体层12、22之间的接合不仅可以是使用焊锡等导电性粘合剂5的方式,也可以使用激光焊接,还可以使用超音波接合。端子部110、120可以设置在与第一连结体210或第二连结体220相反侧的边缘侧部。作为其中一例,如图1所示,可以构成为:在第二连结体220的边缘外侧设置有第一连结体210,在与第一连结体210以及第二连结体220是相反侧的边缘侧部设置有端子部110、120,且该端子部向封装部90的边缘外侧突出。
如图1以及图2所示,在第一基板11的另一侧(背面侧)设置有由铜基板等构成的第一散热板151。同样地,在第二基板12的一侧(背面侧)设置有由铜基板等构成的第二散热板152。
《制造方法》
下面,对本实施方式的电子模块的制造方法的一例进行说明。
首先,将第一电子元件13配置在第一夹具500上(第一电子元件配置工序,参照图6(a))。此外,图6展示了与图2是不同的芯片模块的制造工序,例如第二电子元件23是成为在面方向上收纳于第一连接体60内的大小。
接着,通过焊锡等导电性粘合剂5将第一连接体60配置在第一电子元件13上(第一连接体配置工序,参照图6(b))。此外,在图6中未展示焊锡等导电性粘合剂5。
其次,通过导电性粘合剂5将第二电子元件23配置在第一连接体60上(第二电子元件配置工序,参照图6(c))。此外,第一连接体60上的导电性粘合剂5被配置在第一电子元件13的第一沟部64的边缘内侧。
将第二连接体70配置在第二夹具550上(第二电子元件配置工序,参照图6(d))。第二夹具550在配置有第二连接体70的位置上具有多个夹具凹部560。夹具凹部560的高度可以与芯片模块的高度相对应。此外,夹具凹部560的高度与芯片模块的高度相对应是指:夹具凹部560所具有的高度是大于等于也考虑到导电性粘合剂5的厚度的芯片模块的整体设计上的厚度。
使用吸附构件等使第二连接体70在吸附于第二夹具550的状态下使第二夹具550翻转后,通过导电性粘合剂5将第二连接体70配置在第二电子元件23上(翻转放置工序,参照图6(e))。
接着,对导电性粘合剂5进行加热在使其融化后再使其硬化(使其回流)(第一硬化工序)。通过这样制造具有第一电子元件13以及第二电子元件23的芯片模块。
下面,对制造电子模块的方法进行说明。其中,在图7中未展示芯片模块。
将芯片模块的第一电子元件13通过导电性粘合剂5来放置在设置于第一基板11上的第一导体层12上(芯片模块放置工序)。
在进行芯片模块放置工序的同时或在其前后,通过导电性粘合剂5将第一电子元件13放置在第一导体层12上(第一电子元件放置工序,参照图7(a))。通过导电性粘合剂5将连接件95放置在第一电子元件13以及第一导体层12上。
在进行第一电子元件放置工序的同时或在其前后,通过导电性粘合剂5将第一连结体210设置在第一基板11的正面侧的第一导体层12上(第一连结体放置工序,参照图7(a))。
在进行第一连结体放置工序的同时或在其前后,通过导电性粘合剂5将第二连结体220设置在第一基板11的正面侧的第一导体层12上(第二连结体放置工序,参照图7(a))。
在进行第二连结体放置工序的同时或在其前后,通过导电性粘合剂5将第一端子部110设置在第一基板11的正面侧的第一导体层12上。
通过导电性粘合剂5将第二电子元件23设置在第二基板21的正面侧的第二导体层22上(第二电子元件放置工序,参照图7(b))。
在进行第二电子元件放置工序的同时或在其前后,通过导电性粘合剂5将第二端子部120设置在第二基板21的正面侧的第二导体层22上。
随后,对设置在第一基板11侧以及第二基板21侧的导电性粘合剂5进行加热在使其融化后再使其硬化(使其回流)。
接着,在使第二基板21翻转后,通过导电性粘合剂5将第一连结体210以及第二连结体220连接在第二基板21的第二导体层22上(翻转工序,参照图7(c))。这时,通过导电性粘合剂5将第二导体层22连接在芯片模块的第二连接体70上。
其次,在第一基板11与第二基板21之间提供封装树脂,并将芯片模块、第一电子元件13、第二电子元件23、第一连结体210、第二连结体220等以封装树脂进行封装,从而形成封装部90(封装工序,参照图7(c))。
通过上述内容来制造本实施方式的电子模块。
《作用·效果》
下面,对由上述构造所构成的本实施方式的作用·效果的一例进行说明。此外,能够在上述构成中采用在“作用·效果”中说明的所有形态。
在本实施方式中,当采用设置有第一连结体210以及第二连结体220的形态时,能够防止第一基板11以及第二基板21产生翘曲或变形。具体来说,由于在制造电子模块的工序中会加入热量,因此第一基板11以及第二基板21就会有翘曲变形的可能性。例如,由于在焊接工序、回流工序等工序中会加入热量,因此第一基板11以及第二基板21就会有翘曲变形的可能性。对于这点,当采用设置有第一连结体210以及第二连结体220的形态时,就能够防止第一基板11以及第二基板21产生这种翘曲或变形。此外,由于第一基板11以及第二基板21在面方向上的大小越大这种翘曲以及变形就越大,因此在这种情况下,使用本实施方式的第一基板11以及第二基板21是非常有帮助的。
此外,即使是采用第一连接体60或第二连接体70也能够防止第一基板11以及第二基板21产生翘曲或变形。另外,通过采用第一连接体60或第二连接体70,还能够使从第一电子元件13或第二电子元件23产生的热量有效地散热。
由于在包含第一基板11以及第二基板21的构件中存在有公差,因此在组装电子模块的部件时的厚度方向(第一方向)上的厚度有时也会变得大于模具的厚度方向上的大小。在这时一旦受到来自模具的强按压力,会有发生电气故障的可能性。对于这点,当采用未与电子元件电连接的第一连结体210是比与电子元件电连接的第二连结体220的长度更长的形态时,即使是在受到来自模具的按压力的情况下,也能够以第一连结体210来承受按压力。这样一来,就能够防止在与电子元件电连接且发挥电气功能的第二连结体220中发生故障,进而能够在电子模块中降低发生电气故障的可能性。
从在受到来自模具的强按压力的情况下允许第一连结体210发生破损来看,采用第一连结体210相比第二连结体220是被配置在边缘外侧的形态是有帮助的。鉴于第一基板11以及第二基板21所产生的翘曲或变形的效果,其有很高的可能性是由于在边缘外侧施加了较大的力。
与第二连结体220接触的导电性粘合剂5的厚度比接触于第一连结体210的导电性粘合剂5的厚度更厚。由于第二连结体220与电子元件电连接,因此通过这样充分持有导电性粘合剂5的厚度,对于能够实现较高的可靠性是有帮助的。
如图3以及图4所示,在采用设置有多个第一连结体210的形态时,对于能够更为准确地防止第一基板11以及第二基板21产生翘曲或变形是有帮助的。作为其中一例,第一连结体210至少设置大于等于四个,且被设置为能够支撑第一基板11以及第二基板21的四个角部。
如图3以及图4所示,在采用设置有多个第二连结体220的形态时,对于能够更为准确地防止第一基板11以及第二基板21产生翘曲或变形也是有帮助的。作为其中一例,第二连结体220至少设置大于等于四个,且被设置为能够支撑第一基板11以及第二基板21的四个角部。
在采用第一连结体210与第二连结体220是构成一对的组合的形态时,通过第一连结体210对于能够防止因第一基板11以及第二基板21的翘曲或变形所引起的按压力施加在对应的第二连结体220(成为组合后的第二连结体220)上是有帮助的。此外,在考虑到对于第二连结体220的影响,第一连结体210的数量成为比第二连结体220的数量更多的形态是有帮助的。另一方面,由于第一连结体210是不发挥电气功能的部件,因此对于抑制其数量也是有帮助的。所以,在从抑制对于第二连结体220的影响的同时,将不发挥电气功能的部件的数量设为不多的观点来看,第一连结体210与第二连结体220被设置为相同数量的形态是有帮助的。如图4所示,第二连结体220的数量也可以比第一连结体210的数量更多。
第二实施方式
下面,对本发明的第二实施方式进行说明。
在第一实施方式中,第二连结体220是由圆柱形、角柱形等柱形所构成的形态。在本实施方式中,第二连结体220是如图8所示般具有弹性构造的形态。关于除此以外的其他构成,则与第一实施方式相同且能够采用在第一实施方式中说明过的所有形态。对在第一实施方式中说明过的构件使用相同符号来进行说明。
作为弹性构造能够采用各种形态。作为其中一例,在沿第一方向的纵截面上,可以是如图8所示般的Z形构造,也可以是如图9(a)所示般的C形构造,还可以是如图9(b)所示般的M形构造。
在采用本实施方式般的第二连结体220是具有弹性构造的形态时,即使是在向第二连结体220施加按压力等的情况下,也能够通过第二连结体220自身来吸收该按压力。因此,能够防止在第二连结体220自身发生较大的故障。从而就能够更为降低在电子模块中发生电气故障的可能性。
如图9(c)(d)所示,在第二连结体220的一侧端部的面上设置有向一侧突出后的突出部225。同样地,在第二连结体220的另一侧端部的面上设置有向另一侧突出后的突出部225。在设置这种突出部225的情况下,对于能够确保导电性粘合剂5的厚度是有帮助的。由于在向第二连结体220施加按压力时导电性粘合剂5会被压碎,因此会有无法充分确保导电性粘合剂5的厚度的可能性。对于这点,通过设置本实施方式般的突出部225,对于能够更为准确地确保导电性粘合剂5的充分厚度是有帮助的。此外,突出部225可以被设置在仅是第二连结体220的一侧端部的面以及另一侧端部的面中的任意一方上。
第三实施方式
下面,对本发明的第三实施方式进行说明。
在上述各实施方式中,第一连结体210是由圆柱形、角柱形等柱形所构成的形态。在本实施方式中,如图10所示,第一连结体210是具有主体部215以及横截面积比主体部215更小的结合部216的形态。在本实施方式中,能够采用在上述各实施方式中说明过的所有形态。对在上述各实施方式中说明过的构件使用相同符号来进行说明。
在采用本实施方式般的横截面积为较小的结合部216的情况下,在从第一基板11、第二基板21等沿着第一方向施加过度的力时,能够使第一连结体210在结合部216断裂。因此,能够防止过度的力通过第一连结体210运作在第一基板11或第二基板21上。虽然第一连结体210是为了防止第一基板11以及第二基板21的翘曲或变形而设置的,但是通过该第一连结体210会对第一基板11或第二基板21施加过度的力,进而会有对第一基板11或第二基板21产生故障的可能性。通过采用本实施方式般的结合部216,在施加有过度的力的情况下,能够使第一连结体210在结合部216断裂,进而能够防止过度的力通过第一连结体210运作在第一基板11或第二基板21上。
主体部215以及结合部216能够采用各种形状。作为其中一例,主体部215可以是具有后述的倾斜部217的构造(参照图10(a)),也可以是具有圆柱形、角柱形等柱形的构造(参照图10(b))。作为结合部216能够是采用例如具有圆柱形、角柱形等柱形的构造,也可以是具有倾斜部的构造。
第四实施方式
下面,对本发明的第四实施方式进行说明。
在本实施方式中,如图11所示,第一连结体210是具有横截面积为连续变小的倾斜部217的形态。即使是本实施方式,也能够采用在上述各实施方式中说明过的所有形态。对在上述各实施方式中说明过的构件使用相同符号来进行说明。
如所述般,虽然第一连结体210是为了防止第一基板11以及第二基板21的翘曲或变形而设置的,但是通过该第一连结体210会对第一基板11或第二基板21施加过度的力,进而会有对第一基板11或第二基板21产生故障的可能性。通过采用本实施方式般的倾斜部217,在施加过度的力时,第一连结体210的一部分会在倾斜部217中的横截面(面方向上的截面)为较小的部位上被压碎,对于能够防止过度的力通过第一连结体210运作在第一基板11或第二基板21上是有帮助的。此外,在图11(a)所示的形态中,横截面为较小的部位是位于前端侧(图11(a)的上端侧)的部分(前端部),在图11(b)所示的形态中,横截面为较小的部位是位于中央部(图11(b)的上下方向的中心部)的部分(中央部)。
第五实施方式
下面,对本发明的第五实施方式进行说明。
在上述各实施方式中,虽然使用的是截面为大致呈T字形的第一连接体60,但是本实施方式的第一连接体60如图12所示,具有从第一头部61向另一侧延伸的四个支撑部65(65a-65d)。支撑部65与第一导体层12或第一基板11相抵接。即使是本实施方式,也能够采用在上述各实施方式中说明过的所有形态。对在上述各实施方式中说明过的构件使用相同符号来进行说明。
在本实施方式中虽然是使用四个支撑部65的形态来进行说明的,但是并不限于此,也可以使用大于等于一、二、三或五个的支撑部65。
当设置有本实施方式般的从第一头部61延伸的支撑部65时,能够在第二电子元件23的安装时或安装后,防止第一连接体60因第二电子元件23的重量而发生倾斜。此外,通过这样将支撑部65与第一基板11或第一导体层12相抵接,能够提高散热性。特别是在支撑部65与第一导体层12相抵接的情况下,对于能够更为提高散热效果是有帮助的。
在采用本实施方式般的具有多个支撑部65的第一连接体60时,对于第一基板11以及第二基板21因热量所产生的翘曲或变形能够赋予更强的反弹力。也就是说,虽然如所述般在电子模块的制造工序中由于加入热量从而会施加有使第一基板11以及第二基板21产生翘曲变形的力,但是通过使用具有多个支撑部65的第一连接体60,在除了第一连结体210的作用以外,对于第一连接体60能够通过第二电子元件23、第二连接体70、第三连接体80、连接件85等来更为准确地防止第一基板11以及第二基板21产生翘曲或变形也是有帮助的。
第六实施方式
下面,对本发明的第六实施方式进行说明。
在上述各实施方式中,虽然是使用具有第二柱部72的截面是大致呈T字形的第二连接体70进行说明的,但是在本实施方式中,如图13所示,第二连接体70具有从第二头部71向另一侧延伸的延伸部75(75a、75b)。即使是本实施方式,也能够采用在上述各实施方式中说明过的所有形态。对在上述各实施方式中说明过的构件使用相同符号来进行说明。
在本实施方式中虽然是使用两个延伸部75的形态来进行说明的,但是并不限于此,也可以使用大于等于一个或三个的延伸部75。
根据本实施方式,由于设置有延伸部75,因此能够将来自第二电子元件23处的热量有效地进行散热,且第二连接体70也能够实现高散热效果。此外,在设置有本实施方式般的多个延伸部75的情况下,对于能够实现更高的散热效果是有帮助的。
在采用本实施方式般的具有多个延伸部的第二连接体70的情况下,对于第一基板11以及第二基板21因热量所产生的翘曲或变形能够赋予更大的反弹力。也就是说,虽然如所述般在电子模块的制造工序中由于加入热量从而会施加有使第一基板11以及第二基板21产生翘曲变形的力,但是通过使用具有多个延伸部的第二连接体70,在除了第一连结体210的作用以外,对于第二连接体70能够更为准确地防止第一基板11以及第二基板21产生翘曲或变形也是有帮助的。
第七实施方式
下面,对本发明的第七实施方式进行说明。
在上述各实施方式中,虽然是使用第一连接体60以及第二连接体70的形态进行说明的,但是并不限于这种形态。也可以不设置第一连接体60以及第二连接体70。作为其中一例,可以是图1所示的形态,也可以是如图2所示的不设置第一连接体60以及第二连接体70的形态。即使是本实施方式,也能够得到所述的对第一连结体210以及第二连结体220说明过的效果。
第八实施方式
下面,对本发明的第八实施方式进行说明。
在本实施方式中,至少有一个第二连结体220是设置在电子元件13、23与第二基板11、21之间或是设置在相向的电子元件13、23之间的形态。在图14所示的形态中展示了设置有第一电子元件13以及第二电子元件23的形态,在图15所示的形态中展示了设置有第一电子元件13的形态。关于除此以外的其他构成则与第七实施方式相同。即使是本实施方式也能够采用在上述各实施方式中说明过的所有形态。对在上述各实施方式中说明过的构件使用相同符号来进行说明。此外,在图15中虽然展示了只设置第一电子元件13的形态,但是不仅限于此,也能够采用只设置第二电子元件23的形态。
如图14所示,当第二连结体220是设置在第一电子元件13与第二电子元件23之间时,通过第二连结体220能够将第一电子元件13与第二电子元件23电连接。
如图15所示,也能够采用第二连结体220是设置在第一电子元件13与第二基板21之间,且通过第二连结体220能够将第一电子元件13与第二导体层22或由金属基板构成的第二基板21电连接的形态。
同样地,还能够采用第二连结体220是设置在第二电子元件23与第一基板11之间,且通过第二连结体220能够将第二电子元件23与第一导体层12或由金属基板构成的第一基板11电连接的形态。
如已述般,在本实施方式中能够采用在上述各实施方式中说明过的所有形态,并且还能够采用所述的第二连结体220是具有弹性构造的形态(在图14以及图15中展示了这种具有弹性构造的形态)。在采用这种第二连结体220是具有弹性构造的形态时,对于能够防止强按压力施加在电子元件13、23上是有帮助的。
第九实施方式
下面,对本发明的第九实施方式进行说明。
在本实施方式中,仅仅使用了第一电子元件13以及第二电子元件23中的任意一方,关于除此以外的其他构成则与第七实施方式相同。在图16中,虽然展示了只设置第一电子元件13的形态,但是不仅限于此,也能够采用只设置第二电子元件23的形态。即使是本实施方式也能够采用在上述各实施方式中说明过的所有形态。本实施方式也能够得到所述的对第一连结体210以及第二连结体220说明过的效果。
上述记载的各实施方式以及公开的附图只是用于说明权利要求中记载的发明的一例,权利要求中记载的发明不受上述记载的各实施方式或公开的附图所限定。此外,申请最初的记载的权利要求也仅是一例,基于说明书、附图等能够将记载的权利要求进行适当的变更。
符号说明
11 第一基板
12 第一导体层
13 第一电子元件(电子元件)
21 第二基板
22 第二导体层
23 第二电子元件(电子元件)
210 第一连结体
215 主体部
216 结合部
217 倾斜部
220 第二连结体

Claims (11)

1.一种电子模块,其特征在于,包括:
第一基板;
电子元件,设置在所述第一基板的一侧;
第二基板,设置在所述电子元件的一侧;
第一连结体,设置在所述第一基板与所述第二基板之间;
第二连结体,设置在所述第一基板与所述第二基板之间,且长度比所述第一连结体更短;以及
封装部,至少封装所述电子元件,
其中,所述第一连结体未与所述电子元件电连接,
所述第二连结体与所述电子元件电连接。
2.根据权利要求1所述的电子模块,其特征在于:
其中,所述第二连结体具有弹性构造。
3.根据权利要求1或2所述的电子模块,其特征在于:
其中,所述第一连结体具有主体部以及横截面积比所述主体部更小的结合部。
4.根据权利要求1至3中的任意1项所述的电子模块,其特征在于:
其中,所述第一连结体具有横截面积为连续变小的倾斜部。
5.根据权利要求1至4中的任意1项所述的电子模块,其特征在于:
其中,所述第一连结体被设置有多个,
所述第二连结体也被设置有多个。
6.根据权利要求5所述的电子模块,其特征在于:
其中,所述第一连结体与所述第二连结体构成一对组合。
7.根据权利要求6所述的电子模块,其特征在于:
其中,所述第一连结体与所述第二连结体被设置为相同的数量。
8.根据权利要求1至7中的任意1项所述的电子模块,其特征在于:
其中,所述第一连结体通过导电性粘合剂与设置在所述第一基板上的第一导体层或所述第一基板相连结,且所述第一连结体通过导电性粘合剂与设置在所述第二基板上的第二导体层或所述第二基板相连结,
所述第二连结体通过导电性粘合剂与设置在所述第一基板上的所述第一导体层或所述第一基板相连结,且所述第二连结体通过导电性粘合剂与设置在所述第二基板上的所述第二导体层或所述第二基板相连结,
与所述第二连结体接触的所述导电性粘合剂的厚度比接触于所述第一连结体的所述导电性粘合剂的厚度更厚。
9.根据权利要求1至8中的任意1项所述的电子模块,其特征在于:
其中,所述第二连结体被设置在:所述电子元件与所述第二基板之间、所述电子元件与所述第一基板之间、或设置在所述第一基板侧的第一电子元件与设置在所述第二基板侧的第二电子元件之间。
10.根据权利要求1至9中的任意1项所述的电子模块,其特征在于:
其中,所述第二连结体相比所述第一连结体,被配置在边缘内侧。
11.一种电子模块的制造方法,其特征在于,包括:
在第一基板的一侧设置电子元件的工序;
在所述第一基板与第二基板之间设置未与所述电子元件电连接的第一连结体的工序;
在所述第一基板与所述第二基板之间设置长度比所述第一连结体更短且与所述电子元件电连接的第二连结体的工序;以及
在所述第一基板与所述第二基板之间提供封装树脂,并将所述电子元件、所述第一连结体以及所述第二连结体以所述封装树脂进行封装的工序。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6463558B1 (ja) * 2017-05-19 2019-02-06 新電元工業株式会社 電子モジュール、リードフレーム及び電子モジュールの製造方法
IT201700103511A1 (it) * 2017-09-15 2019-03-15 St Microelectronics Srl Dispositivo microelettronico dotato di connessioni protette e relativo processo di fabbricazione
DE102019111964A1 (de) * 2019-05-08 2020-11-12 Danfoss Silicon Power Gmbh Halbleitermodul mit einem ersten Substrat, einem zweiten Substrat und einen Abstandhalter, der die Substrate voneinander trennt
EP3739624A1 (en) * 2019-05-13 2020-11-18 Infineon Technologies Austria AG Semiconductor arrangement with a compressible contact element encapsulated between two carriers and corresponding manufacturing method
US11380646B2 (en) 2020-05-14 2022-07-05 Life-On Semiconductor Corporation Multi-sided cooling semiconductor package and method of manufacturing the same
DE102021209486A1 (de) * 2021-08-30 2023-03-02 Robert Bosch Gesellschaft mit beschränkter Haftung Elektronikanordnung und Verfahren zu deren Herstellung
EP4261872A1 (en) * 2022-04-11 2023-10-18 Nexperia B.V. Molded electronic package with an electronic component encapsulated between two substrates with a spring member between the electronic component and one of the substrates and method for manufacturing the same

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004335624A (ja) * 2003-05-06 2004-11-25 Hitachi Ltd 半導体モジュール
JP2006310649A (ja) * 2005-04-28 2006-11-09 Sharp Corp 半導体装置パッケージおよびその製造方法、ならびに半導体装置パッケージ用一括回路基板
KR100656587B1 (ko) * 2005-08-08 2006-12-13 삼성전자주식회사 금속 포스트를 매개로 연결된 적층 기판을 이용한 적층패키지
JP2007335702A (ja) * 2006-06-16 2007-12-27 Apic Yamada Corp 転写基板の製造方法
US20090190319A1 (en) * 2008-01-24 2009-07-30 Olympus Corporation Three-dimensional module
US20100133684A1 (en) * 2008-11-28 2010-06-03 Mitsubishi Electric Corporation Power semiconductor module and manufacturing method thereof
CN101911845A (zh) * 2007-12-26 2010-12-08 株式会社藤仓 安装基板及其制造方法
JP2012162680A (ja) * 2011-02-08 2012-08-30 Hitachi Chemical Co Ltd 半導体用接着フィルム、接着シート、半導体ウエハ及び半導体装置
CN103515362A (zh) * 2012-06-25 2014-01-15 台湾积体电路制造股份有限公司 堆叠式封装器件和封装半导体管芯的方法
CN104303289A (zh) * 2013-05-13 2015-01-21 新电元工业株式会社 电子模块及其制造方法
CN104347547A (zh) * 2013-07-26 2015-02-11 日月光半导体制造股份有限公司 半导体封装件及其的制造方法
CN205122571U (zh) * 2014-08-27 2016-03-30 株式会社村田制作所 导电柱
KR20170096945A (ko) * 2016-02-17 2017-08-25 가부시기가이샤 디스코 반도체 패키지 및 반도체 패키지의 제조 방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497258A (en) * 1994-05-27 1996-03-05 The Regents Of The University Of Colorado Spatial light modulator including a VLSI chip and using solder for horizontal and vertical component positioning
JP2001267714A (ja) 2000-03-16 2001-09-28 Sony Corp 電子回路装置
US6882546B2 (en) * 2001-10-03 2005-04-19 Formfactor, Inc. Multiple die interconnect system
WO2007013239A1 (ja) * 2005-07-27 2007-02-01 Murata Manufacturing Co., Ltd. 積層型電子部品、電子装置および積層型電子部品の製造方法
US7989707B2 (en) 2005-12-14 2011-08-02 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
US8466543B2 (en) * 2010-05-27 2013-06-18 International Business Machines Corporation Three dimensional stacked package structure
US9704793B2 (en) * 2011-01-04 2017-07-11 Napra Co., Ltd. Substrate for electronic device and electronic device
CN103534805B (zh) 2011-05-16 2016-08-24 丰田自动车株式会社 功率模块
KR101926854B1 (ko) 2012-02-09 2018-12-07 후지 덴키 가부시키가이샤 반도체 장치
JP2014045157A (ja) 2012-08-29 2014-03-13 Hitachi Automotive Systems Ltd パワー半導体モジュール
JP2015015302A (ja) 2013-07-03 2015-01-22 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
WO2016007120A1 (en) 2014-07-07 2016-01-14 Intel IP Corporation Package-on-package stacked microelectronic structures
WO2016024333A1 (ja) 2014-08-12 2016-02-18 新電元工業株式会社 半導体モジュール
EP3208838B1 (en) 2014-10-16 2021-11-24 Shindengen Electric Manufacturing Co., Ltd. Semiconductor module
JP6689708B2 (ja) * 2016-08-10 2020-04-28 ルネサスエレクトロニクス株式会社 電子装置
KR102497572B1 (ko) * 2018-07-03 2023-02-09 삼성전자주식회사 반도체 패키지 및 그의 제조 방법

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004335624A (ja) * 2003-05-06 2004-11-25 Hitachi Ltd 半導体モジュール
JP2006310649A (ja) * 2005-04-28 2006-11-09 Sharp Corp 半導体装置パッケージおよびその製造方法、ならびに半導体装置パッケージ用一括回路基板
KR100656587B1 (ko) * 2005-08-08 2006-12-13 삼성전자주식회사 금속 포스트를 매개로 연결된 적층 기판을 이용한 적층패키지
JP2007335702A (ja) * 2006-06-16 2007-12-27 Apic Yamada Corp 転写基板の製造方法
CN101911845A (zh) * 2007-12-26 2010-12-08 株式会社藤仓 安装基板及其制造方法
US20090190319A1 (en) * 2008-01-24 2009-07-30 Olympus Corporation Three-dimensional module
US20100133684A1 (en) * 2008-11-28 2010-06-03 Mitsubishi Electric Corporation Power semiconductor module and manufacturing method thereof
JP2012162680A (ja) * 2011-02-08 2012-08-30 Hitachi Chemical Co Ltd 半導体用接着フィルム、接着シート、半導体ウエハ及び半導体装置
CN103515362A (zh) * 2012-06-25 2014-01-15 台湾积体电路制造股份有限公司 堆叠式封装器件和封装半导体管芯的方法
CN104303289A (zh) * 2013-05-13 2015-01-21 新电元工业株式会社 电子模块及其制造方法
CN104347547A (zh) * 2013-07-26 2015-02-11 日月光半导体制造股份有限公司 半导体封装件及其的制造方法
CN205122571U (zh) * 2014-08-27 2016-03-30 株式会社村田制作所 导电柱
KR20170096945A (ko) * 2016-02-17 2017-08-25 가부시기가이샤 디스코 반도체 패키지 및 반도체 패키지의 제조 방법

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
曾光龙: "FR-4覆铜板常见缺陷与解决方法 ", 《印制电路信息》 *

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